CN111933738B - 基于分子束外延技术的自成结光电探测器及其制备方法 - Google Patents
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Abstract
本发明提供一种基于分子束外延技术的自成结半导体光电探测器及其制备方法，属于光电探测器件领域。本发明制备的光电探测器采用非对称PIN浅结结构，将Sb原子在分子束外延设备腔体内采用高温原位掺杂的方法掺杂进Ge薄膜中，将Ge改性为N型半导体；全程制备过程均在分子束外延设备腔体中进行，这样就大大减小了外来杂质的污染，简化了光电探测器制作工艺的流程，且相比传统的离子注入的掺杂方法，该方法不会破坏晶体的晶格结构。
Description
技术领域
本发明属于光电探测器件领域，具体涉及一种基于分子束外延技术的自成结半导体光电探测器及其制备方法。
背景技术
光通信近年来飞速发展，而光电探测器是将光信号转化为电信号的重要器件之一，制备具有高量子效率、低暗电流、高响应度和高频率带宽的光电探测器，并实现Si基光电集成接收芯片一直是相关领域科研工作者重点研究方向。基于InP等Ⅲ-Ⅴ族半导体材料制备的探测器暗电流小，但其价格昂贵、导热性能和机械性能较差，并且与Si工艺兼容性较差，故在Si基光电集成技术中的应用受到了限制。GaAs是目前常见的红外半导体材料，然而它的截止波长仅在0.86μm，已经不能满足下一代红外探测的带宽和波段需求。因此，如何在保证相关性能的基础上，制备与Si工艺兼容性较好、价格便宜、可重复性高、制备简单的光电探测器是一个值得研究的课题。
Ge作为和Si同族的半导体材料，直接带隙约为0.67eV，自身的截止波长为1.3μm，对光通信中的C波段信号具有良好的响应特性。近年来，GeR(R为Si、Sn、Bi等)材料应用越来越多，其中一个重要应用便是在光电探测领域，Su S等人(Su S,Cheng B,Xue C,etal.GeSn pin photodetector for all telecommunication bands detection[J].Opticsexpress,2011,19(7):6400-6405.)以n型硅单晶作为衬底，利用分子束外延技术先制备GeSn薄膜或Ge缓冲层作为i层，再生长一层GeSn薄膜，最后再利用磁控溅射掺杂硼原子将其改性为p型半导体，进而构成p-i-n结半导体光电探测器。但是采用这种方法制备的光电探测器，一方面由于GeSn材料本身的限制，导致其探测波长具有一定的局限性，暗电流相对于光电流较大；另一方面，这种方法制成的光电探测器制备方法复杂，需要多次将基片拿出，不可避免的带来很多污染，这对半导体材料性能也有一定的影响，比如暗电流等。
因此，如何基于一种新的材料和工艺实现与Si工艺兼容性较好的半导体光电探测器的制备成为了亟待解决的问题。
发明内容
针对背景技术所存在的问题，本发明的目的在于提供一种基于GeSb/GeSn薄膜的P-N结半导体光电探测器及其制备方法，该光电探测器采用分子束外延方法制备，在制备过程中原位生长形成非对称PIN浅结结构，制备过程简单易操作，可重复性强。
为实现上述目的，本发明的技术方案如下：
一种基于分子束外延技术的自成结光电探测器，其特征在于，从下至上依次为P型单晶Si衬底、GeSn薄膜、Ge1-x Sbx薄膜和电极，所述GeSn薄膜厚度为60～120nm，所述Ge1-xSbx薄膜为N型半导体薄膜，厚度为60～120nm，其中，0.05≤x≤0.20。
一种基于分子束外延技术的自成结光电探测器的制备方法，包括以下步骤：
步骤1.选择<100>晶向的P型单晶Si衬底，并进行清洗；
步骤2.在步骤1清洗后的Si衬底表面采用分子束外延方法沉积GeSn薄膜，其中，GeSn薄膜的厚度为60～120nm；
步骤3.在步骤2沉积的GeSn薄膜表面采用双源双控方法，生长Ge1-x Sbx薄膜，其中，0.01≤x≤0.14，薄膜厚度为60～120nm；
步骤4在步骤3沉积的Ge1-x Sbx薄膜表面采用光刻并结合反应离子束刻蚀的方法制备Ti/Au电极，即可得到所述半导体光电探测器。
进一步地，步骤1中Si衬底清洗的具体过程为：衬底采用浓度为10％浓度的盐酸在100℃～120℃下超声清洗10～20min，再经过10％浓度的氢氧化钠溶液在100℃～120℃下超声清洗10～20min，再经过丙酮、酒精以及去离子水分别依次超声清洗，得到粗糙度小于0.5nm且洁净度高的P型单晶硅基片。
进一步地，步骤2中采用分子束外延方法沉积GeSn薄膜的具体过程为：
步骤2.1、将步骤1中清洗后的P型单晶硅衬底放入分子束外延设备的腔室内，抽真空，至腔室气压为1～10^10-10Torr；
步骤2.2、加热衬底至150～250℃，保持40～50min，以去除其表面附着的气体与杂质；
步骤2.3、将反应源锗源和锡源分别升温至1200～1350℃和800～1050℃，然后将衬底升温至250～400℃；
步骤2.4、打开锡源和锗源的挡板，待束流稳定后，打开衬底挡板，在衬底上沉积GeSn薄膜，沉积反应结束后，关闭衬底挡板以及锡源和锗源的挡板，即可在硅衬底表面得到60～120nm厚的GeSn薄膜。
进一步地，步骤2.2中的加热衬底的升温速率为3～5℃/min；步骤2.3中锗源的体积百分比纯度高于99.99％，升温速率为5～7℃/min；锡源的体积百分比纯度高于99.99％，升温速率为3～5℃/min；衬底的升温速率为3～5℃/min；步骤2.4中的沉积反应时间为60～120min。
进一步地，步骤3中采用分子束外延方法沉积Ge1-x Sbx薄膜的具体过程为：
步骤3.1、打开锗源的挡板，待束流稳定后，打开衬底挡板，在到GeSn薄膜表面沉积Ge薄膜，沉积反应结束后，关闭衬底挡板以及锗源的挡板，关闭衬底加热装置，冷却降温；
步骤3.2、将反应源锑源升温至200～400℃，待衬底温度降至150～250℃，打开锑源的挡板，等待束流稳定，打开衬底挡板，反应60min；
步骤3.3、将衬底温度设定为800～1000℃，保持60～180min，使得锑原子进入锗薄膜的晶格中，完成N型掺杂；
步骤3.4、掺杂反应结束后，冷却降至室温，即可在GeSn薄膜表面得到60～120nm厚的Ge1-x Sbx薄膜。
综上所述，由于采用了上述技术方案，本发明的有益效果是：
1.本发明光电探测器采用非对称PIN浅结结构，将Sb原子在分子束外延设备腔体内采用高温原位掺杂的方法掺杂进Ge中，将Ge改性为N型半导体；同时Sb的掺杂可以促进GeSb薄膜晶化，得到很好的单晶薄膜，减少薄膜的缺陷，提高材料的电子迁移率极大程度降低器件的暗电流；I层薄膜设计用于在一定程度上增加耗尽层的宽度，大量吸收光子，使得光电探测材料产生大量的电子空穴对，产生更大的光电流强度，用于提升器件性能。
2.本发明基于分子束外延方法制备器件主体结构，通过在P型Si基片上通过分子束外延技术生长高质量的GeSn和GeSb薄膜，制备过程中对Ge的N型掺杂改性全过程均在分子束外延设备腔体中进行，这样就大大减少了外来杂质的污染，简化了光电探测器制作工艺的流程，且相比传统的离子注入的掺杂方法，该方法不会破坏晶体的晶格结构；除此之外，该方法可以在一定程度上突破材料本身的固溶度限制，通过调控生长时间和扩散时间及温度，可以较好的实现对掺杂浓度和结深度的控制，从而使得制作出来的光电探测器件性能参数可调范围增大。
3.本发明利用分子束外延技术，可以方便的生产大尺寸晶圆级的薄膜结构，配合后续的光刻和刻蚀工艺，更为简便地制备出与现有Si工艺兼容性较好的器件；而且，本发明涉及的制备方法工艺简单，成本低，可重复性高，无毒，低污染，具有良好的应用潜力。
附图说明
图1为本发明提供的基于分子束外延技术的自成结光电探测器结构示意图。
图2为本发明制备方法工艺流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面结合实施方式和附图，对本发明作进一步地详细描述。
一种基于分子束外延技术的自成结光电探测器，其结构示意图如图1所示，从下至上依次为P型单晶Si衬底、GeSn薄膜、Ge1-x Sbx薄膜和电极，所述Ge1-x Sbx薄膜为N型半导体薄膜，其中，0.05≤x≤0.14。
实施例1
一种基于分子束外延技术的自成结光电探测器的制备方法，工艺流程图如图2所示，包括以下步骤：
步骤1、选择<100>晶向的P型单晶硅衬底(R＝0.1～1.0Ω.cm)，经过10％浓度的盐酸在100℃下超声清洗15min，再经过10％浓度的氢氧化钠溶液在100℃下超声清洗15min，再经过丙酮、酒精以及去离子水分别依次超声清洗10min，得到粗糙度低且洁净度高的P型单晶硅基片；
步骤2、将步骤1清洗后的P型单晶硅Si衬底放入分子束外延设备腔室中，将腔室真空抽至10-10Torr，然后以3℃/min的升温速率将P型单晶硅衬底加热至250℃，保持50min，以去除其表面附着的气体与杂质；
以7℃/min的升温速率将体积百分比纯度高于99.99％的锗源加热至1200℃，以5℃/min的升温速率将体积百分比纯度高于99.99％的锡源加温到1000℃，以3℃/min的升温速率将衬底升温至400℃；
打开锡源和锗源的挡板，等待束流稳定，打开衬底挡板，生长溅射4h，然后关闭衬底挡板以及锡源和锗源的挡板，并关闭衬底加热装置，即可在衬底表面得到240nm厚的GeSn薄膜；
步骤3.在步骤2沉积的GeSn薄膜表面采用双源双控方法，生长厚度为60nm的Ge0.94Sb0.06薄膜，具体过程为：
将衬底温度设置为350℃，打开锗源的挡板，待束流稳定后，打开衬底挡板，在GeSn薄膜表面沉积Ge薄膜，沉积反应结束后，关闭衬底挡板以及锗源的挡板，关闭衬底加热装置，冷却降温；
以5℃/min的升温速率将体积百分比纯度高于99.99％的锑源加温到200℃，打开锑源的挡板，等待束流稳定，打开衬底挡板，反应生长60min；关闭衬底挡板以及锗源和锑源的挡板，关闭锗源和锑源的加热电源；
将衬底温度设定为800℃，保持120min，使得锑原子进入锗薄膜的晶格中，完成N型掺杂；然后以3℃/min的速率将衬底温度降到室温，即可在GeSn薄膜表面得到60nm厚的Ge0.94 Sb0.06薄膜。
步骤4在步骤3沉积的Ge0.94 Sb0.06薄膜表面采用光刻和反应离子束刻蚀相结合，制备Ti/Au电极，即可得到所述半导体光电探测器。
实施例2
按照实施例1的制备方法制备半导体光电探测器，仅将步骤3中的锑源温度调整为250℃，得到Ge0.92 Sb0.08薄膜，其余步骤与实施例1相同。
实施例3
按照实施例1的制备方法制备半导体光电探测器，仅将步骤3中的锑源温度调整为300℃，得到Ge0.90 Sb0.10薄膜，其余步骤与实施例1相同。
实施例4
按照实施例1的制备方法制备半导体光电探测器，仅将步骤3中的锑源温度调整为350℃，得到Ge0.88 Sb0.12薄膜，其余步骤与实施例1相同。
实施例5
按照实施例1的制备方法制备半导体光电探测器，仅将步骤3中的锑源温度调整为400℃，得到Ge0.86 Sb0.14薄膜，其余步骤与实施例1相同。
通过调节锑源的温度，控制锑源的蒸发速率和生长速度，从而实现Ge1-x Sbx薄膜中Sb的含量的调节，即掺杂S原子的浓度。随着Sb含量的增加，所形成的结深度也会增加。Sb含量的不同会对所制备的半导体薄膜载流子浓度、电阻率等都有影响，进而会影响所制成的半导体光电探测器的性能参数，如暗电流等。
以上所述，仅为本发明的具体实施方式，本说明书中所公开的任一特征，除非特别叙述，均可被其他等效或具有类似目的的替代特征加以替换；所公开的所有特征、或所有方法或过程中的步骤，除了互相排斥的特征和/或步骤以外，均可以任何方式组合。
Claims (3)
1.一种基于分子束外延技术的自成结光电探测器，其特征在于，从下至上依次为P型单晶Si衬底、GeSn薄膜、Ge1-xSbx薄膜和电极，所述GeSn薄膜厚度为60～120nm，所述Ge1-xSbx薄膜为N型半导体薄膜，厚度为60～120nm，其中，0.05≤x≤0.20；所述自成结光电探测器采用非对称PIN浅结结构，按照以下步骤制备：
步骤1.清洗P型单晶Si衬底；
步骤2.在步骤1清洗后的Si衬底表面采用分子束外延技术沉积GeSn薄膜，其中，GeSn薄膜的厚度为60～120nm，具体制备过程为：
步骤2.1、将步骤1中清洗后的P型单晶硅衬底放入分子束外延设备的腔室内，抽真空，至腔室气压为1～10^10-10Torr；
步骤2.2、加热衬底至150～250℃，保持40～50min；
步骤2.3、将反应源锗源和锡源分别升温至1200～1350℃和800～1050℃，然后将衬底升温至250～400℃；
步骤2.4、打开锡源和锗源的挡板，待束流稳定后，打开衬底挡板，在衬底上沉积GeSn薄膜，沉积反应结束后，关闭衬底挡板以及锡源和锗源的挡板，即可在硅衬底表面得到60～120nm厚的GeSn薄膜；
步骤3.在步骤2沉积的GeSn薄膜表面采用分子束外延技术生长Ge1-xSbx薄膜，其中，0.05≤x≤0.14，具体制备过程为：
步骤3.1、打开锗源的挡板，待束流稳定后，打开衬底挡板，在到GeSn薄膜表面沉积Ge薄膜，沉积反应结束后，关闭衬底挡板以及锗源的挡板，关闭衬底加热装置，冷却降温；
步骤3.2、将反应源锑源升温至200～400℃，待衬底温度降至150～250℃，打开锑源的挡板，等待束流稳定，打开衬底挡板，反应60min；
步骤3.3、将衬底温度设定为800～1000℃，保持60～180min，使得锑原子进入锗薄膜的晶格中，完成N型掺杂；
步骤3.4、掺杂反应结束后，冷却降至室温，即可在GeSn薄膜表面得到60～120nm厚的Ge1-xSbx薄膜；
步骤4.在步骤3沉积的Ge1-xSbx薄膜表面制备电极，即可得到所述自成结光电探测器。
2.如权利要求1所述自成结光电探测器的制备方法，其特征在于，步骤1中P型单晶硅Si衬底清洗的具体过程为：衬底先在100℃～120℃下的盐酸中超声清洗10～20min，再在100℃～120℃下的氢氧化钠溶液中超声清洗10～20min，最后经丙酮、酒精以及去离子水分别依次超声清洗，得到粗糙度小于0.5nm的P型单晶硅衬底。
3.如权利要求1所述自成结光电探测器的制备方法，其特征在于，步骤2.2中衬底的升温速率为3～5℃/min；步骤2.3中锗源的升温速率为5～7℃/min；锡源的升温速率为3～5℃/min；衬底的升温速率为3～5℃/min；步骤2.4中的沉积反应时间为60～120min。
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