CN111900210A - Thin film transistor, display substrate and display device - Google Patents
Thin film transistor, display substrate and display device Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 92
- 239000000758 substrate Substances 0.000 title claims abstract description 48
- 239000000463 material Substances 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 79
- 238000000034 method Methods 0.000 description 9
- 238000002360 preparation method Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000007769 metal material Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
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- 238000005530 etching Methods 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The utility model provides a thin film transistor, display substrate and display device belongs to and shows technical field, and it can solve the great technical problem of current thin film transistor leakage current. The thin film transistor of the present disclosure includes: the transistor comprises a substrate, an active layer, a grid electrode, a source electrode and a drain electrode, wherein the active layer, the grid electrode, the source electrode and the drain electrode are positioned on the substrate; the grid electrode is provided with one or more hollow structures; the grid is divided into a plurality of electrically connected sub-grids by a hollow structure; the orthographic projection of each sub-grid electrode on the substrate is partially overlapped with the orthographic projection of the active layer on the substrate.
Description
Technical Field
The disclosure belongs to the technical field of display, and particularly relates to a thin film transistor, a display substrate and a display device.
Background
The performance of the tft, which is an important electrical device in a display device, directly affects the display effect and the service life of the display device.
The inventors found that at least the following problems exist in the related art: in the current display device, the thin film transistor has a large leakage current in an off state, so that a display image is prone to have poor image sticking and the display effect is affected. In addition, in the using process, if only a small part of circuits in the thin film transistors are in failure, the whole thin film transistor and other adjacent thin film transistors can not be normally used easily, and the service lives of the thin film transistors and the display device are influenced.
Disclosure of Invention
The present disclosure is directed to at least one of the problems of the related art, and provides a thin film transistor, a display substrate and a display device.
The technical scheme adopted for solving the technical problem of the present disclosure is a thin film transistor, comprising: the transistor comprises a substrate, an active layer, a grid electrode, a source electrode and a drain electrode, wherein the active layer, the grid electrode, the source electrode and the drain electrode are positioned on the substrate;
the grid electrode is provided with one or more hollow structures; the grid is divided into a plurality of electrically connected sub-grids by the hollow structure; the orthographic projection of each sub-gate on the substrate is overlapped with the orthographic projection of the active layer on the substrate.
Optionally, the plurality of sub-gates are all disposed on a side of the active layer away from the substrate, and are all disposed in an insulating manner with the active layer.
Optionally, a plurality of the sub-grids are of an integrally molded structure.
Optionally, the active layer includes a plurality of channel regions, and a source contact region and a drain contact region are disposed on two sides of each channel region; the number of the channel regions is equal to that of the sub-gates;
and the ion doping concentration of the source electrode contact region and the drain electrode contact region is greater than that of the channel region.
Optionally, the width-to-length ratio of the channel region is less than or equal to 1: 2.
optionally, a light-shielding layer is disposed on one side of the active layer close to the substrate;
the light shielding layer is at least partially overlapped with the projection of the active layer on the substrate.
Optionally, the material of the active layer includes any one of amorphous silicon, polysilicon, and metal oxide.
The technical scheme adopted for solving the technical problem of the present disclosure is a display substrate, which comprises a plurality of pixel units arranged in an array, wherein each pixel unit comprises the thin film transistor provided as above.
Optionally, a plurality of the sub-gates in the pixel units in the same row are connected to form a gate bar;
the grid bars in the pixel units in the same row are connected with the same signal line; the grid bars and the connected signal lines are arranged on the same layer and are made of the same material.
The technical scheme adopted for solving the technical problem of the present disclosure is a display device, which comprises the display substrate provided as above.
Drawings
FIG. 1 is a schematic plan view of a thin film transistor according to the related art;
fig. 2 is a schematic plane structure diagram of a thin film transistor according to an embodiment of the present disclosure;
fig. 3 is a schematic plane structure diagram of a failed tft according to an embodiment of the present disclosure;
fig. 4 is a schematic cross-sectional structure view of the thin film transistor in fig. 2 along a direction a-a according to an embodiment of the present disclosure.
Detailed Description
For a better understanding of the technical aspects of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
It should be noted that, in the embodiments of the present disclosure, the "same layer" refers to a layer structure formed by forming a film layer for forming a specific pattern by using the same film forming process and then performing a one-step patterning process by using the same mask. The sequential patterning process may include multiple exposure, development or etching processes depending on the specific pattern, and the specific pattern of the formed layer may be continuous or discontinuous, and may be at different heights or have different thicknesses. In the embodiment of the present disclosure, the thin film transistor may be an N-type thin film transistor, or may be a P-type thin film transistor; the N-type thin film transistor is characterized in that N-type ion doping is carried out on an active layer of the thin film transistor; the P-type thin film transistor refers to P-type ion doping on an active layer of the thin film transistor. The working level signal of the N-type thin film transistor is a high level signal; the working level signal of the P-type thin film transistor is a low level signal. In the following embodiments, the thin film transistor is described as an N-type thin film transistor, but the embodiments of the present disclosure are not limited to the N-type thin film transistor.
Fig. 1 is a schematic plan view illustrating a thin film transistor in the related art, and for convenience of understanding, fig. 1 shows two thin film transistors having the same structure, and as shown in fig. 1, the thin film transistor includes: a substrate (not shown), an active layer 101 on the substrate, a gate electrode 102, a source electrode (not shown), and a drain electrode (not shown), wherein the gate electrode 102 covers a portion of the active layer 102, the covered portion of the active layer 102 may serve as a channel region 1011, and the uncovered portion of the active layer 102 may serve as a source contact region 1012 and a drain contact region 1013, which may be connected to a source electrode and a drain electrode of the thin film transistor, respectively. Due to process limitation, in the prior art, the thin film transistor has a large leakage current in an off state, so that a display image in the display device is prone to have poor image sticking and the display effect is affected. In addition, in the using process, if only a small part of circuits in the gate 102 of the thin film transistor are failed, the whole thin film transistor and other adjacent thin film transistors cannot be normally used, and the service lives of the thin film transistor and the display device are affected. In order to solve one of the above technical problems in the related art, embodiments of the present disclosure provide a thin film transistor, a display substrate and a display device. The thin film transistor, the display substrate, and the display device in the embodiments of the present disclosure will be described below with reference to the drawings, but the present disclosure is not limited to these specific embodiments.
Example one
Fig. 2 is a schematic plan view of a thin film transistor provided in an embodiment of the present disclosure, and for ease of understanding, fig. 2 shows two thin film transistors with the same structure, and as shown in fig. 2, the thin film transistor: a substrate (not shown), an active layer 101 on the substrate, a gate electrode 102, a source electrode (not shown), and a drain electrode (not shown); the gate 102 has one or more hollow structures 1021; the gate 102 is divided into a plurality of electrically connected sub-gates 1022 by a hollow structure 1021; an orthographic projection of each sub-gate 1022 on the substrate is partially overlapped with an orthographic projection of the active layer 101 on the substrate.
In the thin film transistor provided by the embodiment of the disclosure, the gate 102 has one or more hollow structures 1021, the gate 102 may be divided into a plurality of electrically connected sub-gates 1022 by the hollow structures 1021, each sub-gate 1022 may cover a portion of the active layer 101, and the source and the drain are connected to two ends of the active layer 101, so that a portion corresponding to each sub-gate 1022 may form one thin film transistor, and a plurality of thin film transistors may be formed in a region where only one thin film transistor is originally formed. In the off state, the active layers 101 of the plurality of thin film transistors may be shunted, so that the leakage current of each thin film transistor may be reduced, and thus, poor image sticking of a display screen in the display device may be avoided, thereby improving the display effect. As shown in fig. 3, assuming that only part of the sub-gates 1022 of the tft fails, since other parts of each sub-gate 1022 can still be electrically connected, the input high-level signal can still be transmitted to each sub-gate 1022, so that each sub-gate 1022 keeps the same potential, and thus, the tft corresponding to the failed sub-gate 1022 can still receive the input high-level signal and keep the normal operation state. Therefore, even if a small part of circuits in the sub-gates 1022 of the thin film transistors are broken down during use, normal use of the thin film transistors is not affected, and the service lives of the thin film transistors and the display device can be prolonged.
In some embodiments, fig. 4 is a schematic cross-sectional view of the thin film transistor in fig. 2 along the a-a direction according to an embodiment of the disclosure, and as shown in fig. 4, a plurality of sub-gates 1022 are disposed on a side of the active layer 101 away from the substrate and are disposed in an insulating manner from the active layer 101.
It should be noted that the active layer 101 is formed on the substrate, the gate insulating layer covers the active layer 101, each sub-gate 1022 is formed on the gate insulating layer, the gate insulating layer can insulate the active layer 101 and each sub-gate 1022 from each other, when a high-level signal is applied to each electrically connected sub-gate 1022, an electric field is generated in the gate insulating layer, and induced charges are generated on a side surface of the active layer 101 close to the sub-gate 1022. With the application of a high-level signal on each sub-gate 1022, a depletion layer on the surface of the active layer 101 near the sub-gate 1022 is converted into an electron accumulation layer to form an inversion layer, and when the inversion layer is strongly inverted (i.e., when a turn-on voltage is reached), carriers pass through the active layer 101 when a voltage is applied between the source and the drain, so that the thin film transistor is in an on state. In the embodiment of the present disclosure, the gate 102 includes a plurality of sub-gates 1022 electrically connected, and if a small part of the sub-gates 1022 of the thin film transistor fails, since other parts of each sub-gate 1022 can still be electrically connected, the input high level signal can still be transmitted to each sub-gate 1022, so that each sub-gate 1022 keeps the same potential, and thus, the thin film transistor corresponding to the sub-gate 1022 with the failure can still receive the input high level signal, and maintain a normal operation state. Therefore, even if a small part of circuits in the sub-gates 1022 of the thin film transistors are broken down during use, normal use of the thin film transistors is not affected, and the service lives of the thin film transistors and the display device can be prolonged. In practical applications, each sub-gate 1022 may be made of a metal material such as aluminum, and the source and the drain are disposed in the same layer and may be made of a metal material such as copper. It is understood that the preparation materials of the electrodes in the thin film transistor can be reasonably selected according to actual needs, and are not listed here.
In some embodiments, the plurality of sub-gates 1022 are a unitary structure.
In the manufacturing process, an integral gate 102 may be formed first, and one or more hollow structures 1021 may be formed on the gate 102 through a patterning process, so as to divide the gate 102 into a plurality of sub-gates 1022, thereby forming an integrated structure. Thus, the preparation steps can be reduced, and the preparation cost can be saved. It is understood that each sub-gate 1022 can be independently fabricated according to actual requirements.
In some embodiments, the active layer 101 includes a plurality of channel regions 1011, each channel region 1011 having disposed on either side thereof a source contact region 1012 and a drain contact region 1013; the number of channel regions 1011 is equal to the number of sub-gates 1022; the ion doping concentration of both the source contact region 1012 and the drain contact region 1013 is greater than the ion doping concentration of the channel region 1013.
It should be noted that the sub-gate 1022 may cover a portion of the active layer 101, a portion of the active layer covered by the sub-gate 1022 may form a channel region 1011, and a portion of the active layer on both sides of the channel region 1011 and not covered by the sub-gate 1022 may form a source contact region 1012 and a drain contact region 1013, such that the number of the channel regions 1011 is equal to the number of the sub-gates 1022, thereby forming a plurality of thin film transistors corresponding to the number of the sub-gates 1022. The ion doping concentration of the source contact region 1012 and the drain contact region 1013 is greater than the ion doping concentration of the channel region 1011, which is advantageous in that the source contact region 1012 and the drain contact region 1013 of the active layer 101 have good ohmic contact with the source and the drain connected thereto, respectively. Specifically, the active layer 101 may be channel-doped after the active layer 101 is patterned for the first time to adjust the threshold voltage Vth of the thin film transistor. After the sub-gates 1022 are patterned, the source and drain contact regions 1012 and 1013 of the active layer 1011 are heavily doped such that the ion doping concentration of the source and drain contact regions 1012 and 1013 forming the active layer 101 is greater than the ion doping concentration of the channel region 1011.
In some embodiments, the width to length ratio of the channel region 1011 is less than or equal to 1: 2.
it should be noted that the aspect ratio of the channel region 1011 may affect the magnitude of the leakage current of the thin film transistor, and the corresponding relationship between the size of the channel region 1011 and the leakage current is shown in the following table:
as can be seen from the above table, in a certain range, in the case where the width W of the channel region 1011 is not changed, the leakage current of the thin film transistor can be reduced by increasing the length L of the channel region 1011, that is, by decreasing the aspect ratio. However, when the length L of the channel region 1011 is increased to a certain value, the contribution to reduction of the leakage current of the thin film transistor is small, or the leakage current of the thin film transistor cannot be reduced. In the disclosed embodiment, the width-to-length ratio of the channel region 1011 is generally controlled to be 1: 2, thereby achieving the effect of reducing the leakage current of the thin film transistor. While also avoiding unnecessary material waste by excessively increasing the length L of the channel region 1011. It is understood that the width and length of the channel region 1011 of the active layer 101 in the thin film transistor in the above table are merely exemplary and do not represent the actual width and length of the channel region 1011 of the active layer 101 in the thin film transistor provided by the embodiment of the present disclosure.
In some embodiments, a light-shielding layer is disposed on a side of the active layer 101 close to the substrate; the light-shielding layer at least partially overlaps the projection of the active layer 101 on the substrate.
It should be noted that, on the side of the active layer 101 away from the substrate, the channel region 1011 of the active layer 101 may be shielded by each sub-gate 1022, so as to prevent external ambient light from irradiating the channel region 1011 of the active layer 101 away from the substrate side, which may affect the performance of the thin film transistor. The active layer is close to one side of the substrate and can be shielded by the light shielding layer, so that external ambient light is prevented from being irradiated onto the channel region 1011 of the active layer 101 from the substrate side, and the performance of the thin film transistor is prevented from being influenced. The material of the light shielding layer may adopt a light shielding metal material, including but not limited to molybdenum Mo. It can be understood that the thin film transistor provided in the embodiment of the present disclosure is a top gate thin film transistor, and certainly, the thin film transistor may also be a bottom gate thin film transistor, and the implementation principle of the thin film transistor is similar to that of the top gate thin film transistor, and is not described herein again. It should be further noted that the thin film transistor provided in the embodiment of the present disclosure may further include, in addition to the above-mentioned film layer structures, other film layers such as a blocking layer, a buffer layer, a planarization layer, and an interlayer insulating layer, the structures and functions of which are the same as those of the film layers in the related art, and the thin film transistor may be prepared and formed by using the preparation process in the related art, which is not described herein again.
In some embodiments, the material of the active layer 101 includes any one of amorphous silicon, polysilicon, and metal oxide.
It should be noted that the material of the active layer 101 may be amorphous silicon, polysilicon, or metal oxide, so as to form a polysilicon thin film transistor, or an oxide thin film transistor, and the material of the active layer 101 may be selected reasonably according to actual needs. Of course, the material of the active layer 101 may also be other materials having semiconductor function, and is not listed here.
Example two
The embodiment of the present disclosure provides a display substrate, which includes a plurality of pixel units arranged in an array, where each pixel unit includes the thin film transistor provided in the above embodiment.
The thin film transistor may be a switching transistor in a pixel unit, or may be a driving transistor in a pixel unit, and is not limited herein. Since the display substrate in the embodiment of the disclosure includes any one of the above thin film transistors, the leakage current of the thin film transistor is small, and the performance of the display substrate is good.
In some embodiments, the plurality of sub-gates in the pixel units in the same row are connected to form a gate bar; grid bars positioned in the same row of pixel units are connected with the same signal line; the grid bars and the connected signal lines are arranged in the same layer and are made of the same material.
It should be noted that, the same material and the same process may be adopted to prepare each sub-gate in each pixel unit, and connect the plurality of sub-gates in the same row of pixel units to form a gate bar, so as to ensure that the electrical signals input on each sub-gate are the same when the scanning signal is input. And the grid bars and the connected signal wires can be arranged on the same layer and made of the same material, so that the preparation steps can be reduced in the preparation process, and the preparation cost is saved.
EXAMPLE III
The embodiment of the present disclosure provides a display device, which includes the display substrate provided in the above embodiment. It can be understood that the display device may be a terminal device such as a mobile phone, a computer, a smart television, or a smart watch. The thin film transistor in the display panel of the display device adopts the thin film transistor, so that the leakage current is small, and the display effect is excellent.
It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.
Claims (10)
1. A thin film transistor, comprising: the transistor comprises a substrate, an active layer, a grid electrode, a source electrode and a drain electrode, wherein the active layer, the grid electrode, the source electrode and the drain electrode are positioned on the substrate;
the grid electrode is provided with one or more hollow structures; the grid is divided into a plurality of electrically connected sub-grids by the hollow structure; the orthographic projection of each sub-gate on the substrate is overlapped with the orthographic projection of the active layer on the substrate.
2. The thin film transistor of claim 1, wherein the plurality of sub-gates are disposed on a side of the active layer away from the substrate and are insulated from the active layer.
3. The thin film transistor of claim 1, wherein a plurality of the sub-gates are of a unitary structure.
4. The thin film transistor according to claim 1, wherein the active layer comprises a plurality of channel regions each provided with a source contact region and a drain contact region on both sides; the number of the channel regions is equal to that of the sub-gates;
and the ion doping concentration of the source electrode contact region and the drain electrode contact region is greater than that of the channel region.
5. The thin film transistor according to claim 4, wherein a width-to-length ratio of the channel region is less than or equal to 1: 2.
6. the thin film transistor according to claim 1, wherein a light-shielding layer is provided on a side of the active layer adjacent to the substrate;
the light shielding layer is at least partially overlapped with the projection of the active layer on the substrate.
7. The thin film transistor according to claim 1, wherein a material of the active layer comprises any one of amorphous silicon, polycrystalline silicon, and a metal oxide.
8. A display substrate comprising a plurality of pixel units arranged in an array, each of the pixel units comprising a thin film transistor according to any one of claims 1 to 7.
9. The display substrate according to claim 8, wherein the plurality of sub-gates in the pixel units in the same row are connected to form a gate bar;
the grid bars in the pixel units in the same row are connected with the same signal line; the grid bars and the connected signal lines are arranged on the same layer and are made of the same material.
10. A display device comprising the display substrate according to any one of claims 8 or 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010799880.9A CN111900210A (en) | 2020-08-11 | 2020-08-11 | Thin film transistor, display substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010799880.9A CN111900210A (en) | 2020-08-11 | 2020-08-11 | Thin film transistor, display substrate and display device |
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| CN112563141A (en) * | 2020-12-10 | 2021-03-26 | 武汉天马微电子有限公司 | Thin film transistor array substrate, manufacturing method thereof, display panel and display device |
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