CN112563141A - Thin film transistor array substrate, manufacturing method thereof, display panel and display device - Google Patents
Thin film transistor array substrate, manufacturing method thereof, display panel and display device Download PDFInfo
- Publication number
- CN112563141A CN112563141A CN202011434580.7A CN202011434580A CN112563141A CN 112563141 A CN112563141 A CN 112563141A CN 202011434580 A CN202011434580 A CN 202011434580A CN 112563141 A CN112563141 A CN 112563141A
- Authority
- CN
- China
- Prior art keywords
- thin film
- layer
- silicon
- interface
- ions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 135
- 239000000758 substrate Substances 0.000 title claims abstract description 91
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 150000002500 ions Chemical class 0.000 claims abstract description 141
- 239000012535 impurity Substances 0.000 claims abstract description 116
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 83
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 76
- 239000010703 silicon Substances 0.000 claims abstract description 76
- 239000004065 semiconductor Substances 0.000 claims abstract description 52
- 239000010410 layer Substances 0.000 claims description 222
- 238000000034 method Methods 0.000 claims description 25
- 238000002513 implantation Methods 0.000 claims description 16
- 239000002344 surface layer Substances 0.000 claims description 12
- 239000000725 suspension Substances 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims 2
- 239000007924 injection Substances 0.000 claims 2
- 206010047571 Visual impairment Diseases 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 15
- 230000000052 comparative effect Effects 0.000 description 6
- 239000000047 product Substances 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 5
- 230000008034 disappearance Effects 0.000 description 3
- 239000011265 semifinished product Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 108091006149 Electron carriers Proteins 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The application discloses a thin film transistor array substrate, a manufacturing method thereof, a display panel and a display device. The manufacturing method of the thin film transistor array substrate comprises the following steps: providing a semi-finished semiconductor product, wherein the semi-finished semiconductor product comprises a substrate, a silicon-based thin film layer and an insulating layer which are stacked on the substrate, and an interface is arranged between the silicon-based thin film layer and the insulating layer; and doping impurity ions in the channel region of the silicon-based thin film layer to form a channel doped region, and enabling the impurity ions to be combined with the dangling bonds in the interface. According to the thin film transistor array substrate, the afterimage phenomenon of the display panel can be reduced, and the display quality is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a thin film transistor array substrate, a manufacturing method thereof, a display panel and a display device.
Background
Before the display panel is shipped, various indexes of the display panel need to be detected, wherein the residual shadow disappearance time is an important index for evaluating the quality of the display panel. The ghost refers to a phenomenon that when a display panel displays one picture for a period of time and is switched to another picture, the previous picture is remnant and can disappear after a period of time.
However, the quality of the thin film transistor in the display panel has an influence on the image sticking of the display panel, and therefore, how to improve the quality of the thin film transistor to reduce the image sticking phenomenon of the display panel is an urgent problem to be solved.
Disclosure of Invention
The application provides a thin film transistor array substrate, a manufacturing method thereof, a display panel and a display device, and aims to improve the quality of a thin film transistor and reduce the afterimage phenomenon of the display panel.
A first aspect of the present application provides a method for manufacturing a thin film transistor array substrate, including the steps of:
providing a semi-finished semiconductor product, wherein the semi-finished semiconductor product comprises a substrate, a silicon-based thin film layer and an insulating layer which are stacked on the substrate, and an interface is arranged between the silicon-based thin film layer and the insulating layer;
and doping impurity ions in the channel region of the silicon-based thin film layer to form a channel doped region, and enabling the impurity ions to be combined with the dangling bonds in the interface.
The second aspect of the present application provides a thin film transistor array substrate, including a substrate, and a silicon-based semiconductor layer, a gate layer, and a source drain layer stacked on the substrate, and the semiconductor layer, the gate layer, and the source drain layer are all insulated by an insulating layer, wherein the semiconductor layer includes a source doped region, a drain doped region, and a channel doped region located between the source doped region and the drain doped region, the insulating layer includes a first insulating layer and a second insulating layer respectively disposed on two opposite surface sides of the semiconductor layer in a stacking direction, interfaces are respectively provided between the semiconductor layer and the first insulating layer and between the semiconductor layer and the second insulating layer, and the interfaces include impurity ions combined with a dangling bond; the grid layer comprises a grid which is arranged corresponding to the channel doping region; the source and drain electrode layer comprises a source electrode and a drain electrode which are arranged at intervals, the source electrode is electrically connected with the source electrode doped region, and the drain electrode is electrically connected with the drain electrode doped region.
A third aspect of the present application provides a display panel comprising a thin film transistor array substrate according to the present application.
A fourth aspect of the present application provides a display device comprising a display panel according to the present application.
According to the thin film transistor array substrate and the manufacturing method thereof, the display panel and the display device provided by the embodiment of the invention, the impurity ions are doped in the channel region of the silicon-based thin film layer, so that the impurity ions are combined with the suspension keys in the interface of the silicon-based thin film layer and the insulating layer to passivate the suspension keys in the interface, thereby improving the defect state of the interface between the silicon-based thin film layer and the insulating layer, improving the quality and stability of the thin film transistor, reducing the afterimage phenomenon of the display panel and improving the display quality of the display panel and the display device.
Drawings
Other features, objects, and advantages of the present application will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a thin film transistor array substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic partial structural diagram of a thin film transistor array substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a thin film transistor array substrate according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a thin film transistor array substrate according to another embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a thin film transistor array substrate according to still another embodiment of the present disclosure;
fig. 6 shows a schematic flowchart of step S120 provided in an embodiment of the present application;
fig. 7 to 9 illustrate corresponding schematic structural diagrams of step S120 in fig. 3;
fig. 10 is a schematic flowchart of step S120 according to another embodiment of the present application;
fig. 11 is a graph showing experimental data of a thin film transistor array substrate provided in the present application and a comparative example;
fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present application;
fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.
In an electronic device such as a mobile phone or a tablet computer, a thin film transistor and other circuit devices are usually manufactured in the electronic device, the thin film transistor includes a silicon-based semiconductor Gate layer and a source drain layer which are arranged in an insulated manner, the silicon-based semiconductor layer includes a source doped region, a drain doped region and a channel doped region located between the source doped region and the drain doped region, in order to realize the insulated arrangement of the silicon-based semiconductor layer and the Gate layer, a Gate Insulator (GI) is arranged between the silicon-based semiconductor layer and the Gate layer, so that electrons in an outermost layer of silicon atoms in the channel doped region located at an interface between the Gate Insulator and the silicon-based semiconductor layer are unstable, so that there are more hanging parts at the interface, and when a high Gate voltage is applied to the thin film transistor during a display process of the display panel, the electrons in the outermost layer of silicon atoms located at the interface are, the threshold voltage is raised, thereby reducing the current; when a low gate voltage is applied to the thin film transistor, electron carriers in the outermost layer of the silicon atoms at the interface are released, and the current rises, so that the afterimage phenomenon of the display panel is influenced, the time for the afterimage to disappear is easily prolonged, and the quality of the display panel is not improved.
In order to solve the above problems, embodiments of the present invention provide a thin film transistor array substrate 100, a method of manufacturing the same, a display panel, and a display device. A thin film transistor array substrate 100, a method of manufacturing the same, a display panel 1000, and a display device 2000 according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
Referring to fig. 1 and 2, fig. 1 is a schematic flow chart illustrating a method for manufacturing a thin film transistor array substrate according to an embodiment of the present disclosure, and fig. 2 is a schematic partial structure diagram illustrating the thin film transistor array substrate according to an embodiment of the present disclosure. The embodiment of the invention provides a manufacturing method of a thin film transistor array substrate, which comprises the following steps:
and S110, providing a semi-finished semiconductor product.
In the present embodiment, the semi-finished semiconductor product includes a substrate 10, and a silicon-based thin film layer 20a and an insulating layer 30 stacked on the substrate 10, with an interface SF between the silicon-based thin film layer 20a and the insulating layer 30. The interface SF is a contact surface between the silicon-based thin film layer 20a and the insulating layer 30. The silicon-based thin film layer 20a includes a source region 22a, a drain region 23a, and a channel region 21a between the source region 22a and the drain region 23 a. By doping the source region 22a, the drain region 23a, and the channel region 21a, respectively, the semiconductor semifinished product can be formed into a semiconductor layer in the thin film transistor.
S120, doping impurity ions into the channel region 21a of the silicon-based thin film layer 20a to form a channel doped region 211, and combining the impurity ions with the dangling bonds in the interface SF.
At the interface SF between the silicon-based thin film layer 20a and the insulating layer 30, the outermost electrons of silicon atoms in the silicon-based thin film layer 20a are unstable and have more dangling bonds. In the embodiment of the present invention, the channel region 21a of the silicon-based thin film layer 20a is doped with the impurity ions, so that the impurity ions are combined with the dangling bonds in the interface SF, the dangling bonds at the interface SF can be passivated, and the stability of the silicon atoms in the channel region 21a of the silicon-based thin film layer 20a is improved, so as to improve the defect state of the interface SF between the silicon-based thin film layer 20a and the insulating layer 30, and improve the quality and stability of the thin film transistor, thereby improving the short-residue capability of the display panel and improving the quality of the display panel. Alternatively, in order to better passivate the dangling bonds at the interface SF, in the impurity ion doping process, a part of the impurity ions is doped from the interface SF into the channel region 21a, and another part of the impurity ions can be doped from the interface SF into the insulating layer 30.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a thin film transistor array substrate according to an embodiment of the present disclosure. Based on the structure of the thin film transistor array substrate 100 shown in fig. 3, in some embodiments, after step S120, the method for manufacturing a thin film transistor array substrate further includes doping impurity ions into the source region 22a and the drain region 23a of the silicon-based thin film layer 20a to form a source doped region 221 and a source doped region 231, where the silicon-based thin film layer 20a forms a semiconductor layer 20b after completing the doping; forming a gate layer 40 on a side of the semiconductor layer 20b facing away from the substrate 10 and forming a source drain layer 50 on a side of the gate layer 40 facing away from the substrate 10, wherein the gate layer 40, the semiconductor layer 20b and the source drain layer 50 are insulated from each other. The source and drain layer 50 includes a source 51 and a drain 52, the source 51 is electrically connected to the source doping region 221 through a via, and the drain 52 is electrically connected to the drain doping region 231 through a via, in which case the thin film transistor is a top gate thin film transistor.
Alternatively, referring to fig. 4, fig. 4 is a schematic structural diagram of a thin film transistor array substrate according to another embodiment of the present disclosure. Based on the structure of the thin film transistor array substrate 100 shown in fig. 4, step S110 is to provide a semiconductor semi-finished product, wherein the semiconductor semi-finished product comprises a substrate 10, and a gate layer 40, a silicon-based thin film layer 20a and an insulating layer 30 which are stacked on the substrate 10, and the gate layer 40 is located between the silicon-based thin film layer 20a and the substrate 10; after step S120, the method for manufacturing the thin film transistor array substrate further includes doping impurity ions into the source region 22a and the drain region 23a of the silicon-based thin film layer 20a to form a source doped region 221 and a source doped region 231, where the silicon-based thin film layer 20a forms a semiconductor layer 20b after completing the doping; and forming a source drain layer 50 on a side of the semiconductor layer 20b away from the substrate 10, wherein the gate layer 40, the semiconductor layer 20b and the source drain layer 50 are arranged in an insulated manner. The source and drain layer 50 includes a source 51 and a drain 52, the source 51 is electrically connected to the source doping region 221 through a via, the drain 52 is electrically connected to the source doping region 231 through a via, and the thin film transistor is a bottom gate thin film transistor.
Since the manufacturing method of doping impurity ions in the silicon-based thin film layer 20a is similar in the top gate thin film transistor and the bottom gate thin film transistor, the top gate thin film transistor array substrate is illustrated herein as an example.
As shown in fig. 5, fig. 5 is a schematic structural diagram of a thin film transistor array substrate according to still another embodiment of the present disclosure. Optionally, after the source and drain layers are manufactured, the manufacturing method of the thin film transistor array substrate may further include forming a planarization layer PLN on a side of the source and drain layers away from the substrate 10, so as to facilitate manufacturing of a subsequent film layer structure of the display panel.
In order to completely passivate dangling bonds in the interface SF, so as to effectively improve the stability of the thin film transistor, in some embodiments, in the step S120, impurity ions are doped into the channel region of the silicon-based thin film layer, and the doping amount of the impurity ions is sufficient to saturate the dangling bonds in the interface.
Referring to fig. 6 to 9 together, fig. 6 shows a flowchart of step S120 according to an embodiment of the present application, and fig. 7 to 9 show structural diagrams corresponding to step S120 in fig. 3. In some embodiments, in the step of providing the semi-finished semiconductor product of step S110, the insulating layer 30 comprises the first insulating layer 31 on a surface side of the silicon-based thin film layer 20a facing the substrate 10, at which time an interface SF between the silicon-based thin film layer 20a and the insulating layer 30 comprises a first interface SF1 between the silicon-based thin film layer 20a and the first insulating layer 31. Based on this, the step S120 of doping the channel region 21a of the silicon-based thin film layer 20a with impurity ions includes:
s121, the channel region 21a is first impurity ion-doped so that the impurity ions are bonded to dangling bonds in the first interface SF 1.
As shown in fig. 7, the impurity ions may be doped by an ion implantation process, and optionally, the implantation energy in the first impurity ion doping is such that the difference Δ T between the thickness T of the silicon-based thin film layer 20a and the target depth T1 is 0nm to 5 nm. Through the arrangement, the impurity ions in the first impurity ion doping process can be well diffused to the first interface SF1, so that the impurity ions are well combined with the suspension bonds at the first interface SF 1. Alternatively, Δ T may be 1nm to 2nm to allow impurity ions to be better diffused to the first interface SF 1.
Optionally, the thickness of the silicon-based thin film layer 20a is 30nm to 50nm, and the implantation energy of the first impurity ion doping is 10KeV to 12 KeV. Through the reasonable arrangement of the thickness of the silicon-based thin film layer 20a and the implantation energy of the first impurity ion doping, the impurity ions in the first impurity ion doping process can be well diffused to the first interface SF1, so that the impurity ions are combined with the suspension bond at the first interface SF 1.
And S123, forming a second insulating layer 32 on the surface side of the silicon-based thin film layer 20a, which is opposite to the substrate 10.
As shown in fig. 8, forming the second insulating layer 32 on the surface side of the silicon-based thin film layer 20a facing away from the substrate 10 can facilitate the insulating arrangement of the silicon-based thin film layer 20a from other film structures. At this time, the interface SF also includes a second interface SF2 between the silicon-based thin film layer 20a and the second insulating layer 32.
S125, the channel region 21a is doped with impurity ions for the second time, so that the impurity ions are combined with dangling bonds in the second interface SF 2.
As shown in fig. 9, the impurity ions may be doped by an ion implantation process, and optionally, the implantation energy in the second impurity ion doping is such that the target depth T2 is 0nm to 5 nm. Through the arrangement, the impurity ions in the second impurity ion doping process can be well diffused to the second interface SF2, so that the impurity ions are well combined with the hanging bonds at the second interface SF 2. Alternatively, T2 may be 1nm to 2nm to better bind the impurity ions to the dangling bonds at the second interface SF 2.
Optionally, the thickness of the second insulating layer 32 is 120nm to 200nm, and the implantation energy of the second impurity ion doping is 38KeV to 40 KeV. Through the reasonable setting of the thickness of the second insulating layer 32 and the implantation energy of the second impurity ion doping, the impurity ions in the second impurity ion doping process can be well diffused to the second interface SF2, so that the impurity ions are combined with the hanging bond at the second interface SF 2.
In the embodiment of the present invention, through the manufacturing method of the thin film transistor array substrate shown in fig. 6, impurity ion doping can be achieved on both the first interface SF1 and the second interface SF2 between the silicon-based thin film layer 20a and the insulating layer 30, so as to passivate dangling bonds on the first interface SF1 and the second interface SF2, improve a defect state of an interface between the silicon-based thin film layer 20a and the insulating layer, improve stability of the thin film transistor, and reduce a ghost phenomenon of the display panel.
Referring to fig. 10, in some embodiments, in the step of providing a semi-finished semiconductor product at step S110, the insulating layer 30 includes a first insulating layer 31 at a surface side of the silicon-based thin film layer 20a facing the substrate 10, and a second insulating layer 32 at a surface side of the silicon-based thin film layer 20a facing away from the substrate 10, the interface SF includes a first interface SF1 between the silicon-based thin film layer 20a and the first insulating layer 31, and a second interface SF2 between the silicon-based thin film layer 20a and the second insulating layer 32; at this time, the step S120 of doping impurity ions into the channel region 21a of the silicon-based thin film layer 20a includes:
s122, the channel region 21a is doped with impurity ions for the first time, so that the impurity ions are bonded to dangling bonds in the first interface SF 1.
In the embodiment of the present invention, an ion implantation process may be adopted to dope impurity ions, and optionally, the implantation energy in the first impurity ion doping is such that the difference Δ T between the thickness T of the silicon-based thin film layer 20a and the target depth T1 is 0nm to 5 nm. Through the arrangement, the impurity ions in the first impurity ion doping process can be well diffused to the first interface SF1, so that the impurity ions are well combined with the suspension bonds at the first interface SF 1. Alternatively, Δ T may be 1nm to 2nm to allow impurity ions to better diffuse to the first interface SF 1; t2 may be 1nm to 2nm to better bind the impurity ions to the dangling bonds at the second interface SF 2.
Optionally, the thickness of the silicon-based thin film layer 20a is 30nm to 50nm, the thickness of the second insulating layer 32 is 120nm to 200nm, and the implantation energy of the first impurity ion doping is 48KeV to 50 KeV. Through the reasonable setting of the thicknesses of the silicon-based thin film layer 20a and the second insulating layer 32 and the implantation energy for the first impurity ion doping, the impurity ions in the first impurity ion doping process can be well diffused to the first interface SF1, so that the impurity ions are combined with the suspension bond at the first interface SF 1.
S124, the channel region 21a is doped with impurity ions for the second time, so that the impurity ions are bonded to dangling bonds in the second interface SF 2.
In the embodiment of the invention, the impurity ions can also be doped by adopting an ion implantation process, and the implantation energy in the second impurity ion doping process is satisfied to ensure that the target depth T2 is 0 nm-5 nm. Through the arrangement, the impurity ions in the second impurity ion doping process can be well diffused to the second interface SF2, so that the impurity ions are well combined with the hanging bonds at the second interface SF 2.
Optionally, the thickness of the second insulating layer 32 is 120nm to 200nm, and the implantation energy of the second impurity ion doping is 38KeV to 40 KeV. Through the reasonable setting of the thickness of the second insulating layer 32 and the implantation energy of the second impurity ion doping, the impurity ions in the second impurity ion doping process can be well diffused to the second interface SF2, so that the impurity ions are combined with the hanging bond at the second interface SF 2.
In summary, according to the method for manufacturing the thin film transistor array substrate of the embodiment of the invention, the channel region 21a of the silicon-based thin film layer 20a is doped with the impurity ions, so that the impurity ions are combined with the dangling bonds in the interface SF between the silicon-based thin film layer 20a and the insulating layer 30 to passivate the dangling bonds in the interface SF, thereby improving the defect state of the interface SF between the silicon-based thin film layer 20a and the insulating layer 30, improving the quality and stability of the thin film transistor, reducing the image sticking phenomenon of the display panel, and improving the display quality of the display panel.
In another aspect, an embodiment of the present invention provides a thin film transistor array substrate 100, and the thin film transistor array substrate 100 may be manufactured by the above-mentioned method for manufacturing a thin film transistor array substrate.
Referring to fig. 3 to 5, the tft array substrate 100 includes a substrate 10, and a silicon-based semiconductor layer 20b, a gate layer 40, and a source drain layer 50 stacked on the substrate 10, wherein the semiconductor layer 20b, the gate layer, and the source drain layer 50 are all insulated by an insulating layer 30, the semiconductor layer 20b includes a source doped region 221, a drain doped region 231, and a channel doped region 211 located between the source doped region 221 and the drain doped region 231, the insulating layer 30 includes a first insulating layer 31 and a second insulating layer 32 respectively disposed on two opposite surface sides of the semiconductor layer 20b in a stacking direction, an interface SF is respectively disposed between the semiconductor layer 20b and the first insulating layer 31 and the second insulating layer 32, and the interface SF includes impurity ions combined with dangling bonds; the gate layer 40 includes a gate disposed corresponding to the channel doping region 211; the source/drain layer 50 includes a source 51 and a drain 52 spaced apart from each other, the source 51 is electrically connected to the source doping region 221, and the drain 52 is electrically connected to the drain doping region 231. By arranging that the interface SF contains impurity ions combined with a dangling bond, the impurity ions can be combined with the dangling bond in the interface SF of the semiconductor layer 20b and the insulating layer 30 to passivate the dangling bond in the interface SF, so that the defect state of the interface SF between the semiconductor layer 20b and the insulating layer 30 is improved, the quality and the stability of the thin film transistor are improved, the afterimage phenomenon of the display panel can be reduced, and the display quality of the display panel is improved.
In order to passivate all or most of the dangling bonds in the interface SF, so as to effectively improve the stability of the thin film transistor and reduce the afterimage of the display panel, in some embodiments, the amount of the impurity ions in the interface SF is sufficient to saturate the dangling bonds in the interface SF.
To better bind the impurity ions to the dangling bonds at the interface SF, in some embodiments, the first insulating layer 31 has a first surface layer region 311 in contact with the semiconductor layer 20b, the first surface layer region 311 contains the impurity ions therein, and a thickness t1 of the first surface layer region 311 is 5nm or less; and/or the second insulating layer 32 has a second surface layer region 321 in contact with the semiconductor layer 20b, the second surface layer region 321 containing impurity ions, and the thickness t2 of the second surface layer being 5nm or less. Alternatively, 1nm ≦ t1 ≦ 2 nm; t2 is more than or equal to 1nm and less than or equal to 2 nm. With the above arrangement, all or most of dangling bonds in the interface SF between the semiconductor layer 20b and the insulating layer 30 can be passivated, so as to effectively improve the stability of the thin film transistor, thereby reducing the afterimage of the display panel.
In some embodiments, the impurity ions include one or more of H ions, F ions, S ions, B ions, Ga ions, Al ions, In ions, P ions, As ions, and Sb ions. With the above arrangement, the above-described impurity ions are allowed to combine with electrons of silicon atoms in the semiconductor layer 20b at the interface SF, enabling dangling bonds in the interface SF to be passivated.
Based on this, the impurity ions include one or more of F ions, B ions, and P ions. By arranging reasonable impurity ions, the electron binding force between the impurity ions and silicon atoms at the interface SF in the semiconductor layer 20b can be improved, and the stability of the thin film transistor can be further improved.
In some embodiments, the array substrate includes a top gate type structure transistor and/or a bottom gate type structure transistor. Through the arrangement, the top gate type structure transistor and/or the bottom gate type structure transistor have better stability, and the image sticking phenomenon of the display panel is improved.
To better illustrate that the tft array substrate 100 provided in the embodiments of the present invention can improve the afterimage of the display panel, referring to fig. 11, fig. 11 is a structural diagram illustrating a comparison between the tft array substrate provided in the present application and a comparative example. In fig. 11, in the thin film transistor array substrate 100 provided by the comparative example, there are a large number of dangling bonds at the interface of the semiconductor layer and the insulating layer, and the impurity ions are almost undoped at the interface. As is apparent from the experimental data shown in fig. 11, when the tft array substrate 100 according to the embodiment of the present invention is used, the retardation of the tft is significantly reduced compared to that of the tft in the comparative example, the retardation of the tft according to the embodiment of the present invention is only about 0.20, and the retardation of the tft in the comparative example is about 0.24; when the tft array substrate 100 according to the embodiment of the present invention is applied to a display panel, the remaining image disappearance time is about 10 seconds, whereas in the comparative example, the remaining image disappearance time is about 13 seconds. Therefore, the tft array substrate 100 provided by the embodiment of the invention can significantly improve the afterimage of the display panel.
Referring to fig. 12, fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. The present application further provides a display panel 1000. As shown in fig. 12, a display panel 1000 provided in an embodiment of the present invention may include a thin film transistor array substrate 100 and a counter substrate 200. The thin film transistor array substrate 100 is the thin film transistor array substrate according to any of the embodiments. The counter substrate 200 may be a protective cover plate, for example a glass cover plate. The display panel shown in fig. 12 may be an Organic Light-Emitting Diode (OLED) display panel, which may be a flexible display panel.
It should be understood by those skilled in the art that in other implementations of the present application, the Display panel may also be a Micro light emitting diode (Micro LED) Display panel, a quantum dot Display panel, a Liquid Crystal Display panel (LCD), or the like.
The display panel 1000 provided in the embodiment of the present application has the beneficial effects of the thin film transistor array substrate 100 provided in the embodiment of the present application, and specific descriptions for the array substrate in the above embodiments may be specifically referred to, and the detailed description of the embodiment is omitted here.
The application also provides a display device which comprises the display panel provided by the application. Referring to fig. 13, fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. Fig. 13 provides a display device 2000 including a display panel 1000 according to any of the above embodiments of the present application. The embodiment of fig. 13 is only an example of a mobile phone, and the display device 2000 is described, it is understood that the display device provided in the embodiment of the present application may be other display devices having a display function, such as a computer, a television, and a vehicle-mounted display device, and the present application is not limited thereto. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application, and specific reference may be specifically made to the specific description of the display panel in each of the above embodiments, which is not repeated herein.
In accordance with the embodiments of the present application as described above, these embodiments are not exhaustive and do not limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.
Claims (17)
1. A manufacturing method of a thin film transistor array substrate is characterized by comprising the following steps:
providing a semi-finished semiconductor product, wherein the semi-finished semiconductor product comprises a substrate, a silicon-based thin film layer and an insulating layer which are arranged on the substrate in a laminated mode, and an interface is arranged between the silicon-based thin film layer and the insulating layer;
and doping impurity ions in the channel region of the silicon-based thin film layer to form a channel doped region, and enabling the impurity ions to be combined with the suspension bonds in the interface.
2. The manufacturing method according to claim 1, wherein in the step of providing the semi-finished semiconductor product, the insulating layer comprises a first insulating layer on a surface side of the silicon-based thin film layer facing the substrate, and the interface comprises a first interface between the silicon-based thin film layer and the first insulating layer;
the doping of impurity ions to the channel region of the silicon-based thin film layer comprises:
performing first impurity ion doping on the channel region so that the impurity ions are combined with the dangling bonds in the first interface;
forming a second insulating layer on the surface side of the silicon-based thin film layer, which is far away from the substrate, wherein the interface further comprises a second interface between the silicon-based thin film layer and the second insulating layer;
and doping impurity ions for the second time in the channel region, so that the impurity ions are combined with the dangling bonds in the second interface.
3. The manufacturing method according to claim 1, wherein in the step of providing the semi-finished semiconductor product, the insulating layer includes a first insulating layer on a surface side of the silicon-based thin film layer facing the substrate and a second insulating layer on a surface side of the silicon-based thin film layer facing away from the substrate, and the interfaces include a first interface between the silicon-based thin film layer and the first insulating layer and a second interface between the silicon-based thin film layer and the second insulating layer;
the doping of impurity ions to the channel region of the silicon-based thin film layer comprises:
performing first impurity ion doping on the channel region so that the impurity ions are combined with the dangling bonds in the first interface;
and doping impurity ions for the second time in the channel region, so that the impurity ions are combined with the dangling bonds in the second interface.
4. The manufacturing method according to any one of claims 1 to 3, wherein in the step of doping the channel region of the silicon-based thin film layer with impurity ions, the impurity ions are doped in an amount sufficient to saturate dangling bonds in the interface.
5. The manufacturing method according to claim 2 or 3, wherein the doping of the impurity ions employs an ion implantation process, wherein,
the injection energy in the first impurity ion doping is satisfied to ensure that the difference delta T between the thickness T of the silicon-based thin film layer and the target depth T1 is 0 nm-5 nm; and/or the presence of a gas in the gas,
the injection energy in the second impurity ion doping is satisfied to make the target depth T2 be 0 nm-5 nm.
6. The production method according to claim 5, wherein Δ T is 1nm to 2 nm; t2 is 1 nm-2 nm.
7. The method according to claim 2, wherein the thickness of the silicon-based thin film layer is 30nm to 50nm, and the implantation energy of the first impurity ion doping is 10KeV to 12 KeV;
the thickness of the second insulating layer is 120 nm-200 nm, and the implantation energy of the second impurity ion doping is 38 KeV-40 KeV.
8. The method according to claim 3, wherein the thickness of the silicon-based thin film layer is 30nm to 50nm, the thickness of the second insulating layer is 120nm to 200nm, the implantation energy of the first impurity ion doping is 48KeV to 50KeV, and the implantation energy of the second impurity ion doping is 38KeV to 40 KeV.
9. A thin film transistor array substrate comprises a substrate, and a silicon-based semiconductor layer, a gate layer and a source drain layer which are stacked on the substrate and insulated by insulating layers, wherein,
the semiconductor layer includes a source doped region, a drain doped region, and a channel doped region between the source doped region and the drain doped region, the insulating layer includes a first insulating layer and a second insulating layer provided on opposite surface sides of the semiconductor layer in the stacking direction, the semiconductor layer and the first insulating layer and the second insulating layer respectively have an interface therebetween, the interface containing impurity ions bonded to dangling bonds;
the grid layer comprises a grid which is arranged corresponding to the channel doping region;
the source and drain electrode layer comprises a source electrode and a drain electrode which are arranged at intervals, the source electrode is electrically connected with the source electrode doped region, and the drain electrode is electrically connected with the drain electrode doped region.
10. The thin film transistor array substrate of claim 9, wherein the amount of impurity ions in the interface is sufficient to saturate dangling bonds in the interface.
11. The thin film transistor array substrate of claim 9, wherein the first insulating layer has a first surface layer region in contact with the semiconductor layer, the first surface layer region containing the impurity ions therein, the first surface layer region having a thickness t1 ≦ 5 nm; and/or the presence of a gas in the gas,
the second insulating layer has a second surface layer region in contact with the semiconductor layer, the second surface layer region contains the impurity ions, and the thickness t2 of the second surface layer is less than or equal to 5 nm.
12. The thin film transistor array substrate of claim 9, wherein t1 is 1nm or more and 2nm or less; t2 is more than or equal to 1nm and less than or equal to 2 nm.
13. The thin film transistor array substrate of claim 9, wherein the impurity ions comprise one or more of H ions, F ions, S ions, B ions, Ga ions, Al ions, In ions, P ions, As ions, and Sb ions.
14. The thin film transistor array substrate of claim 9, wherein the impurity ions comprise one or more of F ions, B ions, and P ions.
15. The thin film transistor array substrate of claim 9, wherein the array substrate comprises a top gate structure transistor and/or a bottom gate structure transistor.
16. A display panel comprising the array substrate according to any one of claims 9 to 15.
17. A display device characterized by comprising the display panel according to claim 16.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011434580.7A CN112563141A (en) | 2020-12-10 | 2020-12-10 | Thin film transistor array substrate, manufacturing method thereof, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011434580.7A CN112563141A (en) | 2020-12-10 | 2020-12-10 | Thin film transistor array substrate, manufacturing method thereof, display panel and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112563141A true CN112563141A (en) | 2021-03-26 |
Family
ID=75060271
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011434580.7A Pending CN112563141A (en) | 2020-12-10 | 2020-12-10 | Thin film transistor array substrate, manufacturing method thereof, display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112563141A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104716200A (en) * | 2015-04-03 | 2015-06-17 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method of thin film transistor, array substrate and display device |
| CN107819021A (en) * | 2017-11-06 | 2018-03-20 | 武汉华星光电半导体显示技术有限公司 | The preparation method and flexible OLED display panel of a kind of flexible OLED display panel |
| CN110828486A (en) * | 2019-11-19 | 2020-02-21 | 云谷（固安）科技有限公司 | Display panel manufacturing method and display panel |
| CN111653578A (en) * | 2020-06-22 | 2020-09-11 | 昆山国显光电有限公司 | Thin film transistor array substrate, preparation method thereof, display panel and display device |
| CN111900210A (en) * | 2020-08-11 | 2020-11-06 | 京东方科技集团股份有限公司 | Thin film transistor, display substrate and display device |
-
2020
- 2020-12-10 CN CN202011434580.7A patent/CN112563141A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104716200A (en) * | 2015-04-03 | 2015-06-17 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method of thin film transistor, array substrate and display device |
| CN107819021A (en) * | 2017-11-06 | 2018-03-20 | 武汉华星光电半导体显示技术有限公司 | The preparation method and flexible OLED display panel of a kind of flexible OLED display panel |
| CN110828486A (en) * | 2019-11-19 | 2020-02-21 | 云谷（固安）科技有限公司 | Display panel manufacturing method and display panel |
| CN111653578A (en) * | 2020-06-22 | 2020-09-11 | 昆山国显光电有限公司 | Thin film transistor array substrate, preparation method thereof, display panel and display device |
| CN111900210A (en) * | 2020-08-11 | 2020-11-06 | 京东方科技集团股份有限公司 | Thin film transistor, display substrate and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20230261005A1 (en) | Display device | |
| CN102640292B (en) | Semiconductor device and and manufacture method | |
| US20230359097A1 (en) | Display Device | |
| JP2021122051A (en) | Semiconductor device | |
| CN102891181B (en) | Transistor and display device | |
| US10153304B2 (en) | Thin film transistors, arrays substrates, and manufacturing methods | |
| TWI739757B (en) | Manufacturing method of semiconductor device | |
| US11749692B2 (en) | Display panel and display device | |
| US20170184892A1 (en) | Array substrate, method for manufacturing the same, and display device | |
| CN101740633A (en) | Semiconductor device and method for manufacturing the same | |
| US8785243B2 (en) | Method for manufacturing a thin film transistor array panel | |
| TWI590423B (en) | Display device | |
| US20220123082A1 (en) | Display panel and display device | |
| CN111886697B (en) | Display backboard, manufacturing method thereof, display panel and display device | |
| CN112563141A (en) | Thin film transistor array substrate, manufacturing method thereof, display panel and display device | |
| CN115295564A (en) | Array substrate and display panel | |
| CN203134809U (en) | Thin film transistor, array substrate, and display device | |
| CN103811558A (en) | Thin film transistor, method for manufacturing thin film transistor, array substrate, and display device | |
| CN220065706U (en) | Thin film transistor, driving circuit, display panel and display device | |
| KR102089339B1 (en) | Mask for forming active layer and manufacturing method of thin film transistor using the same | |
| CN111697005A (en) | Array substrate and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210326 |
|
| RJ01 | Rejection of invention patent application after publication |