CN203134809U - Thin film transistor, array substrate, and display device - Google Patents
Thin film transistor, array substrate, and display device Download PDFInfo
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- CN203134809U CN203134809U CN 201220581514 CN201220581514U CN203134809U CN 203134809 U CN203134809 U CN 203134809U CN 201220581514 CN201220581514 CN 201220581514 CN 201220581514 U CN201220581514 U CN 201220581514U CN 203134809 U CN203134809 U CN 203134809U
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Abstract
The utility model discloses a thin film transistor, an array substrate and a display device. The thin film transistor comprises a gate, an active layer and a gate insulating layer arranged between the gate and the active layer, and is characterized in that a crystalline material thin film layer is further arranged between the gate insulating layer and the active layer. According to the thin film transistor, the array substrate and the display device, the detects caused by the interfacial reaction between -OH perssad in the gate insulating layer and the active layer as well as the bombardment on the surface of the gate insulating layer can be overcame, thereby optimizing the features of the thin film transistor.
Description
Technical field
The utility model relates to the display technology field, relates in particular to a kind of thin-film transistor, array base palte and display unit.
Background technology
At present, the factor that influences the oxide thin film transistor stability of characteristics is a lot, whether good with the contact of active layer such as: gate insulator, there are differences because of moisture, stopping of oxygen in the different environment to external world of characteristic of barrier material, and the atmosphere in the annealing temperature of active layer and when annealing etc., this paper relates generally to the situation that contacts of gate insulator and active layer, and the structure of existing thin-film transistor as shown in Figure 1.
When having the preparation thin-film transistor now, normally at argon gas (Ar), oxygen (O
2) or Ar O
2Atmosphere under, magnetron sputtering a-indium gallium zinc oxide (IGZO) active layer 2 on gate insulator 1.Because polyvinylpyrrolidone resin materials such as (PVP) possesses advantages such as cost is low, dielectric constant is bigger, be often used as the gate insulator layer material of thin-film transistor.Comprise a large amount of-OH group in the resin material, can reduce a lot behind the crosslinking curing, but inside still has-the OH group, and these-OH group and unstable, can escape into gate insulator 1 and active layer 2 at the interface, with active layer 2 interfacial reaction taking place, thereby influence the characteristic of semiconductor of IGZO film, finally influences the performance of thin-film transistor.
In addition, during magnetron sputtering IGZO, Ar atom in the gas or Ar ion can bombard the surface of resin material, make gate insulator surperficial roughening and defective appears, like this, when thin film transistor switch is worked, the surface of gate insulator will produce the phenomenon of charge-trapping, and at the interface-the OH group further increases, and this will form certain grid leakage current, influence the performance of thin-film transistor equally.
The utility model content
In view of this, main purpose of the present utility model is to provide a kind of thin-film transistor, array base palte and display unit, can overcome in the thin-film transistor preparation process in the gate insulator-OH group and active layer generation interfacial reaction and gate insulator laminar surface bombarded the defective of generation, thereby optimized the characteristic of thin-film transistor.
For achieving the above object, the technical solution of the utility model is achieved in that
A kind of thin-film transistor comprises grid, active layer and the gate insulator between grid and active layer, also is provided with the crystalline material thin layer between described gate insulator and the active layer.
Described crystalline material thin layer is transparent conductive material.
Described transparent conductive material includes one or more in indium tin oxide, indium-zinc oxide, Graphene and the Single Walled Carbon Nanotube.
The figure of described crystalline material thin layer is more than or equal to the figure of active layer.
Described thin-film transistor also comprises: be arranged at grid on the substrate, be arranged at gate insulator on the grid, be arranged at barrier layer on the active layer, be arranged at source-drain electrode on active layer and the barrier layer, be arranged at the passivation layer on barrier layer and the source-drain electrode; Described crystalline material thin layer is positioned on the described gate insulator, and described active layer is positioned on the described crystalline material thin layer.
Described thin-film transistor also comprises: substrate, be arranged at source-drain electrode on the substrate, be arranged at active layer on substrate and the source-drain electrode, be arranged at the gate insulator on the active layer, and be arranged at the grid on the gate insulator; Described crystalline material thin layer is positioned under the described gate insulator, and described active layer is positioned under the described crystalline material thin layer.
The thickness of described crystalline material thin layer is 400～500 Ethylmercurichlorendimides.
A kind of array base palte comprises above-mentioned thin-film transistor.
A kind of display unit comprises above-mentioned array base palte.
The thin-film transistor that the utility model provides; the crystalline material thin layer is set between gate insulator and active layer; arranging when having cut off the deposition active layer of described crystalline material thin layer; oxonium ion in the resin material and active layer generation interfacial reaction; and the surface of gate insulator can be by Ar atom or the bombardment of Ar ion yet, and the surface of gate insulator has obtained protection, therefore; just can not produce grid leakage current during thin-film transistor work yet, thereby optimize the characteristic of thin-film transistor.
Description of drawings
Fig. 1 is the structural representation of existing thin-film transistor;
Fig. 2 forms structural representation behind the grid for the utility model embodiment;
Fig. 3 forms structural representation behind the crystalline material film for the utility model embodiment;
Fig. 4 forms structural representation behind the barrier layer for the utility model embodiment;
Fig. 5 forms structural representation behind the passivation layer for the utility model embodiment;
Fig. 6 is a kind of structural representation of the utility model embodiment thin-film transistor.
Fig. 7 is another structural representation of the utility model embodiment thin-film transistor.
Description of reference numerals:
1, gate insulator; 2, active layer; 3, grid; 4, crystalline material thin layer; 5, barrier layer; 6, source-drain electrode; 6a, source electrode; 6b, drain electrode; 7, passivation layer; 8, pixel electrode; 9, via hole.
Embodiment
Basic thought of the present utility model is: the crystalline material thin layer is set, to overcome the problem that existing gate insulator and active layer contact interface exist between gate insulator and active layer.
Wherein, described crystalline material thin layer is transparent conductive material, for example: materials such as indium tin oxide (as ITO) or indium-zinc oxide (as IZO), Graphene or Single Walled Carbon Nanotube.
Described crystalline material thin layer can be one or more layers, and described crystalline material thin layer can comprise single transparent conductive material, also can be for comprising the composite bed of multiple transparent conductive material.
Below in conjunction with drawings and the specific embodiments the utility model is described in further detail.
The preparation flow of the utility model thin-film transistor, comprise: form the figure that comprises grid, the figure that comprises active layer, and the gate insulator between grid layer and active layer, be formed with the crystalline material thin layer between described gate insulator and the active layer.
Manufacture method with bottom gate thin film transistor is described below:
Its idiographic flow comprises as follows:
Step 1: form the figure that comprises grid 3 at substrate;
Form grid layer film and graphical at substrate, form grid.Here, can adopt wet-etching technology to form grid 3, this step can adopt existing composition technology, no longer describes in detail herein, and the structure of formation as shown in Figure 2.When making grid, can also comprise the grid lead wire (not shown); Perhaps, can also make (not shown) such as public electrode or public electrode wire simultaneously.
Step 2: form gate insulator 1, and form the figure that comprises crystalline material thin layer 4 at gate insulator 1;
Form the gate insulator layer film at the substrate that forms grid, form gate insulator; Specifically comprise: apply gate dielectric materials at the substrate that forms grid, as PVP, can adopt prior art to form gate insulator 1.Here, described gate insulator 1 can also be silicon nitride (SiN
x), silica (SiO
x), hafnium oxide (HfO
x), aluminium oxide (AlO
x) or by at least wherein two kinds of multilayer laminated films of forming, thickness is generally controlled at for example 100nm～500nm, preferred 300nm-400nm, and transmitance is controlled more than 85%.
In addition, gate insulator 1 can also adopt physical sputtering method sputter deposition to form for example insulating layer of thin-film of 300nm-500nm, and material can be selected aluminium oxide (Al for use
2O
3) etc.
After forming gate insulator 1, form a crystalline material film and graphical at substrate, form crystalline material thin layer 4.For example, specifically comprise: forming substrate deposition one deck crystalline material of gate insulator 1, as ITO, IZO, Graphene or Single Walled Carbon Nanotube etc., adopt composition technology, as: dry etch process forms crystalline material thin layer 4, as shown in Figure 3.
Except the mode of deposition, the formation of crystalline material can also be adopted the mode of coating or spin coating.
Preferably, the formation of gate insulator and crystalline material thin layer can be finished with in a composition technology.
Here, ability is stronger because crystalline material is resisted the ion bombardment to select for use crystalline material to be, organic resin material is difficult for causing defective relatively, and good with contacting of gate insulator.
Step 3: order forms the figure that comprises active layer 2 and barrier layer 5;
Form active layer film and graphical at the substrate that forms the crystalline material thin layer, form active layer.Specifically comprise: can adopt observing and controlling sputtering sedimentation and wet-etching technology to form active layer 2, the material of described active layer 2 is oxide semiconductor material, active layer 2 is for comprising the sull of any two elements among In, Ga, Zn, the Sn element at least, for example: IGZO, InSnO or InGaSnO.The thickness of active layer 2 can be 10nm～100nm.The material of the active layer 2 in the present embodiment is preferentially selected IGZO, because ITO and IGZO material associativity are better.
Preferably, can also barrier layer 5 be set at active layer 2.Detailed process comprises: at active layer 2 deposition one deck SiO2, and adopt dry etch process to form barrier layer 5, obtain structure as shown in Figure 4, for interfacial reaction takes place in oxonium ion and the active layer 2 that cuts off fully in the resin material, described active layer 2 covers on the crystalline material thin layer 4, and the figure of crystalline material thin layer 4 can fully active layer 2 and gate insulator 1 are isolated, prevent from reacting between two more than or equal to the figure of active layer 2.This step can adopt prior art, no longer describes in detail herein, and the figure on the active layer 2 shown in Fig. 4 and barrier layer 5 is slightly different with prior art, but does not influence the technical solution of the utility model.Certainly, the active layer in the existing thin-film transistor structure shown in Figure 1 and the figure on barrier layer also are applicable to the utility model.
Step 4: order forms figure and the passivation layer 7 that comprises source-drain electrode 6;
Form source-drain electrode layer film and graphical at the substrate that forms active layer 2 and barrier layer 5, form the source-drain electrode layer.Specifically comprise: can pass through magnetron sputtering deposition molybdenum (Mo) on the substrate on barrier layer 5, and adopt wet etching to obtain source-drain electrode 6.Described source/drain electrode layer comprises source electrode and the drain electrode of each interval, and described active layer at interval part between corresponding to described source electrode and described drain electrode forms channel region.For example, when forming source-drain electrode, can also comprise forming the data wire (not shown) that it can be connected with the source electrode of one of source-drain electrode.
Preferably, after forming source-drain electrode 6, also form passivation layer.Forming passivation layer 7 specifically comprises: by spin coating acrylic materials on the source-drain electrode layer, perhaps deposit PVX or SiO
2 Form passivation layer 7, and adopt the dry etching method to form via hole at passivation layer 7, structure as shown in Figure 5.
Further, the thin-film transistor that the utility model present embodiment is made also comprises during as the switch block of display device pixel cell:
Step 5: form the figure that comprises pixel electrode 8.
Described pixel electrode only needs to be electrically connected with the drain electrode of source-drain electrode layer, guarantees that pixel cell is got final product by the thin-film transistor driven by pixel electrode.
For example, form pixel electrode film and graphical at the substrate that is formed with passivation layer, form pixel electrode.Specifically comprise: but on the substrate of the passivation layer that is formed with via hole magnetron sputtering deposition ITO, and adopting wet etching to form pixel electrode 8, described pixel electrode links to each other with the drain electrode of one of source-drain electrode 6 by the via hole on the passivation layer 7, as shown in Figure 6, this is prior art, no longer describes in detail.
Here, then can not need pixel electrode for the switch in the Organic Light Emitting Diode (OLED), therefore not need to carry out this step.
As shown in Figure 6, described crystalline material film is arranged between gate insulator and the active layer, to resist ion bombardment ability stronger because of crystalline material, relative organic resin material, as PVP, be difficult for causing defective, and good with contacting of gate insulator, with active layer material, also better as the combination of IGZO.The thinner thickness of described crystalline material film is approximately 400～500 Ethylmercurichlorendimides, if the too thick conductivity that can influence between gate insulator and active layer.
Below the structure of the thin-film transistor of the utility model embodiment is simply described.Shown in Fig. 1～6, described thin-film transistor comprises: be arranged at grid 3 on the substrate, be arranged at gate insulator 1 on grid 3 and the substrate, be arranged at crystalline material thin layer 4 on the gate insulator 1, be arranged at active layer 2 on the crystalline material thin layer 4, be arranged at barrier layer 5 on active layer 2 and the gate insulator 1, be arranged at source-drain electrode 6 on active layer 2 and the barrier layer 5, be arranged at the passivation layer 7 on barrier layer 5 and the source-drain electrode 6; Also comprise the pixel electrode 8 that is arranged on source-drain electrode 6 and the passivation layer 7.Wherein, described crystalline material thin layer is positioned on the described gate insulator, and described active layer is positioned on the described crystalline material thin layer.
Further, the utility model also is applicable to the top gate type metal oxide thin-film transistor, the structure of top gate type metal oxide thin-film transistor as shown in Figure 7, comprise: substrate, be arranged at source-drain electrode layer on the substrate (comprising source electrode 6a and drain electrode 6b), be arranged at active layer 2 on substrate and the source-drain electrode, be arranged at the gate insulator 1 on the active layer 2, and be arranged at grid 3 on the gate insulator 1, between the active layer 2 of described top gate type thin film transistor and the gate insulator 1 crystalline material thin layer 4 is set, is used for isolating active layer 2 and gate insulator 1.Described crystalline material thin layer 4 is positioned under the described gate insulator 1, and described active layer 2 is positioned under the described crystalline material thin layer 4.
Preferably, can also be included on the source-drain electrode layer barrier layer 5 between (comprising source electrode 6a and drain electrode 6b) and the active layer 2, and the passivation layer with via hole 97 on the grid 3.
Manufacture method with top gate type thin film transistor is described below:
Its idiographic flow comprises as follows:
Step 1: form the figure that comprises source-drain electrode 6 at substrate;
Form source-drain electrode layer film and graphical at substrate, form source-drain electrode (source electrode 6a and drain electrode 6b).For example, can pass through magnetron sputtering deposition molybdenum (Mo), and adopt wet etching to obtain source-drain electrode; Its technology can not repeat them here with reference to the mode of making bottom gate thin film transistor.Described source/drain electrode layer comprises source electrode and the drain electrode of each interval, and described active layer at interval part between corresponding to described source electrode and described drain electrode forms channel region.
For example: when forming source-drain electrode, can also comprise forming the data wire (not shown) that it can be connected with the source electrode of one of source-drain electrode.
Step 2: form the figure that comprises active layer 2, and form crystalline material thin layer 4 at active layer 2;
Optionally, form active layer 2 and can also form barrier layer 5 at source-drain electrode before, but need carry out via hole on the barrier layer, the realization active layer is electrically connected with source-drain electrode.Be that active layer can directly be connected with source-drain electrode, also can be by to connecting behind the via hole of barrier layer.
Wherein the making on active layer and barrier layer can not repeat them here with reference to the mode of making bottom gate thin film transistor.
After forming active layer, form crystalline material thin layer 4.For example, specifically comprise: forming substrate deposition one deck crystalline material of active layer, as ITO, IZO, Graphene or Single Walled Carbon Nanotube etc., adopt composition technology, as: dry etch process forms the crystalline material thin layer; Except the mode of deposition, can also adopt coating or spin coating one deck crystalline material.
Described crystalline material thin layer 4 covers on the active layer 2, and the figure of crystalline material thin layer 4 can fully active layer and gate insulator are isolated, prevent from reacting between two more than or equal to the figure of active layer 2.
Preferably, crystalline material thin layer and active layer can form with in a composition technology.
Here, ability is stronger because crystalline material is resisted the ion bombardment to select for use crystalline material to be, organic resin material is difficult for causing defective relatively, and good with contacting of gate insulator.
Step 3: form gate insulator 1;
Step 4: form the figure that comprises grid 3 at gate insulator 1;
Further, can also after forming grid, form passivation layer 7, the planarization that can keep thin-film transistor.At this moment, only need passivation layer is carried out via hole 9, grid is drawn realize getting final product with being electrically connected of gate drive signal.
Make insulating barrier, passivation layer and formation grid step and method and can be referenced as the mode of making bottom gate thin film transistor, do not repeat them here.
Preferably, gate insulator and grid can form with in a composition technology.
Further, the top gate type thin film transistor that the utility model present embodiment is made also comprises during as the switch block of display device pixel cell:
Step 5: form the figure that comprises pixel electrode 8.
Described pixel electrode only needs to be electrically connected with the drain electrode of source-drain electrode layer, guarantees that pixel cell is got final product by the thin-film transistor driven by pixel electrode.For example, pixel electrode can be realized being electrically connected with the drain electrode of source-drain electrode layer by the via hole of passivation layer etc.
As seen, the utility model can overcome in the gate insulator-and OH group and active layer generation interfacial reaction and gate insulator laminar surface bombarded the defective of generation, thereby optimized the characteristic of thin-film transistor.
In the utility model, described composition technology comprises mask, exposure, development, the photoetching of making figure, etching figures process.
For instance, adopt composition technology to form grid at substrate, be specially: at first at substrate deposition grid film, be coated with photoresist then, utilize mask plate that photoresist is exposed and form the photoresist pattern with development treatment, then utilize this photoresist pattern as etching mask, remove corresponding electrode layer by technologies such as etchings, and remove remaining photoresist, finally form gate patterns at substrate.
In addition, the utility model also provides a kind of array base palte, and the thin-film transistor in the described array base palte adopts aforesaid thin-film transistor.
The utility model also provides a kind of display unit, and described display unit comprises aforesaid thin-film transistor.
Need to prove that the manufacture method of thin-film transistor, array base palte, display unit and thin-film transistor that the utility model embodiment is related is not only applicable to liquid crystal display device, also is applicable to display devices such as OLED.
Wherein, described display unit can be any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
Embodiment of the present utility model provides a kind of display unit, and it comprises the array base palte of above-mentioned arbitrary embodiment.
One of this display unit is exemplified as liquid crystal indicator, and wherein, array base palte and counter substrate are opposite each other to form liquid crystal cell, are filled with liquid crystal material in liquid crystal cell.This counter substrate for example is color membrane substrates.The pixel electrode of each pixel cell of array base palte is used for applying electric field to be controlled the rotation degree of liquid crystal material, thereby carries out display operation.In some instances, this LCD also comprises: for array base palte provides backlight backlight.
Another of this display unit is exemplified as organic electroluminescence display device and method of manufacturing same, and wherein, the thin-film transistor of each pixel cell of array base palte is connected with the male or female of organic electroluminescence devices, and it is luminous to carry out display operation to be used for driving luminous organic material.
The crystalline material film arranges when having cut off the deposition active layer in the utility model, oxonium ion in the resin material and active layer generation interfacial reaction, and the surface of gate insulator can not bombarded yet, just can not produce grid leakage current during thin-film transistor work yet, optimize the characteristic of thin-film transistor.
The above is preferred embodiment of the present utility model only, is not for limiting protection range of the present utility model.
Claims (9)
1. a thin-film transistor comprises grid, active layer and the gate insulator between grid and active layer, it is characterized in that, also is provided with the crystalline material thin layer between described gate insulator and the active layer.
2. Thin Film Transistor (TFT) according to claim 1 is characterized in that, described crystalline material thin layer is transparent conductive material.
3. thin-film transistor according to claim 2 is characterized in that, described transparent conductive material includes one or more in indium tin oxide, indium-zinc oxide, Graphene and the Single Walled Carbon Nanotube.
4. thin-film transistor according to claim 1 and 2 is characterized in that, the figure of described crystalline material thin layer is more than or equal to the figure of active layer.
5. thin-film transistor according to claim 1, it is characterized in that, also comprise: be arranged at grid on the substrate, be arranged at gate insulator on the grid, be arranged at barrier layer on the active layer, be arranged at source-drain electrode on active layer and the barrier layer, be arranged at the passivation layer on barrier layer and the source-drain electrode;
Described crystalline material thin layer is positioned on the described gate insulator, and described active layer is positioned on the described crystalline material thin layer.
6. thin-film transistor according to claim 1, it is characterized in that, also comprise: substrate, be arranged at source-drain electrode on the substrate, be arranged at active layer on substrate and the source-drain electrode, be arranged at the gate insulator on the active layer, and be arranged at the grid on the gate insulator;
Described crystalline material thin layer is positioned under the described gate insulator, and described active layer is positioned under the described crystalline material thin layer.
7. thin-film transistor according to claim 1 and 2 is characterized in that, the thickness of described crystalline material thin layer is 400～500 Ethylmercurichlorendimides.
8. an array base palte is characterized in that, comprises each described thin-film transistor of claim 1-7.
9. a display unit is characterized in that, comprises the described array base palte of claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220581514 CN203134809U (en) | 2012-11-06 | 2012-11-06 | Thin film transistor, array substrate, and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220581514 CN203134809U (en) | 2012-11-06 | 2012-11-06 | Thin film transistor, array substrate, and display device |
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| Publication Number | Publication Date |
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| CN203134809U true CN203134809U (en) | 2013-08-14 |
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| CN 201220581514 Expired - Lifetime CN203134809U (en) | 2012-11-06 | 2012-11-06 | Thin film transistor, array substrate, and display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811558A (en) * | 2012-11-06 | 2014-05-21 | 北京京东方光电科技有限公司 | Thin film transistor, method for manufacturing thin film transistor, array substrate, and display device |
| CN105810745A (en) * | 2014-12-31 | 2016-07-27 | 业鑫科技顾问股份有限公司 | Thin-film transistor and thin-film transistor substrate |
| CN110335869A (en) * | 2019-05-09 | 2019-10-15 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display device |
-
2012
- 2012-11-06 CN CN 201220581514 patent/CN203134809U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811558A (en) * | 2012-11-06 | 2014-05-21 | 北京京东方光电科技有限公司 | Thin film transistor, method for manufacturing thin film transistor, array substrate, and display device |
| CN105810745A (en) * | 2014-12-31 | 2016-07-27 | 业鑫科技顾问股份有限公司 | Thin-film transistor and thin-film transistor substrate |
| CN105810745B (en) * | 2014-12-31 | 2019-06-18 | 鸿富锦精密工业（深圳）有限公司 | Thin film transistor (TFT) and thin film transistor base plate |
| CN110335869A (en) * | 2019-05-09 | 2019-10-15 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display device |
| CN110335869B (en) * | 2019-05-09 | 2021-11-23 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
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|---|---|---|---|
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| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: JINGDONGFANG SCIENCE AND TECHNOLOGY GROUP CO., LTD Free format text: FORMER OWNER: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY CO., LTD. Effective date: 20150629 Owner name: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY Effective date: 20150629 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20150629 Address after: 100015 Jiuxianqiao Road, Beijing, No. 10, No. Patentee after: BOE TECHNOLOGY GROUP Co.,Ltd. Patentee after: BEIJING BOE OPTOELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 100176 Beijing city in Western Daxing District economic and Technological Development Zone, Road No. 8 Patentee before: BEIJING BOE OPTOELECTRONICS TECHNOLOGY Co.,Ltd. |
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| CX01 | Expiry of patent term |
Granted publication date: 20130814 |
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| CX01 | Expiry of patent term |