CN103811558B - A kind of thin film transistor and its manufacturing method, array substrate and display device - Google Patents
A kind of thin film transistor and its manufacturing method, array substrate and display device Download PDFInfo
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- CN103811558B CN103811558B CN201210440147.3A CN201210440147A CN103811558B CN 103811558 B CN103811558 B CN 103811558B CN 201210440147 A CN201210440147 A CN 201210440147A CN 103811558 B CN103811558 B CN 103811558B
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- crystalline material
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- 239000010409 thin film Substances 0.000 title claims abstract description 53
- 239000000758 substrate Substances 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000010408 film Substances 0.000 claims abstract description 74
- 239000002178 crystalline material Substances 0.000 claims abstract description 68
- 239000012212 insulator Substances 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 25
- 230000004888 barrier function Effects 0.000 claims description 22
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 20
- 238000002161 passivation Methods 0.000 claims description 18
- 239000004020 conductor Substances 0.000 claims description 11
- 239000011347 resin Substances 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 10
- 239000002109 single walled nanotube Substances 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- 229910021389 graphene Inorganic materials 0.000 claims description 5
- 230000007547 defect Effects 0.000 abstract description 7
- 238000010406 interfacial reaction Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 239
- 238000000151 deposition Methods 0.000 description 9
- 230000008021 deposition Effects 0.000 description 9
- 238000000059 patterning Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000001755 magnetron sputter deposition Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000010849 ion bombardment Methods 0.000 description 4
- -1 oxonium ion Chemical class 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229920000036 polyvinylpyrrolidone Polymers 0.000 description 4
- 235000013855 polyvinylpyrrolidone Nutrition 0.000 description 4
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 210000002858 crystal cell Anatomy 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 150000001336 alkenes Chemical class 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- HTCXJNNIWILFQQ-UHFFFAOYSA-M emmi Chemical compound ClC1=C(Cl)C2(Cl)C3C(=O)N([Hg]CC)C(=O)C3C1(Cl)C2(Cl)Cl HTCXJNNIWILFQQ-UHFFFAOYSA-M 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- ZEWMZYKTKNUFEF-UHFFFAOYSA-N indium;oxozinc Chemical compound [In].[Zn]=O ZEWMZYKTKNUFEF-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000009738 saturating Methods 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
- 235000014692 zinc oxide Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/35—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being liquid crystals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Abstract
The invention discloses a kind of thin film transistor and its manufacturing method, array substrate and display device, which includes：Grid, active layer and the gate insulating layer between grid and active layer, which is characterized in that described that crystalline material film layer is additionally provided between gate insulating layer and active layer.The present invention can overcome-OH groups in gate insulating layer that the defect that interfacial reaction and gate insulator layer surface are generated by bombardment occurs with active layer, to optimize the characteristic of thin film transistor (TFT).
Description
Technical field
The present invention relates to display technology field more particularly to a kind of thin film transistor and its manufacturing method, array substrates
And display device.
Background technology
Currently, there are many factor for influencing oxide thin film transistor stability of characteristics, such as：Gate insulating layer and active layer
Whether contact is good, is had differences to the blocking of extraneous Environmental Water, oxygen because of the characteristic of barrier material difference, and
Atmosphere the etc. when annealing temperature of active layer and annealing relates generally to contact feelings of the gate insulating layer with active layer herein
The structure of condition, existing thin film transistor (TFT) is as shown in Figure 1.
It is existing when preparing thin film transistor (TFT), typically in argon gas (Ar), oxygen (O2) or Ar O2Atmosphere under,
Magnetron sputtering a- indium gallium zinc oxides (IGZO) active layer 2 on gate insulating layer 1.Because of resins such as polyvinylpyrrolidones (PVP)
Material has the advantages that at low cost, dielectric constant is larger, is often used as the gate insulating layer material of thin film transistor (TFT).Resinous wood
Comprising a large amount of-OH groups in material, can be much less after crosslinking curing, but it is internal still have-OH a groups, and these-
OH groups are simultaneously unstable, can escape into the interface of gate insulating layer 1 and active layer 2, and interfacial reaction occurs with active layer 2, from
And the characteristic of semiconductor of IGZO films is influenced, the final performance for influencing thin film transistor (TFT).
In addition, when magnetron sputtering IGZO, Ar atoms or Ar ions in gas can bombard the surface of resin material so that grid
The surface of pole insulating layer is roughening and defect occurs, in this way, when thin film transistor switch works, at the surface of gate insulating layer
The phenomenon that just will produce charge-trapping, and-OH the groups of interface further increase, this will form certain grid leakage current,
The same performance for influencing thin film transistor (TFT).
Invention content
In view of this, the main purpose of the present invention is to provide a kind of thin film transistor and its manufacturing method, array substrates
And display device, can overcome in thin film transistor (TFT) preparation process in gate insulating layer-OH groups and active layer occur interfacial reaction,
And the defect that gate insulator layer surface is generated by bombardment, to optimize the characteristic of thin film transistor (TFT).
In order to achieve the above objectives, the technical proposal of the invention is realized in this way：
A kind of thin film transistor (TFT), including grid, active layer and the gate insulating layer between grid and active layer, institute
It states and is additionally provided with crystalline material film layer between gate insulating layer and active layer.
The crystalline material film layer is transparent conductive material.
The transparent conductive material includes in indium tin oxide, indium-zinc oxide, graphene and single-walled carbon nanotube
It is one or more.
The figure of the crystalline material film layer is more than or equal to the figure of active layer.
The thin film transistor (TFT) further includes：The grid that is set on substrate, the gate insulating layer being set on grid, setting
In on active layer barrier layer, be set on active layer and barrier layer source-drain electrode, be set to it is blunt on barrier layer and source-drain electrode
Change layer；The crystalline material film layer is located on the gate insulating layer, and the active layer is located at the crystalline material film
On layer.
The thin film transistor (TFT) further includes：Substrate, is set on substrate and source-drain electrode the source-drain electrode being set on substrate
Active layer, the gate insulating layer being set on active layer, and it is set to the grid on gate insulating layer；The crystalline material
Film layer is located under the gate insulating layer, and the active layer is located under the crystalline material film layer.
The thickness of the crystalline material film layer is 400~500 Ethylmercurichlorendimides.
A kind of array substrate, including above-mentioned thin film transistor (TFT).
A kind of display device, including above-mentioned array substrate.
A kind of production method of thin film transistor (TFT), this method include：Formation includes that the figure of grid includes the figure of active layer
Shape, and the gate insulating layer between grid layer and active layer, it is described that crystalline substance is formed between gate insulating layer and active layer
Body material film layers.
Crystalline material film layer is formed between gate insulating layer and active layer, production method specifically includes：In grid
Crystalline material film layer is formed using transparent conductive material on the insulating layer of pole.
Crystalline material film layer is formed between gate insulating layer and active layer, production method specifically includes：Having
Crystalline material film layer is formed using transparent conductive material on active layer.
Crystalline material film layer, institute is arranged in thin film transistor (TFT) provided by the invention between gate insulating layer and active layer
When stating the setting of crystalline material film layer and having separated deposition active layer, it is anti-that interface occurs for oxonium ion and active layer in resin material
It answers, and the surface of gate insulating layer will not be protected by Ar atoms or Ar ion bombardments, the surface of gate insulating layer, because
This, thin film transistor (TFT) would not also generate grid leakage current when working, to optimize the characteristic of thin film transistor (TFT).
Description of the drawings
Fig. 1 is the structural schematic diagram of existing thin film transistor (TFT)；
Fig. 2 is that the embodiment of the present invention forms the structural schematic diagram after grid；
Fig. 3 is that the embodiment of the present invention forms the structural schematic diagram after crystalline material film；
Fig. 4 is that the embodiment of the present invention forms the structural schematic diagram behind barrier layer；
Fig. 5 is that the embodiment of the present invention forms the structural schematic diagram after passivation layer；
Fig. 6 is a kind of structural schematic diagram of thin film transistor (TFT) of the embodiment of the present invention.
Fig. 7 is another structural schematic diagram of thin film transistor (TFT) of the embodiment of the present invention.
Reference sign：
1, gate insulating layer；2, active layer；3, grid；4, crystalline material film layer；5, barrier layer；6, source-drain electrode；6a, source
Pole；6b, drain electrode；7, passivation layer；8, pixel electrode；9, via.
Specific implementation mode
The present invention basic thought be：Crystalline material film layer is set between gate insulating layer and active layer, to overcome
Existing gate insulating layer and active layer contact interface there are the problem of.
Wherein, the crystalline material film layer is transparent conductive material, such as：Indium tin oxide (such as ITO) or indium zinc oxygen
Compound (such as IZO), graphene or single-walled carbon nanotube material.
The crystalline material film layer can be one or more layers, and the crystalline material film layer may include single saturating
Bright conductive material, or include the composite layer of a variety of transparent conductive materials.
Below in conjunction with the accompanying drawings and specific embodiment invention is further described in detail.
The preparation flow of thin film transistor (TFT) of the present invention, including：Formation includes that the figure of grid includes the figure of active layer,
And the gate insulating layer between grid layer and active layer, it is described that crystal material is formed between gate insulating layer and active layer
Expect film layer.
It is described below with the production method of bottom gate thin film transistor：
Its detailed process includes as follows：
Step 1：Formation includes the figure of grid 3 on substrate；
Grid layer film and graphical, formation grid are formed on substrate.Here, wet-etching technology can be used and form grid
Existing patterning processes may be used in pole 3, the step, and and will not be described here in detail, and the structure of formation is as shown in Figure 2.When making grid,
It can also include grid lead wire (not shown)；(do not show alternatively, public electrode or public electrode wire etc. can also be made simultaneously
Go out).
Step 2：Gate insulating layer 1 is formed, and formation includes the figure of crystalline material film layer 4 on gate insulating layer 1
Shape；
Gate insulator layer film is formed on the substrate for forming grid, forms gate insulating layer；It specifically includes：Forming grid
Gate dielectric materials, such as PVP are coated on the substrate of pole, and the prior art may be used and form gate insulating layer 1.Here, the grid
Pole insulating layer 1 can also be silicon nitride (SiNx), silica (SiOx), hafnium oxide (HfOx), aluminium oxide (AlOx) or by least its
In two kinds of compositions multi-laminate tunics, thickness general control penetrates in such as 100nm~500nm, preferably 300nm-400nm
Rate is controlled 85% or more.
In addition, gate insulating layer 1 can also use physical sputtering method sputter deposition to form such as 300nm-500nm's
Insulating layer of thin-film, material can select aluminium oxide (Al2O3) etc..
After forming gate insulating layer 1, a crystalline material film and graphical, formation crystalline material are formed on substrate
Film layer 4.For example, specifically including：One layer of crystalline material is deposited on the substrate for forming gate insulating layer 1, such as ITO, IZO, stone
Black alkene or single-walled carbon nanotube etc., using patterning processes, such as：Dry etch process forms crystalline material film layer 4, such as Fig. 3 institutes
Show.
In addition to the mode of deposition, being formed for crystalline material can also be by the way of coating or spin coating.
Preferably, the formation of gate insulating layer and crystalline material film layer can be completed in a patterning processes.
Here, it is the opposite organic resin material because crystalline material resistance ion bombardment ability is stronger to select crystalline material
Defect is not easily caused, and the contact with gate insulating layer is good.
Step 3：Sequentially form the figure including active layer 2 and barrier layer 5；
Active layer film and graphical, formation active layer are formed on the substrate for forming crystalline material film layer.Specific packet
It includes：Observing and controlling sputtering sedimentation can be used and wet-etching technology forms active layer 2, the material of the active layer 2 is that oxide is partly led
Body material, active layer 2 are the sull including at least any two elements among In, Ga, Zn, Sn element, such as：IGZO,
InSnO or InGaSnO.The thickness of active layer 2 can be 10nm~100nm.The material of active layer 2 in the present embodiment preferentially selects
A-IGZO is selected, since ITO and IGZO material associativities are more preferable.
Preferably, barrier layer 5 can also be set on active layer 2.Detailed process includes：One layer is deposited on active layer 2
SiO2, and barrier layer 5 is formed using dry etch process, structure as shown in Figure 4 is obtained, in order to separate in resin material completely
Oxonium ion and active layer 2 interfacial reaction occurs, the active layer 2 is covered on crystalline material film layer 4, and crystalline material
The figure of film layer 4 can be more than or equal to the figure of active layer 2, active layer 2 and gate insulating layer 1 to be isolated completely, prevent
Only react between two.The prior art may be used in the step, and and will not be described here in detail, active layer 2 shown in Fig. 4 and resistance
The figure of barrier 5 is slightly different with the prior art, but does not influence technical scheme of the present invention.Certainly, existing film shown in Fig. 1 is brilliant
The figure of active layer and barrier layer in body pipe structure is also applied for the present invention.
Step 4：Sequentially form figure and passivation layer 7 including source-drain electrode 6；
Source-drain electrode layer film and graphical, formation source-drain electrode layer are formed on the substrate for forming active layer 2 and barrier layer 5.
It specifically includes：Source-drain electrode 6 can be obtained by magnetron sputtering deposition molybdenum (Mo) on the substrate on barrier layer 5, and using wet etching.
The source/drain layer includes the source electrode and drain electrode being spaced, and the active layer is corresponding to the source electrode and the drain electrode
Between the part that is spaced form channel region.Can also include forming data line (not shown) for example, when forming source-drain electrode,
It can connect with the source electrode of one of source-drain electrode.
Preferably, passivation layer is also formed after forming source-drain electrode 6.Passivation layer 7 is formed to specifically include：By in source-drain electrode
Spin coating acrylic materials on layer, or deposition PVX or SiO2Passivation layer 7 is formed, and using dry etching method in passivation layer 7
Upper formation via, structure are as shown in Figure 5.
Further, switch block of the thin film transistor (TFT) that the present embodiment of the present invention makes as display device pixel unit
When, further include：
Step 5：Formation includes the figure of pixel electrode 8.
The pixel electrode need to be only electrically connected with the drain electrode of source-drain electrode layer, it is ensured that pixel unit is by pixel electrode by film
Transistor normal driving.
For example, forming pixel electrode film and graphical, formation pixel electrode on the substrate for be formed with passivation layer.Specifically
Including：On the substrate for the passivation layer for being formed with via can magnetron sputtering deposition ITO, and using wet etching formed pixel electrode
8, the pixel electrode is connected by the via on passivation layer 7 with the drain electrode of one of source-drain electrode 6, as shown in fig. 6, this is existing skill
Art is no longer described in detail.
Here, pixel electrode can then not needed for the switch in Organic Light Emitting Diode (OLED), therefore do not needed
Execute this step.
As shown in fig. 6, the crystalline material film is set between gate insulating layer and active layer, because crystalline material is resisted
Ion bombardment ability is stronger, and opposite organic resin material, such as PVP does not easily cause defect, and the contact with gate insulating layer is good
Good, with active layer material, the combination such as IGZO is also preferable.The thinner thickness of the crystalline material film, about 400~500
Ethylmercurichlorendimide, if the too thick electric conductivity that can influence gate insulating layer and active interlayer.
The structure of the thin film transistor (TFT) of the embodiment of the present invention is briefly described below.As shown in figs. 1 to 6, described thin
Film transistor includes：The grid 3 that is set on substrate, is set to grid at the gate insulating layer 1 being set on grid 3 and substrate
Crystalline material film layer 4 on insulating layer 1, is set to active layer 2 and grid at the active layer 2 being set in crystalline material film layer 4
Barrier layer 5 on pole insulating layer 1, is set to barrier layer 5 and source-drain electrode 6 at the source-drain electrode 6 being set on active layer 2 and barrier layer 5
On passivation layer 7；It further include the pixel electrode 8 being set on source-drain electrode 6 and passivation layer 7.Wherein, the crystalline material film layer
On the gate insulating layer, the active layer is located on the crystalline material film layer.
Further, the present disclosure additionally applies for top gate type metal oxide thin-film transistor, top gate type metal oxide is thin
The structure of film transistor as shown in fig. 7, comprises：Substrate, the source-drain electrode layer being set on substrate (including source electrode 6a and drain electrode 6b),
The active layer 2 being set on substrate and source-drain electrode, the gate insulating layer 1 being set on active layer 2, and it is set to gate insulator
Crystalline material film is arranged in grid 3 on layer 1 between the active layer 2 and gate insulating layer 1 of the top gate type thin film transistor
Layer 4, for active layer 2 and gate insulating layer 1 to be isolated.The crystalline material film layer 4 is located under the gate insulating layer 1,
The active layer 2 is located under the crystalline material film layer 4.
Preferably, it can also include the blocking of (including source electrode 6a and drain electrode 6b) between active layer 2 on source-drain electrode layer
The passivation layer 7 with via 9 on layer 5 and grid 3.
It is described below with the production method of top gate type thin film transistor：
Its detailed process includes as follows：
Step 1：Formation includes the figure of source-drain electrode 6 on substrate；
Source-drain electrode layer film and graphical, formation source-drain electrode (source electrode 6a and drain electrode 6b) are formed on substrate.For example, can lead to
Magnetron sputtering deposition molybdenum (Mo) is crossed, and source-drain electrode is obtained using wet etching；Its technique, which can refer to, makes bottom gate thin film crystalline substance
The mode of body pipe, details are not described herein.The source/drain layer includes the source electrode and drain electrode being spaced, and the active layer exists
Channel region is formed corresponding to the part being spaced between the source electrode and the drain electrode.
Such as：Can also include forming data line (not shown) when forming source-drain electrode, it can be with one of source-drain electrode
Source electrode connects.
Step 2：Formation includes the figure of active layer 2, and crystalline material film layer 4 is formed on active layer 2；
Optionally, barrier layer 5 can also be formed before forming active layer 2 on source-drain electrode, but needs to carry out on barrier layer
Via, realization active layer are electrically connected with source-drain electrode.I.e. active layer can be directly connected to source-drain electrode, can also be by blocking
It is connected after layer via.
Wherein making for active layer and barrier layer can refer to the mode for making bottom gate thin film transistor, no longer superfluous herein
It states.
After forming active layer, crystalline material film layer 4 is formed.For example, specifically including：In the substrate for forming active layer
One layer of crystalline material of upper deposition, such as ITO, IZO, graphene or single-walled carbon nanotube, using patterning processes, such as：Dry etching
Technique forms crystalline material film layer；In addition to the mode of deposition, coating or one layer of crystalline material of spin coating can also be used.
The crystalline material film layer 4 is covered on active layer 2, and the figure of crystalline material film layer 4 can be more than etc.
In the figure of active layer 2, active layer and gate insulating layer to be isolated completely, react between preventing two.
Preferably, crystalline material film layer and active layer can be formed in a patterning processes.
Here, it is the opposite organic resin material because crystalline material resistance ion bombardment ability is stronger to select crystalline material
Defect is not easily caused, and the contact with gate insulating layer is good.
Step 3：Form gate insulating layer 1；
Step 4：Formation includes the figure of grid 3 on gate insulating layer 1；
Further, it can also form passivation layer 7 after the gate formation, the planarization of thin film transistor (TFT) can be kept.
At this point, only need to passivation layer be carried out via 9, grid is drawn and realizes and is electrically connected with gate drive signal.
Making insulating layer, passivation layer and forming grid step and method can be referenced as making bottom gate thin film transistor
Mode, details are not described herein.
Preferably, gate insulating layer and grid can be formed in a patterning processes.
Further, top gate type thin film transistor the opening as display device pixel unit that the present embodiment of the present invention makes
When closing component, further include：
Step 5：Formation includes the figure of pixel electrode 8.
The pixel electrode need to be only electrically connected with the drain electrode of source-drain electrode layer, it is ensured that pixel unit is by pixel electrode by film
Transistor normal driving.For example, pixel electrode can realize the drain electrode electricity with source-drain electrode layer by the via of passivation layer etc.
Connection.
As it can be seen that the present invention can overcome-OH groups in gate insulating layer that interfacial reaction and gate insulator occurs with active layer
The defect that layer surface is generated by bombardment, to optimize the characteristic of thin film transistor (TFT).
In the present invention, the patterning processes include the mask for making figure, exposure, development, photoetching, the graphical mistake such as etching
Journey.
For example, grid is formed on substrate using patterning processes, specially：It is thin that grid is deposited first on substrate
Film, then coating photoresist, is exposed photoresist using mask plate and development treatment forms photoetching agent pattern, then sharp
It uses the photoetching agent pattern as etching mask, removes corresponding electrode layer by techniques such as etchings, and remove remaining photoetching
Glue finally forms gate patterns on substrate.
In addition, the present invention also provides a kind of array substrate, the thin film transistor (TFT) in the array substrate uses institute as above
The thin film transistor (TFT) stated.
The present invention also provides a kind of display device, the display device includes thin film transistor (TFT) as described above.
It should be noted that the thin film transistor (TFT), array substrate, display device involved by the embodiment of the present invention and film
The production method of transistor, is applicable not only to liquid crystal display device, applies also for the display devices such as OLED.
Wherein, the display device can be：Liquid crystal display panel, Electronic Paper, oled panel, mobile phone, tablet computer, TV
Any product or component with display function such as machine, display, laptop, Digital Frame, navigator.
The embodiment provides a kind of display devices comprising the array substrate of any of the above-described embodiment.
One example of the display device is liquid crystal display device, wherein array substrate and counter substrate it is opposite each other with
Liquid crystal cell is formed, liquid crystal material is filled in liquid crystal cell.The counter substrate is, for example, color membrane substrates.Each picture of array substrate
The pixel electrode of plain unit controls the degree of rotation of liquid crystal material for applying electric field, to execute display operation.?
In some examples, which further includes：The backlight of backlight is provided for array substrate.
Another example of the display device is organic electroluminescence display device and method of manufacturing same, wherein each pixel of array substrate
Unit thin film transistor (TFT) connection organic electroluminescence device anode or cathode, for drive luminous organic material shine with into
Row display operation.
When the setting of crystalline material film has separated deposition active layer in the present invention, oxonium ion in resin material with it is active
Interfacial reaction occurs for layer, and the surface of gate insulating layer will not be bombarded, and thin film transistor (TFT) would not also generate grid when working
Pole leakage current optimizes the characteristic of thin film transistor (TFT).
The foregoing is only a preferred embodiment of the present invention, is not intended to limit the scope of the present invention.
Claims (10)
1. a kind of thin film transistor (TFT), including grid, active layer and the gate insulating layer between grid and active layer, special
Sign is, crystalline material film layer is additionally provided between the gate insulating layer and active layer；
The crystalline material film layer is one or more transparent conductive materials in graphene and single-walled carbon nanotube；
The gate insulating layer is formed by resin material.
2. thin film transistor (TFT) according to claim 1, which is characterized in that the figure of the crystalline material film layer be more than etc.
In the figure of active layer.
3. thin film transistor (TFT) according to claim 1, which is characterized in that further include：It is set to grid on substrate, setting
In on grid gate insulating layer, be set on active layer barrier layer, be set on active layer and barrier layer source-drain electrode, set
The passivation layer being placed on barrier layer and source-drain electrode；
The crystalline material film layer is located on the gate insulating layer, and the active layer is located at the crystalline material film layer
On.
4. thin film transistor (TFT) according to claim 1, which is characterized in that further include：Substrate, the source and drain being set on substrate
Pole, the active layer being set on substrate and source-drain electrode, the gate insulating layer being set on active layer, and it is set to gate insulator
Grid on layer；
The crystalline material film layer is located under the gate insulating layer, and the active layer is located at the crystalline material film layer
Under.
5. thin film transistor (TFT) according to claim 1, which is characterized in that the thickness of the crystalline material film layer is 400
~500 Ethylmercurichlorendimides.
6. a kind of array substrate, which is characterized in that including claim 1-5 any one of them thin film transistor (TFT)s.
7. a kind of display device, which is characterized in that including the array substrate described in claim 6.
8. a kind of production method of thin film transistor (TFT), which is characterized in that this method includes：
Formation includes that the figure of grid includes the figure of active layer, and the gate insulator between grid layer and active layer
Layer, is formed with crystalline material film layer between the gate insulating layer and active layer；
The crystalline material film layer is one or more transparent conductive materials in graphene and single-walled carbon nanotube；
The gate insulating layer is formed by resin material.
9. the production method of thin film transistor (TFT) as claimed in claim 8, which is characterized in that gate insulating layer and active layer it
Between be formed with crystalline material film layer, production method specifically includes：
Crystalline material film layer is formed using transparent conductive material on gate insulating layer.
10. the production method of thin film transistor (TFT) as claimed in claim 8, which is characterized in that in gate insulating layer and active layer
Between be formed with crystalline material film layer, production method specifically includes：
Crystalline material film layer is formed using transparent conductive material in active layer.
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| KR100963027B1 (en) * | 2008-06-30 | 2010-06-10 | 삼성모바일디스플레이주식회사 | Thin film transistor, method of manufacturing the thin film transistor and flat panel display device having the thin film transistor |
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