CN204289541U - Array base palte, display floater, display unit - Google Patents
Array base palte, display floater, display unit Download PDFInfo
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- CN204289541U CN204289541U CN201420870677.6U CN201420870677U CN204289541U CN 204289541 U CN204289541 U CN 204289541U CN 201420870677 U CN201420870677 U CN 201420870677U CN 204289541 U CN204289541 U CN 204289541U
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Abstract
The utility model provides a kind of array base palte, display floater, display unit, relate to Display Technique field, wherein array base palte comprises and is positioned at above active layer and/or the zinc oxide film of below, and the upright projection of the upright projection of this zinc oxide film on array base palte at least with active layer on array base palte is overlapping.Described display floater comprises above-mentioned array base palte.Described display unit comprises above-mentioned display floater.The utility model by above active layer and/or below zinc oxide film is set, utilize zinc oxide film to have the character of good absorption to UV light, efficiently avoid the harmful effect of the threshold voltage of UV illumination array substrate TFT.
Description
Technical field
The utility model relates to Display Technique field, particularly relates to a kind of array base palte, display floater, display unit.
Background technology
OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode) display unit mainly comprises each functional layer of TFT (Thin Film Transistor, thin-film transistor) array base palte and OLED.Wherein, for tft array substrate, according to the difference of the material of TFT active layer, TFT can be divided into amorphous silicon (a-Si:H), low temperature polycrystalline silicon (Low Temperature Poly-Silicon, be called for short LTPS), the polytype such as high temperature polysilicon (High Temperature Poly-Silicon, be called for short HTPS), oxide.Wherein, oxide TFT relative to the TFT of other type have electron mobility high, with the advantage such as the compatibility of display unit production line is good, be the focus studied in current field.
Active layer is subject to UV illumination and penetrates and easily produce threshold voltage shift, for oxide TFT, the active layer of oxide TFT generally adopts IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide), ITZO (Indium Tin Zinc Oxide, indium tin zinc oxide), the material such as ZnO (zinc oxide), IZO (IndiumZinc Oxide, indium-zinc oxide).For the IGZO OLED display of common bottom grating structure, UV light can irradiate on IGZO active layer after the multiple reflections of cathode metal layer and source/drain metal level.Energy gap due to IGZO is about 3.4eV, the energy gap of UV light is higher than 3.1eV, IGZO has good absorption to UV light, therefore after penetrating through UV illumination, the electronics of catching in the valence-band electrons in active layer and forbidden band defect level can absorb energy jump easily to conduction band, produces photo-generate electron-hole pair, finally makes the threshold voltage vt h of TFT drift about, cause GTG to show abnormal, picture display effect declines.
Utility model content
For overcoming above-mentioned defect of the prior art, technical problem to be solved in the utility model is: provide a kind of array base palte, display floater, display unit, to improve the problem that UV illumination causes TFT threshold voltage shift.
For achieving the above object, the utility model adopts following technical scheme:
First aspect of the present utility model provides a kind of array base palte, comprise thin-film transistor, described array base palte also comprises: above the active layer being positioned at described thin-film transistor and/or the zinc oxide film of below, and the upright projection of described zinc oxide film on array base palte is at least overlapping with the upright projection of described active layer on array base palte.
Preferably, described zinc oxide film is Nano zinc oxide film.
Preferably, the thickness of described zinc oxide film is 5nm ~ 50nm.
Preferably, the upright projection of described zinc oxide film on array base palte covers the upright projection of described active layer on array base palte.
Preferably, the upright projection of described zinc oxide film on array base palte covers whole array base palte.
Preferably, described array base palte also comprises: be set in turn in the passivation layer above described active layer and planarization layer, and described zinc oxide film is between described passivation layer and described planarization layer or be positioned at above described planarization layer.
Preferably, described array base palte also comprises: be positioned at thin-film transistor drain electrode top and run through the via hole of described planarization layer, described zinc oxide film and described passivation layer.
Preferably, described array base palte also comprises: be arranged at the resilient coating below described active layer, and described zinc oxide film is positioned at the below of described resilient coating.
Preferably, the material of described active layer is indium gallium zinc oxide.
Preferably, described array base palte also comprises: be arranged at the anode layer above described active layer, pixel defines layer, luminescent layer and cathode layer.
Preferably, described array base palte also comprises: the color rete between described active layer and described anode layer.
Second aspect of the present utility model provides a kind of display floater, comprises above-described array base palte.
The third aspect of the present utility model provides a kind of display unit, comprises above-described display floater.
In array base palte provided by the utility model, display floater, display unit, above active layer and/or below formed zinc oxide film, make zinc oxide film and the active layer upright projection on array base palte overlapping, energy gap due to zinc oxide is 3.24eV, good absorption is had to UV light, therefore, it is possible to the UV light improved in light is radiated at TFT threshold voltage shift caused on the active layer of TFT, improve the stability of TFT.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Each block diagram of the manufacture method of a kind of display floater that Fig. 1 ~ Figure 14 provides for the utility model embodiment;
Description of reference numerals: 101-underlay substrate; 102-grid; The hardware that 103-and grid are formed with layer; Gate insulator 201; Active layer 301; Etching barrier layer 401; Drain electrode 501; Source electrode 502; Passivation layer 601; Zinc oxide film 701; Color rete 801; Planarization layer 901; Via hole 1001; Anode layer 1101; Pixel defines layer 1201; Form each functional layer 1301 of OLED; Cathode layer 1401.
Embodiment
For enabling above-mentioned purpose of the present utility model, feature and advantage become apparent more, below in conjunction with the accompanying drawing in the utility model embodiment, are clearly and completely described the technical scheme in the utility model embodiment.Obviously, described embodiment is only the utility model part embodiment, instead of whole embodiments.Based on the embodiment in the utility model, other embodiments all that those of ordinary skill in the art obtain under the prerequisite of not making creative work, all belong to the scope of the utility model protection.
The utility model embodiment provides a kind of array base palte, comprise thin-film transistor, described array base palte also comprises: above the active layer being positioned at described thin-film transistor and/or the zinc oxide film of below, and the upright projection of the upright projection of zinc oxide film on array base palte at least with active layer on array base palte is overlapping.Energy gap due to zinc oxide is 3.24eV, good absorption is had to UV light, by making zinc oxide film and the active layer upright projection on array base palte overlapping, zinc oxide film is made to play the effect of blocking UV light to active layer, therefore, it is possible to the UV light improved in light is radiated at TFT threshold voltage shift caused on the active layer of TFT, improve the stability of TFT.
In the present embodiment, zinc oxide film is Nano zinc oxide film preferably, to strengthen the absorption efficiency of zinc oxide film to UV light further.Certainly, zinc oxide film can be common zinc oxide film (as: particle diameter is greater than the zinc-oxide film that nano level Zinc oxide particles is formed), does not limit at this.
The thickness of zinc oxide film preferably can be 5nm ~ 50nm, has both guaranteed fully to absorb UV light, and the integral thickness of the rete on array base palte can not be made again too much to increase.
For ensureing that whole active layer all can avoid the irradiation of UV light, the upright projection of zinc oxide film on array base palte preferably can be made to be coated with the upright projection of active layer on array base palte.More preferably, the upright projection of zinc oxide film on array base palte covers whole array base palte, thus it stops that the effect of UV light is better, and do not need independent patterning processes, just directly can form zinc oxide film by means of only film-forming process such as sputtering, evaporation, deposits, technique simply, easily realizes.
In the present embodiment, the set-up mode of zinc oxide film can design targetedly according to the type difference of display floater.For OLED display panel, the major part UV light be radiated on TFT comes from the top of TFT, therefore can arrange zinc oxide film above active layer; For the display floater of liquid crystalline type, have the backlight module of quite a few UV light from the array base palte back side, therefore, zinc oxide film can be set in the below of active layer; Certainly, in order to avoid the irradiation of the UV light above and below from TFT simultaneously, zinc oxide film can be set above and below active layer simultaneously.
And, the present embodiment does not limit the setting position of zinc oxide film in each rete of array base palte, preferably can be arranged between the two-layer rete with insulating property (properties) or be arranged on the top of the rete with insulating barrier character, separating with the rete with conduction property, impacting to avoid the rete to having conduction property.
Concrete, if arrange zinc oxide film above active layer, then for the array base palte of bottom grating structure, grid, gate insulator, active layer, source-drain electrode metal level, passivation layer, planarization layer sets gradually, the rete that the top of active layer has insulating property (properties) comprises passivation layer and planarization layer, preferably can zinc oxide film be arranged between passivation layer and planarization layer or be arranged on above planarization layer, now, if array base palte also comprises the via hole for exposing source-drain electrode metal level, then this via hole runs through planarization layer, zinc oxide film and passivation layer, expose source-drain electrode metal level, so that the electrode formed in subsequent step can be electrically connected with source-drain electrode metal level by this via hole, for the array base palte of top gate structure, active layer, source-drain electrode metal level, gate insulator, grid, passivation layer, planarization layer sets gradually, the rete that the top of active layer has insulating property (properties) comprises passivation layer and planarization layer, preferably can zinc oxide film be arranged between passivation layer and planarization layer or be arranged on above planarization layer, now, if array base palte also comprises the via hole for exposing source-drain electrode metal level, then this via hole runs through planarization layer, zinc oxide film and passivation layer, so that the electrode formed in subsequent step can be electrically connected with source-drain electrode metal level by this via hole.If arrange zinc oxide film in the below of active layer, then owing to preferably can there is resilient coating below active layer, therefore zinc oxide film can be arranged at the below of resilient coating.
Certainly, other set-up mode except above cited set-up mode and setting position and setting position can also be adopted to arrange zinc oxide film for the array base palte of different structure, this be will not enumerate.
In addition, it should be noted that, in the present embodiment, the material of the active layer of array base palte preferably can be indium gallium zinc oxide, indium gallium zinc oxide has higher electron mobility, but it is comparatively responsive to UV light, easily be subject to the impact of UV light and the problem of threshold voltage shift occurs, owing to being provided with the zinc oxide film for blocking UV light in the present embodiment, solve the problem that indium gallium zinc oxide easily drifts about as threshold voltage during active layer, the technical scheme that therefore the present embodiment provides is particularly useful for the array base palte of indium gallium zinc oxide as active layer.
It should be noted that, for the display unit of OLED type, the array base palte that the present embodiment provides also can comprise: anode layer, pixel define layer, luminescent layer and cathode layer, wherein anode layer is electrically connected with the source and drain metal level of the TFT on array base palte by a via hole, define between layer and cathode layer except there is luminescent layer in pixel, also can comprise: hole injection layer, hole transmission layer and electron transfer layer; Further, if the light that luminescent layer produces is white light, then this array base palte also can comprise color rete, between active layer and anode layer, filter with the white light produced luminescent layer, the light through sub-pixel is made to have the solid color such as red, green, blue, Huang, if the luminescent layer of different subpixel inherently can send the light of the solid color such as red, green, blue, Huang, then without the need to arranging color rete.For the display unit of liquid crystalline type, the array base palte that the present embodiment provides also can comprise the electrode be electrically connected with the source and drain metal level of the TFT on array base palte by a via hole, and this electrode specifically can be pixel electrode.
The present embodiment additionally provides a kind of manufacture method of array base palte, comprise the step forming thin-film transistor, this manufacture method also comprises: before or after being formed with active layer, form zinc oxide film, and the upright projection of the upright projection of zinc oxide film on array base palte at least with active layer on array base palte is overlapping.Energy gap due to zinc oxide is 3.24eV, good absorption is had to UV light, therefore by make the upright projection of zinc oxide film on array base palte and the upright projection of active layer on array base palte overlapping, zinc oxide film can be made active layer to be played to the effect of blocking UV light, avoid UV light and be radiated at TFT threshold voltage shift caused on the active layer of TFT, improve the stability of TFT.
The process forming zinc oxide film in the present embodiment preferably can be: form zinc layers, the upright projection of the upright projection of this zinc layers on array base palte at least with active layer on array base palte is overlapping, formed zinc layers is annealed, zinc layers is oxidized and forms zinc oxide film.Adopt aforementioned process to form the requirement of zinc oxide film to technique low, easily realize.
The manufacture method of the array base palte that the present embodiment provides is different according to the structure difference of made array base palte.Such as: for bottom grating structure and the array base palte of zinc oxide film above active layer, its manufacture method can also comprise after being formed with active layer: above active layer, form passivation layer and planarization layer successively, zinc oxide film is formed between passivation layer and planarization layer or is formed at above planarization layer, after formation planarization layer, zinc oxide film and passivation layer, also can form the via hole running through planarization layer, zinc oxide film and passivation layer further, for top gate structure and the array base palte of zinc oxide film above active layer, its manufacture method can also comprise after being formed with active layer: above active layer, form source-drain electrode metal level successively, gate insulator, grid, passivation layer and planarization layer, zinc oxide film is formed between passivation layer and planarization layer or is formed at above planarization layer, at formation planarization layer, after zinc oxide film and passivation layer, also can be formed further and run through planarization layer, the via hole of zinc oxide film and passivation layer, so that the electrode formed in subsequent step can be electrically connected with source-drain electrode metal level by this via hole, be positioned at the array base palte below active layer for zinc oxide film, before being formed with active layer, its manufacture method also can comprise: form resilient coating, zinc oxide film is formed at the below of resilient coating, before being namely formed at resilient coating formation.
Below in conjunction with Fig. 1 ~ Figure 10 to bottom grating structure and the manufacture method of array base palte that zinc oxide film is arranged between passivation layer and planarization layer describe in detail.
Step S1: form the figure comprising grid 102 on underlay substrate 101, as shown in Figure 1.
In this step, underlay substrate 101 is preferably transparency carrier, specifically can adopt corning glass, Asahi Glass glass or quartz glass etc., to ensure subsequent technique and the enough mechanical strength of display unit.The thickness of underlay substrate 101 preferably can be 50 μm ~ 1000 μm, meets the demand of various thickness displaying apparatus.
The material comprising the figure of grid 102 such as can be the metals such as Al, Mo, Cr, Cu, Ti, ensures the electric conductivity that grid 102 is good.Thickness profile can design according to actual conditions and demand, preferably can be 200nm ~ 1000nm.
The process that preparation comprises the figure of grid 102 can be in simple terms: adopt the techniques such as sputtering or deposit on underlay substrate 101, form grid 102 material layer, use patterning processes on this material layer, define the photoresist of the figure possessing grid 102, utilize dry quarter or this material layer of wet etching, grid 102 figure needed for formation, stripping photoresist, ensures the accuracy of graph position and size in patterning process.In addition, while formation grid 102, also can form the hardware 103 formed with layer with grid 102, this can be capacitance electrode, via hole articulamentum, grid line, public electrode wire etc. with grid 102 with the hardware 103 that layer is formed.
Step S2: form gate insulator 201 on the underlay substrate 101 having formed the figure comprising grid 102, as shown in Figure 2.
The thickness of gate insulator 201 preferably can be set to 50nm ~ 500nm, is more preferably 100nm ~ 300nm, to ensure the insulation property that other conductive film layer of grid 102 and via hole articulamentum 103 and follow-up formation is good.Gate insulator 201 such as can adopt SiO
x(silica, as: SiO
2), SiN
x(silicon nitride, as: Si
3n
4), SiO
xn
yat least one organic or inorganic materials such as (silicon oxynitrides) is formed, and it can be formed as the membrane structure of single or multiple lift further, to play a very good protection to the rete being located thereon layer or lower floor.
In this step, the formation of gate insulator 201 preferably can adopt CVD (Chemical VaporDeposition, chemical vapour deposition (CVD)), especially PECVD (Plasma Enhanced Chemical VaporDeposition, plasma enhanced chemical vapor deposition) technique is formed.
Step S3: form the figure including active layer 301 on gate insulator 201, as shown in Figure 3.
The material of active layer 301 preferably can be the oxide semiconductors such as IGZO, ITZO, makes TFT have higher electron mobility.Its thickness such as can be 5nm ~ 250nm, ensures active layer and has good electrical property.
Form the process including the figure of active layer 301 preferably to can be: adopt sputtering or depositing technics to cover active layer material on gate insulator 201, utilize patterning processes to etch covered active layer material, form the figure including active layer 301.Active layer 301 is specifically positioned at the region above grid 102.
Step S4: form etching barrier layer 401 on the underlay substrate 101 having formed the figure including active layer 301, this etching barrier layer 401 has the source contact openings exposing active layer 301 surface and drain contact hole, as shown in Figure 4.
In this step, etching barrier layer 401 such as can be the SiOx film that thickness is 50nm ~ 200nm.
Form etching barrier layer 401 and preferably can adopt pecvd process first deposition-etch barrier material, then patterning processes is utilized, define source contact openings and drain contact hole pattern, etch this etching barrier layer materials afterwards, until expose the surface of active layer 301.
Step S5: form the figure comprising drain electrode 501 and source electrode 502 on etching barrier layer 401, wherein source electrode 502 is electrical connected by source contact openings and active layer 301, drain electrode 501 is electrical connected by drain contact hole and active layer 301, as shown in Figure 5.
In this step, the thickness comprising the figure of drain electrode 501 and source electrode 502 preferably can be 5nm ~ 250nm, and its material can be the metals such as Al, Mo, Cr, Cu, Ti, to ensure that drain electrode 501 and source electrode 502 have less transmission resistance.
What formed with layer with drain electrode 501 and source electrode 502 preferably also can comprise connection metal layer, for the grid of the source electrode and driving tube that are electrically connected the switching tube in display unit pixel.In addition, what formed with layer also comprises data wire, and data wire and source electrode 502 are electrical connected, for applying data voltage signal to pixel.
Forming the figure comprising drain electrode 501 and source electrode 502 can adopt the techniques such as sputtering or deposit to cover source/drain metal material, then patterning processes is utilized to define the figure of drain electrode 501 and source electrode 502, source/drain metal material is etched, forms the figure comprising drain electrode 501 and source electrode 502.After this step, prepared by the TFT of OLED display.
Step S6: form passivation layer 601 on the underlay substrate 101 having formed the figure comprising drain electrode 501 and source electrode 502, as shown in Figure 6.
In this step, passivation layer 601 preferably can adopt the insulating material such as the inorganic material such as silica, silicon nitride and organic material to be formed, passivation layer 601 can repair rete (as: comprise the figure of drain electrode 501 and the source electrode 502) surface adjacent with self and inner defect, promotes film quality.
Passivation layer 601 preferably can adopt pecvd process to prepare.
Step S7: form zinc oxide film 701 on passivation layer 601, as shown in Figure 7.
Concrete, the process forming zinc oxide film 701 can be: on passivation layer 601, form zinc layers, the upright projection of this zinc layers on underlay substrate 101 is at least overlapping with the upright projection of active layer 301 on underlay substrate 101, the underlay substrate 101 having formed zinc layers is annealed, makes zinc layers anneal oxidation form zinc oxide film 701.
Because the energy gap of zinc oxide is 3.24eV, there is fabulous UV optical absorption, therefore the zinc oxide film 701 TFT electrical property deterioration problem that can be good at preventing UV illumination to be mapped to the active layer 301 of TFT causes.
Further, adopt in prior art and utilize patterning processes formation can reflect the scheme of the electrode of UV light to alleviate the impact of UV illumination on display unit TFT on passivation layer or active layer, multiple steps such as gluing, contraposition, exposure, development, cleaning are needed due to patterning processes itself, and the cost intensive of patterning processes, this can increase complexity and the cost of manufacture of display unit process for integrally manufacturing undoubtedly.Form zinc oxide film in this step only to need to form zinc layers and anneal oxidation two steps, without the need to carrying out the patterning processes of complexity and costliness, simple for process, cost is low.
In this step, zinc layers preferably can be the granuloplastic film of Nano-Zinc, the film that preferred Nano-Zinc uniform particles distribution is formed, thus the zinc oxide film 701 that oxidation is formed is Nano zinc oxide film, to ensure having higher assimilation effect to UV light.
The thickness of zinc layers preferably can be 5nm ~ 50nm, thus the thickness of the zinc oxide film 701 of oxidation formation is 5nm ~ 50nm, to ensure the light penetration that display unit is higher.
Zinc layers is preferably coated with active layer 301, thus the zinc oxide film 701 that oxidation is formed is coated with active layer 301, penetrates active layer with the more effective UV of preventing illumination.
It should be noted that, paste uv blocking diaphragm according in the outside of array base palte, for ensureing desirable UV assimilation effect, it is thicker that the thickness of uv blocking diaphragm need be arranged, and this affects the light penetration of array base palte to a certain extent.In the present embodiment, because zinc oxide has good UV optical absorption, therefore just can reach desirable uv blocking effect without the need to very thick zinc oxide film, it is very thin that the thickness of zinc layers can be arranged, thus the light penetration of array base palte made by the present embodiment is higher.
In addition, it is to be noted, the particle diameter of zinc particle is only nanometer, thus make formed zinc layers finer and close, and then the zinc oxide film of follow-up formation is finer and close, make under the prerequisite with identical UV optical absorption, it is thinner that the granuloplastic zinc layers of Nano-Zinc can be done, and further increases the light transmission of device.
What form the optimal process that adopts of zinc layers can be evaporation process, sputtering technology or depositing technics, to ensure the uniformity of zinc layers and zinc oxide film 701 thickness.
Because the oxidizing temperature of zinc is very low, generally just can vigorous oxidation 225 DEG C time, therefore, the temperature needed for annealing in this step is lower, and this can reduce technology difficulty further.Preferably can be 230 ~ 400 DEG C to forming the underlay substrate of zinc layers adopted annealing temperature of annealing, to ensure that zinc layers is substantially oxidized, improving the UV assimilation effect of zinc oxide film 701.Because annealing temperature is lower, therefore, it is possible to simplify the manufacture method of OLED display further, reduce production cost.
Step S8: the color film material of spin coating, adopts patterning processes to form color rete 801, as shown in Figure 8.
Color film material preferably can be the resin of red (R), green (G), blue (B) three kinds of colors, or is the resin of red, green, blue, white (W) four kinds of colors, to realize the full-color display of OLED display.Color rete 801 thickness such as can be 2 μm ~ 3.5 μm, specifically can respective design according to actual needs.
The upright projection of color rete 801 is positioned at the grid that gate line and data wire are staggered to form.
Step S9: spin coating planarization layer material, adopts patterning processes to form planarization layer 901, as shown in Figure 9.
In this step, the thickness of planarization layer 901 can be 1 μm ~ 2 μm, and planarization layer material can be resin, to make the surface planarisation of the underlay substrate 101 defining color rete 801.
Step S10: adopt patterning processes to form the via hole 1001 running through planarization layer 901, zinc oxide film 701 and passivation layer 601 successively, as shown in Figure 10.
In this step, via hole 1001 preferably can be made up of with the passivation layer via hole running through zinc oxide film 701 and passivation layer 601 the planarization layer via hole running through planarization layer 901, the aperture of planarization layer via hole is greater than passivation layer via hole, to improve the film quality of the follow-up anode be formed in via hole 1001, strengthen the conductivity of anode.
The forming process of via hole 1001 preferably can be: utilize the region of patterning processes to planarization layer via hole to be formed on planarization layer 901 expose and develop, and forms the planarization layer via hole exposing zinc oxide film 701; Patterning processes is utilized to form the photoresist layer with passivation layer via hole figure in the region of passivation layer via hole to be formed afterwards, with this photoresist layer for mask etching zinc oxide film 701 and passivation layer 601, until expose the surface (namely exposing the surface of connection metal layer) of the figure comprising source electrode 502 and drain electrode 501, form passivation layer via hole, this passivation layer via hole and planarization layer via hole form via hole jointly.
In above step, because zinc oxide film 701 is formed between passivation layer 601 and color rete 801, the rete that the via hole 1001 therefore formed after planarization layer 901 runs through successively is planarization layer 901, zinc oxide film 701 and passivation layer 601.
It should be noted that, the method that the present embodiment is only formed between passivation layer 601 and planarization layer 901 with zinc oxide film 701 has been described in detail, in other embodiment of the present utility model, after zinc oxide film also can be formed at planarization layer, the manufacture method that its detailed process can provide according to the present embodiment is out of shape accordingly, no longer describes in detail this.If after it is pointed out that zinc oxide film is formed at planarization layer, then the rete that the via hole formed after zinc oxide film runs through successively is zinc oxide film, planarization layer and passivation layer.In this case, concrete can be of forming process of via hole: after formation zinc oxide film, patterning processes is utilized to form the planarization layer via hole running through zinc oxide film and planarization layer, utilize patterning processes to form the passivation layer via hole running through passivation layer afterwards, this passivation layer via hole and planarization layer via hole form via hole jointly again.
Step S11: the planarization layer 901 in via hole 1001 and above color rete 801 forms anode layer 1101, as shown in figure 11.
Anode layer 1101 part is electrical connected by via hole 1001 and connection metal layer, and because connection metal layer is connected with the source electrode 502 of TFT, therefore anode layer 1101 and source electrode 502 are electrical connected, to be applied in certain voltage when TFT opens.Another part of anode layer 1101 is positioned at above color rete 801, as the pixel electrode of device.
The thickness of anode layer 1101 preferably can be 10nm ~ 100nm, and material preferably can be the transparent conductive materials such as ITO (IndiumTin Oxide, tin indium oxide).
In this step, the preferred sputtering technology that adopts plates transparent conductive film on the underlay substrate 101 having formed via hole 1001, forms anode layer 1101.
Step S12: form pixel and define layer 1201 on the underlay substrate 101 having formed anode layer 1101, as shown in figure 12.
Pixel defines figure layer 1201 with pixel openings region, and pixel defines layer 1201 for defining the open area of display unit pixel.
The thickness that pixel defines layer 1201 is preferably 1 μm ~ 2 μm, its thickness specifically can with the thickness strict conformance of the OLED of follow-up formation, the material that pixel defines layer 1201 is preferably organic material, with while definition open area, the anode layer 1101 remained in non-open areas insulate with other rete.
The forming process that pixel defines layer 1201 can be: adopt spin coating proceeding on underlay substrate, cover the organic material that pixel defines layer 1201, the pixel removing corresponding open area through photoetching process defines layer material, and being formed to have needs the pixel of figure to define layer 1201.
Step S13: each functional layer 1301 forming OLED on the underlay substrate 101 having formed pixel and define layer 1201, as shown in figure 13.
Each functional layer 1301 of OLED preferably can comprise along near underlay substrate 101 to the direction away from underlay substrate 101: hole transmission layer, luminescent layer, electron transfer layer, preferredly comprises: hole injection layer, hole transmission layer, luminescent layer, electron transfer layer, electron injecting layer.Wherein, hole transmission layer can adopt NPB that 50nm is thick (N, N '-diphenyl-N-N ' two (1-naphthyl)-1,1 ' diphenyl-4,4 '-diamines); The Doping Phosphorus luminescent material that the material of main part of luminescent layer can adopt 25nm thick, the luminescent layer glowed is needed to adopt CBP:Btp2Ir (acac), the luminescent layer of green light is needed to adopt CBP:(ppy) 2Ir (acac), need the luminescent layer of blue light-emitting to adopt CBP:FIrpic; Electron transfer layer can adopt the Bphen that 25nm is thick.
Each functional layer 1301 of OLED preferably can be formed by thermal evaporation evaporation in organic metal thin film deposition high vacuum system, and the vacuum degree in evaporate process can be 1 × 10
-5pa, the evaporation temperature of hole transmission layer and luminescent layer can be 170 DEG C, and the evaporation temperature of electron transfer layer can be 190 DEG C.
Step S14: form cathode layer 1401 in each functional layer 1301 of OLED, as shown in figure 14.
In this step, the material of cathode layer 1401 preferably can be the metal material of the high reflectances such as Ag or Mg, and its thickness can be 10nm ~ 100nm, with by the light reflection from top outgoing, towards underlay substrate 101 direction outgoing, improves light utilization.
Cathode layer 1401 preferably can adopt evaporation process to be formed, and temperature during evaporation can be about 900 DEG C.
It should be noted that, the array base palte that above-mentioned steps S1 ~ step S14 is formed is the array base palte of the display unit being applicable to OLED type, the light color that its luminescent layer produces is white, realize full-color light-emitting, step S8 is needed to form color rete 801, in other embodiment of the present utility model, if luminescent layer itself can produce the light of the solid color such as red, green, blue, Huang, then step S8 can be omitted, without the need to arranging color rete 801.On the other hand, the array base palte that the present embodiment is formed is end light-emitting type, and based on the manufacture method in the present embodiment, those skilled in the art can obtain by corresponding deformation the array base palte ejecting light type.On the other hand, the TFT of the array base palte that the present embodiment is formed is bottom gate ESL (Etch Stop Layer, etching barrier layer) structure, in other embodiment of the present utility model, the TFT of array base palte also can adopt the structure such as top grid, BCE (BackChannel Etching, back of the body channel etching).On the other hand, be out of shape by the manufacture method provided the present embodiment, as: adopt above-mentioned steps S1 ~ S10 to form TFT, form the pixel electrode be electrically connected with source and drain metal level by via hole after step slo, thus the array base palte being applicable to liquid crystalline type display unit can be obtained.
The present embodiment additionally provides a kind of display floater, comprises the array base palte that the present embodiment provides, and because the TFT stability of included array base palte is high, therefore this display floater has the measured advantage of display frame matter.
The display floater that the present embodiment provides can be liquid crystalline type, also can be OLED type.
The present embodiment additionally provides a kind of display unit, comprises the display floater that the present embodiment provides, and has the advantage that display quality is good.OLED display in the present embodiment can be any product or parts with Presentation Function such as mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
The foregoing is only embodiment of the present utility model; but protection range of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; the change that can expect easily or replacement, all should be encompassed within protection range of the present utility model.Therefore, protection range of the present utility model should be as the criterion with the protection range of described claim.
Claims (13)
1. an array base palte, comprise thin-film transistor, it is characterized in that, described array base palte also comprises: above the active layer being positioned at described thin-film transistor and/or the zinc oxide film of below, and the upright projection of described zinc oxide film on array base palte is at least overlapping with the upright projection of described active layer on array base palte.
2. array base palte according to claim 1, is characterized in that, described zinc oxide film is Nano zinc oxide film.
3. array base palte according to claim 1, is characterized in that, the thickness of described zinc oxide film is 5nm ~ 50nm.
4. array base palte according to claim 1, is characterized in that, the upright projection of described zinc oxide film on array base palte covers the upright projection of described active layer on array base palte.
5. array base palte according to claim 4, is characterized in that, the upright projection of described zinc oxide film on array base palte covers whole array base palte.
6. array base palte according to claim 1, it is characterized in that, also comprise: be set in turn in the passivation layer above described active layer and planarization layer, described zinc oxide film is between described passivation layer and described planarization layer or be positioned at above described planarization layer.
7. array base palte according to claim 6, is characterized in that, also comprises: be positioned at thin-film transistor drain electrode top and run through the via hole of described planarization layer, described zinc oxide film and described passivation layer.
8. array base palte according to claim 1, is characterized in that, also comprises: be arranged at the resilient coating below described active layer, and described zinc oxide film is positioned at the below of described resilient coating.
9. the array base palte according to any one of claim 1 ~ 8, is characterized in that, the material of described active layer is indium gallium zinc oxide.
10. the array base palte according to any one of claim 1 ~ 8, is characterized in that, also comprises: be arranged at the anode layer above described active layer, pixel defines layer, luminescent layer and cathode layer.
11. array base paltes according to claim 10, is characterized in that, also comprise: the color rete between described active layer and described anode layer.
12. 1 kinds of display floaters, is characterized in that, comprise the array base palte described in any one of claim 1 ~ 11.
13. 1 kinds of display unit, is characterized in that, comprise display floater according to claim 12.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420870677.6U CN204289541U (en) | 2014-12-31 | 2014-12-31 | Array base palte, display floater, display unit |
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| CN201420870677.6U CN204289541U (en) | 2014-12-31 | 2014-12-31 | Array base palte, display floater, display unit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104600081A (en) * | 2014-12-31 | 2015-05-06 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display panel and display device |
| CN109461763A (en) * | 2018-10-17 | 2019-03-12 | 深圳市华星光电技术有限公司 | The preparation method and display panel of display panel |
-
2014
- 2014-12-31 CN CN201420870677.6U patent/CN204289541U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104600081A (en) * | 2014-12-31 | 2015-05-06 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display panel and display device |
| WO2016107291A1 (en) * | 2014-12-31 | 2016-07-07 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, display panel and display device |
| CN109461763A (en) * | 2018-10-17 | 2019-03-12 | 深圳市华星光电技术有限公司 | The preparation method and display panel of display panel |
| CN109461763B (en) * | 2018-10-17 | 2021-04-27 | Tcl华星光电技术有限公司 | Preparation method of display panel and display panel |
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