CN103022083A - Array substrate, display device and preparing method of array substrate - Google Patents
Array substrate, display device and preparing method of array substrate Download PDFInfo
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- CN103022083A CN103022083A CN2012105304729A CN201210530472A CN103022083A CN 103022083 A CN103022083 A CN 103022083A CN 2012105304729 A CN2012105304729 A CN 2012105304729A CN 201210530472 A CN201210530472 A CN 201210530472A CN 103022083 A CN103022083 A CN 103022083A
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- array base
- base palte
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Abstract
The invention relates to the technical field of display, and discloses an array substrate, a display device and a preparing method of the array substrate. The array substrate comprises a thin film transistor device, the thin film transistor device comprises a semiconductor active layer, and the material quality of the semiconductor active layer of the thin film transistor device is microcrystalline silicon. The utilization of the microcrystalline silicon in the semiconductor active layer can improve the carrier mobility. In the provided preparing method of the array substrate, a source drain metal layer can conduct heat during the laser annealing, thereby enabling the noncrystalline silicon of the semiconductor active layer to be transformed into microcrystalline silicon and improving the carrier mobility of the array substrate, and further lowering the working voltage and power consumption and improving the resolution ratio and brightness of the display device. And, compared to a polycrystalline silicon array substrate, the disclosed array substrate has the advantages of being low in cost and simple in craft.
Description
Technical field
The present invention relates to the Display Technique field, relate in particular to the preparation method of a kind of array base palte, display unit and array base palte.
Background technology
Thin-film transistor (Thin Film Transistor is called for short TFT) is the device that a kind of semiconductor, metal and insulator film that forms with deposition forms.The array base palte that comprises TFT is widely used in liquid crystal display (Liquid Crystal Display is called for short LCD).The another one important application that comprises the array base palte of TFT is as the Organic Light Emitting Diode active driving of (Organic Light Emitting Diode is called for short OLED).OLED is a kind of novel Display Technique that grows up in nearly ten or twenty year, the advantage of comparing OLED with LCD has that driving voltage is low, the light-emitting component life-span is long, almost do not have visible angle and light leak problem, fast response time, dynamic menu are without motion blur phenomenon, need not backlight, low temperature resistant, be easy to large tracts of land preparation, thereby OLED is more and more paid attention to.OLED can be divided into two kinds of passive drive (Passive Matrix is called for short PM) OLED and active driving (Active Matrix is called for short AM) OLED according to the difference of type of drive.The structure of passive mode is simpler, drives to look electric current decision GTG, is mainly used on the small-size product, its resolution and image quality are pretty good, if but to have the problem that consumes power is large, the life-span is short toward the development of large scale application product, must adopt active type of drive.And active driving must use tft array substrate as its switching device.At active matrix liquid crystal display (Active Matrix Liquid Crystal Display, be called for short AMLCD) in, drive because its type of drive is voltage, adopt the low amorphous silicon of mobility just can meet the demands as the semiconductor active layer material of array base palte.And the type of drive of AMOLED is current drives, needs larger electric current just can meet the demands, and therefore must seek the switching device that the array base palte of high carrier mobility more is used as AMOLED.
At present, be applied to the array base palte that comprises TFT of AMOLED, different according to the semiconductor active layer material of TFT, mainly be divided into amorphous silicon array base palte and polysilicon array base palte.Wherein amorphous silicon (a-Si) is amorphous state, and without crystal boundary, its uniformity is better, and cost is low, but the lower (0.5 ~ 1cm of the carrier mobility of amorphous silicon
2V
-1s
-1); And polysilicon (p-Si) array base palte, its carrier mobility is high, but cost is also very high, and complex process.
Existing array base palte preparation technology is that sputter forms gate electrode on underlay substrate, deposition gate insulation layer, deposition a-Si semiconductor active layer, sputtering source drain electrode, deposit passivation layer, making through hole, sputter pixel electrode.
From the above, the carrier mobility of amorphous silicon array base palte is low in the prior art, and then its current carrying capacity is little, and operating voltage is high and power consumption is large, and the resolution of display unit prepared therefrom and brightness are low; And the cost of polysilicon array base palte is high, complex process.
Summary of the invention
The preparation method who the purpose of this invention is to provide a kind of array base palte, display unit and array base palte in order to improving carrier mobility, and then reduces operating voltage and power consumption.
Array base palte of the present invention comprises film transistor device, and described thin-film transistor comprises semiconductor active layer, and the material of the semiconductor active layer of described film transistor device is microcrystal silicon.
The material of the source-drain electrode of described film transistor device is copper molybdenum alloy.
Be provided with ohmic contact layer between the semiconductor active layer of described film transistor device and the source-drain electrode, the material of described ohmic contact layer is doped microcrystalline silicon.
The material of the gate electrode of described film transistor device is copper.
Described array base palte also comprises the pixel electrode that is electrically connected with drain electrode, and described pixel electrode material is tin indium oxide or indium gallium zinc oxide.
Display unit of the present invention comprises the described array base palte of aforementioned techniques scheme.The present invention be more particularly directed to the described array base palte of aforementioned techniques scheme and be used for active matrix organic light-emitting diode.
The preparation method of array base palte of the present invention may further comprise the steps:
Metal level is leaked in the formation source on semiconductor active layer, and the material that metal level is leaked in described source is copper molybdenum alloy;
Leak metal level in the source and form the metal molybdenum layer;
Substrate is carried out laser annealing;
After the laser annealing, remove the metal molybdenum layer, adopt composition technique to form source-drain electrode.
Described on semiconductor active layer the formation source leak metal level, be specially:
Adopt magnetron sputtering formation source on semiconductor active layer to leak metal level.
The preparation method of described array base palte was describedly also comprising before metal level is leaked in formation source on the semiconductor active layer:
Form gate electrode at underlay substrate;
Form the gate insulation layer of covering grid electrode and substrate at the substrate that forms gate electrode;
Form the semiconductor active layer that is positioned at above the gate electrode at the substrate that forms gate insulation layer, and be positioned at the ohmic contact layer on the semiconductor active layer.
The preparation method of described array base palte, adopt composition technique to form source-drain electrode and also comprise afterwards:
Formation is positioned on the source-drain electrode and the passivation layer of covered substrate;
Formation is positioned on the passivation layer and the pixel electrode that is electrically connected with drain electrode.
The beneficial effect that the present invention realizes is as follows at least:
Array base palte provided by the present invention, semiconductor active layer adopts microcrystal silicon, can improve carrier mobility.The preparation method of array base palte provided by the invention, source leakage metal level plays heat transfer effect during laser annealing, make the amorphous silicon of semiconductor active layer be converted into microcrystal silicon, so that the carrier mobility of array base palte improves, reduce operating voltage and power consumption, resolution and the brightness that can improve display unit.And with respect to the polysilicon array base palte, array base palte cost of the present invention is low, and technique is simple.
Description of drawings
Fig. 1 is array base-plate structure schematic diagram of the present invention;
Fig. 2 is the preparation method's of array base palte of the present invention schematic flow sheet.
Reference numeral:
1-substrate 2-gate electrode 3-gate insulation layer 4-semiconductor active layer 5-ohmic contact layer 6-source-drain electrode 7-passivation layer 8-pixel electrode 9-through hole
Embodiment
In order to improve the carrier mobility of amorphous silicon array base palte, the embodiment of the invention provides the preparation method of a kind of array base palte, display unit and array base palte.In this technical scheme, sputtering source leaks metal level on the amorphous silicon semiconductor active layer, by laser annealing, the effect that metal level plays heat transfer is leaked in the source, so that the amorphous silicon crystallization of semiconductor active layer is microcrystal silicon, can improve the carrier mobility of array base palte, reduce operating voltage and power consumption.For making the purpose, technical solutions and advantages of the present invention clearer, below lift specific embodiment the present invention is described in further detail.
As shown in Figure 1, one embodiment of array base palte of the present invention, semiconductor active layer 4 materials of its film transistor device are microcrystal silicon, with respect to the amorphous silicon semiconductor active layer, the microcrystalline silicon semiconductor active layer can improve the carrier mobility of array base palte, reduces operating voltage and power consumption.
Please continue with reference to Fig. 1, array base palte also comprises the source-drain electrode 6 of film transistor device, and source-drain electrode 6 materials are copper molybdenum alloy.The main component of source-drain electrode material is copper (Cu), and its resistivity is low, is beneficial to the power consumption that reduces array base palte.
Please continue with reference to Fig. 1, array base palte also comprises between the semiconductor active layer 4 of film transistor device and the source-drain electrode 6 and is provided with ohmic contact layer 5, the material of ohmic contact layer 5 is doped microcrystalline silicon, doped microcrystalline silicon is as ohmic contact layer, reduced the resistance between semiconductor active layer and source-drain electrode, be conducive to improve the carrier mobility of array base palte, can reduce operating voltage and the power consumption of array base palte.
Please continue with reference to Fig. 1, array base palte also comprises the gate electrode 2 of film transistor device, and the material of gate electrode 2 is Cu, and its resistivity is low, can further reduce the power consumption of array base palte.
Please continue with reference to Fig. 1, the pixel electrode 8 that array base palte also comprises and is electrically connected with drain electrode, pixel electrode 8 materials can be the ITO(tin indium oxide) or IGZO (indium gallium zinc oxide).Array base palte also comprises underlay substrate 1, gate insulation layer 3, passivation layer 7 and through hole 9.Underlay substrate 1 material is glass, and gate insulation layer 3 materials are SiN
x, passivation layer 7 materials are SiN
xThe gate insulation layer material is SiN
x, it to a certain extent can the blocking temperature transmission, the protection underlay substrate.
The array base palte of above-described embodiment, with respect to the amorphous silicon array base palte, semiconductor active layer is that the array base palte carrier mobility of microcrystal silicon increases; The material of source-drain electrode is mainly Cu, and its resistivity is low, can reduce operating voltage and the power consumption of array base palte.
The embodiment of the invention also provides a kind of display unit, comprises array base palte shown in Figure 1, and its carrier mobility improves greatly, and power consumption obviously reduces, and resolution and the brightness of display unit also significantly improve.
Described display unit is AMOLED particularly, other can for: liquid crystal panel, Electronic Paper, LCD TV, liquid crystal display, DPF, mobile phone, panel computer etc. have product or the parts of any Presentation Function.
As shown in Figure 2, preparation method one embodiment of array base palte of the present invention may further comprise the steps:
After step 104, the laser annealing, remove the metal molybdenum layer, adopt composition technique to form source-drain electrode.
Wherein, step 101 is specially: adopt magnetron sputtering formation source on semiconductor active layer to leak metal level.
Before step 101, also comprise:
Form gate electrode at underlay substrate;
Form the gate insulation layer of covering grid electrode and substrate at the substrate that forms gate electrode;
Form the semiconductor active layer that is positioned at above the gate electrode at the substrate that forms gate insulation layer, and be positioned at the ohmic contact layer on the semiconductor active layer.
After step 104, also comprise:
Formation is positioned on the source-drain electrode and the passivation layer of covered substrate;
Formation is positioned on the passivation layer and the pixel electrode that is electrically connected with drain electrode.
Below be preferred embodiment of preparation method of array base palte of the present invention, this preparation method specifically may further comprise the steps:
Splash-proofing sputtering metal copper (Cu) forms gate electrode on underlay substrate, utilizes gas bombardment metal Cu target, and the Cu atom sputtering to underlay substrate, is formed gate electrode layer, adopts composition technique, and is graphical to gate electrode layer, forms gate electrode;
Form the gate insulation layer of covering grid electrode and substrate at the substrate that forms gate electrode, specifically can adopt the ion enhanced chemical vapor deposition, the gate insulation layer material therefor is SiN
x, SiN
xHave the effect that certain blocking temperature transmits, this gate insulation layer has protective effect to underlay substrate during the subsequent step laser annealing;
The semiconductor active layer of the amorphous silicon (a-Si) above gate insulation layer formation is positioned at gate electrode specifically can adopt the ion enhanced chemical vapor deposition;
Form doped amorphous silicon (n at semiconductor active layer
+A-Si) ohmic contact layer specifically can adopt the ion enhanced chemical vapor deposition, and this layer can reduce the resistance between the source-drain electrode of making in semiconductor active layer and the subsequent step, can not make this layer according to arts demand;
Adopt composition technique graphical to semiconductor active layer and ohmic contact layer;
Metal level is leaked in the formation source on ohmic contact layer, adopts the method for magnetic control co-sputtering, and molybdenum (Mo) sheet is attached on the Cu target, utilizes the gas bombardment to post the Cu target of Mo sheet, and Cu and Mo cosputtering on ohmic contact layer, are formed the copper molybdenum alloy layer, and namely metal level is leaked in the source; Perhaps, sputter one Mo layer on ohmic contact layer, sputter one Cu layer on the Mo layer again, the two metal layers that forms Mo layer and Cu layer is leaked metal level as the source.Wherein, make this mode of copper molybdenum alloy layer and more be conducive to reduce cost, and its thicknesses of layers is thinner.When not making ohmic contact layer, directly metal level is leaked in the preparation source on patterned semiconductor active layer.Following steps are only take the copper molybdenum alloy layer as example;
At copper molybdenum alloy layer deposition layer of metal Mo, as photothermal transformation layer, this Mo layer can be converted into heat well with laser;
After forming the metal molybdenum layer, substrate is carried out laser annealing.By photothermal transformation layer, make laser be converted into heat, this heat makes the copper molybdenum alloy layer carry out crystallization, so that metal defect reduces, resistivity decreased, and then reduction power consumption improve resolution.Because Mo and Cu there is no solid solubility, the mixing of Mo and Cu is contained for just, so both difficult formation compounds, and Mo easily separates out from Cu during heating.Because Mo separates out, and is equivalent to form between ohmic contact layer and copper molybdenum alloy layer one deck Mo layer.The mixing of Mo and Si is contained, and it is-19kJ/mol therefore to compare with Mo that the mixing of Cu and Si is contained, Cu and Si more easily form compound, thereby the Mo layer of separating out can suppress the formation of Cu-Si compound, and the formation of Cu-Si compound can make resistivity increase, and increases power consumption; Metal Cu and Mo have good thermal conductivity simultaneously, can make the heat of laser conduct to the amorphous silicon semiconductor active layer, so that amorphous silicon is converted into microcrystal silicon, can improve carrier mobility like this.Only need carry out a laser annealing to source leakage metal level and semiconductor active layer, just can make the source leak the metal level defective and reduce, reduce resistivity; Also can make the amorphous silicon of semiconductor active layer be converted into microcrystal silicon, improve carrier mobility, thereby reduce operating voltage and the power consumption of array base palte;
Mo in the copper molybdenum alloy separates out, and is equivalent to deposit between amorphous silicon semiconductor active layer and copper molybdenum alloy one deck Mo, and this Mo layer has suppressed the formation of Cu-Si compound, makes the source-drain electrode resistivity decreased, has reduced the power consumption of array base palte;
Etch away the metal M o layer on copper molybdenum alloy layer surface, so that the resistivity decreased of metal level is leaked in the source;
The copper molybdenum alloy layer pattern adopts composition technique to form source-drain electrode, and etching ohmic contact layer and semiconductor active layer form groove;
Formation is positioned on the source-drain electrode and the passivation layer of covered substrate, and this passivation layer material therefor is SiN
x
Via hole image is so that drain electrode is electrically connected with the pixel electrode that forms afterwards;
Deposit ITO or IGZO on passivation layer and in the through hole as pixel electrode layer, graphical to pixel electrode layer, form pixel electrode, pixel electrode is electrically connected with drain electrode.
As seen, by above-mentioned preparation method, only need carry out a laser annealing to source leakage metal level and semiconductor active layer, can make the amorphous silicon of semiconductor active layer be converted into microcrystal silicon, improve carrier mobility; Also can make the source leak the metal level metal defect and reduce, reduce its resistivity, thereby reduce operating voltage and the power consumption of array base palte, the resolution and the brightness that improve display unit.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. an array base palte comprises film transistor device, and described thin-film transistor comprises semiconductor active layer, it is characterized in that, the material of the semiconductor active layer of described film transistor device is microcrystal silicon.
2. array base palte as claimed in claim 1 is characterized in that, the material of the source-drain electrode of described film transistor device is copper molybdenum alloy.
3. array base palte as claimed in claim 2 is characterized in that, is provided with ohmic contact layer between the semiconductor active layer of described film transistor device and the source-drain electrode, and the material of described ohmic contact layer is doped microcrystalline silicon.
4. array base palte as claimed in claim 1 is characterized in that, the material of the gate electrode of described film transistor device is copper.
5. array base palte as claimed in claim 1 is characterized in that, described array base palte also comprises the pixel electrode that is electrically connected with drain electrode, and described pixel electrode material is tin indium oxide or indium gallium zinc oxide.
6. a display unit is characterized in that, comprises each described array base palte such as claim 1-5.
7. the preparation method of an array base palte is characterized in that, said method comprising the steps of:
Metal level is leaked in the formation source on semiconductor active layer, and the material that metal level is leaked in described source is copper molybdenum alloy;
Leak metal level in the source and form the metal molybdenum layer;
Substrate is carried out laser annealing;
After the laser annealing, remove the metal molybdenum layer, adopt composition technique to form source-drain electrode.
8. the preparation method of array base palte as claimed in claim 7 is characterized in that, described on semiconductor active layer the formation source leak metal level, be specially:
Adopt magnetron sputtering formation source on semiconductor active layer to leak metal level.
9. the preparation method of array base palte as claimed in claim 7 is characterized in that, is describedly also comprising before metal level is leaked in formation source on the semiconductor active layer:
Form gate electrode at underlay substrate;
Form the gate insulation layer of covering grid electrode and substrate at the substrate that forms gate electrode;
Form the semiconductor active layer that is positioned at above the gate electrode at the substrate that forms gate insulation layer, and be positioned at the ohmic contact layer on the semiconductor active layer.
10. the preparation method of array base palte as claimed in claim 7 is characterized in that, adopts composition technique also to comprise after forming source-drain electrode:
Formation is positioned on the source-drain electrode and the passivation layer of covered substrate;
Formation is positioned on the passivation layer and the pixel electrode that is electrically connected with drain electrode.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103305795A (en) * | 2013-05-07 | 2013-09-18 | 苏州奕光薄膜科技有限公司 | Vacuum coating process of electronic device |
| CN105449001A (en) * | 2015-12-28 | 2016-03-30 | 昆山国显光电有限公司 | Thin film transistor and preparation method thereof |
| CN106024906A (en) * | 2016-07-18 | 2016-10-12 | 京东方科技集团股份有限公司 | Thin film transistor, display substrate and liquid crystal display device |
| CN106981426A (en) * | 2017-04-06 | 2017-07-25 | 京东方科技集团股份有限公司 | Preparation method, the display device of thin film transistor (TFT) |
| CN115132754A (en) * | 2022-06-30 | 2022-09-30 | 惠科股份有限公司 | Backlight module, preparation method thereof and display panel |
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| US20100109010A1 (en) * | 2008-10-31 | 2010-05-06 | Hitachi Displays, Ltd. | Display device |
| US20120146042A1 (en) * | 2010-12-08 | 2012-06-14 | Ki-Tae Kim | Micro-crystalline thin film transistor, display device including the same and manufacturing method thereof |
| CN102751302A (en) * | 2012-07-09 | 2012-10-24 | 上海奕瑞影像科技有限公司 | Microcrystal silicon thin-film detector preparation method and application thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20100109010A1 (en) * | 2008-10-31 | 2010-05-06 | Hitachi Displays, Ltd. | Display device |
| US20120146042A1 (en) * | 2010-12-08 | 2012-06-14 | Ki-Tae Kim | Micro-crystalline thin film transistor, display device including the same and manufacturing method thereof |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103305795A (en) * | 2013-05-07 | 2013-09-18 | 苏州奕光薄膜科技有限公司 | Vacuum coating process of electronic device |
| CN105449001A (en) * | 2015-12-28 | 2016-03-30 | 昆山国显光电有限公司 | Thin film transistor and preparation method thereof |
| CN106024906A (en) * | 2016-07-18 | 2016-10-12 | 京东方科技集团股份有限公司 | Thin film transistor, display substrate and liquid crystal display device |
| CN106981426A (en) * | 2017-04-06 | 2017-07-25 | 京东方科技集团股份有限公司 | Preparation method, the display device of thin film transistor (TFT) |
| CN106981426B (en) * | 2017-04-06 | 2020-04-03 | 京东方科技集团股份有限公司 | Preparation method of thin film transistor and display device |
| CN115132754A (en) * | 2022-06-30 | 2022-09-30 | 惠科股份有限公司 | Backlight module, preparation method thereof and display panel |
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| CN103022083B (en) | 2015-07-22 |
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