CN202977421U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN202977421U CN202977421U CN 201220694817 CN201220694817U CN202977421U CN 202977421 U CN202977421 U CN 202977421U CN 201220694817 CN201220694817 CN 201220694817 CN 201220694817 U CN201220694817 U CN 201220694817U CN 202977421 U CN202977421 U CN 202977421U
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- electrode
- array base
- base palte
- substrate
- channel region
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Abstract
The utility model provides an array substrate and a display device and belongs to the field of display. A channel region, a source electrode and a drain electrode of the array substrate are formed through the one-step pattern composition technique. Specifically, a channel region, a source region and a drain region formed by metal oxide layers are formed through the one-step pattern composition technique. The metal oxide layers in the source region and the drain region are subjected to thermal treatment in the hydrogen gas and form the source electrode and the drain electrode respectively. The manufacture technique of the array substrate can be simplified, and manufacture cost of the array substrate can be reduced.
Description
Technical field
The utility model relates to the demonstration field, refers to especially a kind of array base palte and display unit.
Background technology
In prior art, amorphous silicon hydride TFT(Thin Film Transistor, thin-film transistor) be difficult to satisfy LCD TV that size constantly increases and the demand of more high performance drive circuit.Transparent non-crystal oxide semiconductor TFT is subject to researcher's favor with its many advantages, development recent years rapidly.Its mobility is high, homogeneity good, transparent, manufacture craft is simple, can satisfy better large scale liquid crystal display and OLED(Organic Light-Emitting Diode, organic electroluminescent) demand of display.In addition, make transparent non-crystal oxide semiconductor TFT and existing LCD(Liquid CrystalDisplay, liquid crystal display) the production line matching is good, easy transition, therefore the transparent non-crystal oxide semiconductor TFT of high-performance enjoys people's concern, has become nearest study hotspot.
But the manufacture craft of existing transparent non-crystal oxide semiconductor TFT is comparatively complicated; at least need five composition techniques just can complete the making of bottom gate type array base palte; and need ESL(Etch stoppinglayer etching barrier layer) and PVX(passivation; passivation layer) multilayer protection guarantee TFT performance is stable, and manufacturing cost is very high.
The utility model content
The technical problems to be solved in the utility model is to provide a kind of array base palte and display unit, can simplify the manufacture craft of array base palte, reduces the manufacturing cost of array base palte.
For solving the problems of the technologies described above, embodiment of the present utility model provides technical scheme as follows:
On the one hand, provide a kind of array base palte, the channel region of described array base palte and source electrode, electric leakage very adopt a composition technique to form.
Further, the pixel electrode of described array base palte, channel region and source electrode, electric leakage very adopt a composition technique to form.
Further, described channel region and source electrode, electric leakage very adopt metal oxide to form.
Further, described pixel electrode, channel region and source electrode, electric leakage very adopt metal oxide to form.
Further, described metal oxide is IGZO or ZnO.
Further, described array base palte comprises:
Be positioned at gate electrode and grid line on substrate;
Be positioned at the gate insulation layer on the substrate that is formed with described gate electrode and grid line;
Be positioned at the pixel electrode on described gate insulation layer;
Be positioned at channel region, source electrode and the drain electrode that is connected with described pixel electrode on the substrate that is formed with described pixel electrode;
Be positioned at the passivation layer on the substrate that is formed with described channel region, source electrode and drain electrode, described passivation layer includes to draw the via hole of described source electrode and drain electrode.
Further, described array base palte comprises:
Be positioned at gate electrode and grid line on substrate;
Be positioned at the gate insulation layer on the substrate that is formed with described gate electrode and grid line;
Be positioned at pixel electrode, channel region, source electrode and the drain electrode that is connected with described pixel electrode on described gate insulation layer;
Be positioned at the passivation layer on the substrate that is formed with described channel region, source electrode and drain electrode.
The utility model embodiment also provides a kind of display unit, comprises array base palte as above.
Embodiment of the present utility model has following beneficial effect:
In such scheme, the channel region of array base palte and source electrode, electric leakage very adopt a composition technique to form, do not need to adopt again extra composition technique to make source electrode and drain electrode, simplified the production technology of array base palte, reduced the deposition of exposure technology and metal level, greatly shortened array base palte manufacturing time, reduced the production cost of array base palte.
Description of drawings
Fig. 1 is the utility model embodiment schematic cross-section after depositing metal layers on substrate;
Fig. 2 is the utility model embodiment schematic cross-section of composition technique array base palte afterwards for the first time;
Fig. 3 is the schematic cross-section that the utility model embodiment deposits gate insulation layer and transparency conducting layer array base palte afterwards;
Fig. 4 is the utility model embodiment schematic cross-section of composition technique array base palte afterwards for the second time;
Fig. 5 is the floor map that the utility model embodiment deposits IGZO and protective layer array base palte afterwards;
Fig. 6 is the utility model embodiment schematic cross-section of composition technique array base palte afterwards for the third time;
To be the utility model embodiment process the IGZO in drain region and source region Fig. 7, and etch away the schematic cross-section of the array base palte after protective layer on channel region;
Fig. 8 is the floor map of the array base palte after the utility model embodiment deposit passivation layer;
Fig. 9 is the schematic cross-section of the array base palte after the 4th composition technique of the utility model embodiment;
Figure 10 is the schematic cross-section of the array base palte of another embodiment of the present invention;
Figure 11 is the floor map of the array base palte of another embodiment of the present invention;
Figure 12 is the floor map of the array base palte of yet another embodiment of the invention.
Reference numeral
1 substrate
2 gate electrodes
3 gate insulation layers
4 source electrodes
5 drain electrodes
6 active layers
7 transparency conducting layers
8 contact conductors
9 protective layers
10 passivation layers
11 grid lines
12 data wires
Embodiment
For technical problem, technical scheme and advantage that embodiment of the present utility model will be solved is clearer, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
Embodiment of the present utility model is comparatively complicated for the manufacture craft of transparent non-crystal oxide semiconductor TFT in prior art; at least need five composition techniques just can complete the making of bottom gate type array base palte; and need the stable of ESL and PVX multilayer protection guarantee TFT performance; the problem that manufacturing cost is very high; a kind of array base palte and display unit are provided; can simplify the manufacture craft of array base palte, reduce the manufacturing cost of array base palte.
The utility model embodiment provides a kind of array base palte, and the channel region of this array base palte and source electrode, electric leakage very adopt a composition technique to form.
Particularly, the channel region of this array base palte and source electrode, electric leakage very adopt metal oxide to form.Metal oxide is IGZO or ZnO, and when adopting IGZO formation channel region and source electrode, drain electrode, described source electrode and electric leakage very utilize IGZO to form after heat treatment 1-2 hour in the hydrogen of 250-400 ℃.
Further, the pixel electrode of the array base palte of the present embodiment, channel region and source electrode, drain electrode can also form for adopting a composition technique.Particularly, the pixel electrode of this array base palte, channel region and source electrode, electric leakage very adopt metal oxide to form.Metal oxide is IGZO or ZnO, and when adopting IGZO to form pixel electrode, channel region and source electrode, drain electrode, described pixel electrode, source electrode and electric leakage very utilize IGZO to form after heat treatment 1-2 hour in the hydrogen of 250-400 ℃.
Further, described array base palte comprises:
Be positioned at gate electrode and grid line on substrate;
Be positioned at the gate insulation layer on the substrate that is formed with described gate electrode and grid line;
Be positioned at the pixel electrode on described gate insulation layer;
Be positioned at channel region, source electrode and the drain electrode that is connected with described pixel electrode on the substrate that is formed with described pixel electrode;
Be positioned at the passivation layer on the substrate that is formed with described channel region, source electrode and drain electrode, described passivation layer includes to draw the via hole of described source electrode and drain electrode.
At this moment, the manufacture method of this array base palte specifically comprises the following steps:
One substrate is provided;
Form the gate electrode that formed by metal level and the figure of grid line by composition technique for the first time on described substrate;
Forming gate insulation layer through on the substrate of the described technique of composition for the first time;
Form the figure of the pixel electrode that is formed by transparency conducting layer by composition technique for the second time on described gate insulation layer;
By composition technique for the third time through forming channel region, source region and the drain region that is formed by metal oxide layer on the substrate of the described technique of composition for the second time, metal oxide layer to source region and drain region is heat-treated in hydrogen, forms respectively the source electrode and the drain electrode that is connected with described pixel electrode of conduction;
Form passivation layer by the 4th composition technique on the substrate that forms active electrode and drain electrode, and form via hole on passivation layer, to draw described source electrode and drain electrode.
Further, described composition technique formation is comprised of metal oxide layer on the process substrate of the described technique of composition for the second time channel region, source region and the drain region for the third time of passing through, metal oxide layer to source region and drain region is heat-treated in hydrogen, and the source electrode that forms respectively conduction comprises with the drain electrode that is connected with described pixel electrode:
Depositing successively IGZO layer and protective layer through on the substrate of the described technique of composition for the second time;
Form channel region, source region, drain region and be positioned at protective layer on described channel region by composition technique for the third time;
To the IGZO layer in the source region that exposes and drain region in the hydrogen of 250-400 ℃ heat treatment 1-2 hour, form respectively source electrode and the drain electrode of conduction.
Further, described array base palte comprises:
Be positioned at gate electrode and grid line on substrate;
Be positioned at the gate insulation layer on the substrate that is formed with described gate electrode and grid line;
Be positioned at pixel electrode, channel region, source electrode and the drain electrode that is connected with described pixel electrode on described gate insulation layer;
Be positioned at the passivation layer on the substrate that is formed with described channel region, source electrode and drain electrode.
At this moment, the manufacture method of described array base palte specifically comprises the following steps:
One substrate is provided;
Form the gate electrode that formed by metal level and the figure of grid line by composition technique for the first time on described substrate;
Forming gate insulation layer through on the substrate of the described technique of composition for the first time;
Form by composition technique for the second time pixel electrode district, channel region, source region and the drain region that is formed by metal oxide layer on described gate insulation layer, metal oxide layer to pixel electrode district, source region and drain region is heat-treated in hydrogen, forms respectively pixel electrode, source electrode and the drain electrode that is connected with described pixel electrode of conduction;
Form passivation layer by composition technique for the third time on the substrate that forms active electrode and drain electrode, and form via hole on passivation layer, to draw described source electrode and drain electrode.
The channel region of the array base palte of the utility model embodiment and source electrode, electric leakage very adopt a composition technique to form, do not need like this to adopt again extra composition technique to make source electrode and drain electrode, simplified the production technology of array base palte, reduced the deposition of exposure technology and metal level, greatly shortened array base palte manufacturing time, reduced the production cost of array base palte.
IGZO forms channel region and source electrode to the below, the very example of leaking electricity to adopt, and in conjunction with specific embodiments array base palte of the present utility model and manufacture method thereof is further introduced:
As shown in Fig. 1-9, the manufacture method of the array base palte of the present embodiment comprises the following steps:
Step 1 a: substrate is provided, forms the gate electrode that formed by metal level and the figure of grid line by composition technique for the first time on substrate;
Particularly, this substrate can be transparency carrier.As depicted in figs. 1 and 2, plated metal on substrate 1 forms gate electrode 2 and grid line by composition technique for the first time.
Particularly, can utilize magnetron sputtering deposition a layer thickness to be the metal level of 200nm-400nm on substrate 1, wherein, metal level can adopt any or the alloy of at least two kinds of metals wherein in Nd, Cr, W, Ti, Ta, Mo, Al and Cu; Apply afterwards photoresist on metal level, utilize mask plate to photoresist exposes, development and etching form gate electrode 2 and grid line figure.
Step 2: form gate insulation layer on the substrate through composition technique for the first time, form the figure of the pixel electrode that is formed by transparency conducting layer by composition technique for the second time on gate insulation layer;
As shown in Figure 3 and Figure 4, successive sedimentation gate insulation layer 3 and transparency conducting layer on the substrate 1 of completing steps 1, particularly, gate insulation layer can adopt SiN
x, SiO
2, Al
2O
3, AlN or resin, transparency conducting layer can adopt ITO, and pass through afterwards for the second time composition technique forms pixel electrode 7 on gate insulation layer 3.
Particularly, can utilize magnetron sputtering deposit thickness on the substrate 1 of completing steps 1 to be the Al of 400nm
2O
3Or AlN, perhaps utilizing PECVD(Plasma Enhanced Chemical VaporDeposition, the plasma enhanced chemical vapor deposition method) deposit thickness is the SiN of 400nm on the substrate 1 of completing steps 1
x, recycling afterwards magnetron sputtering deposition thickness is the ITO layer of 40nm, applies photoresist on the ITO layer, utilizes mask plate to photoresist exposes, development and etching form pixel electrode 7 figure.
Step 3: form channel region, source region and the drain region that is formed by the IGZO layer by composition technique for the third time on the substrate through composition technique for the second time, the IGZO layer in source region and drain region is heat-treated in hydrogen, form respectively source electrode and the drain electrode that conducts electricity;
As Fig. 5, Fig. 6 and shown in Figure 7; deposition one deck IGZO and protective layer on the substrate 1 of completing steps 2; by the channel region 6 of composition technique formation for the third time; source region and drain region; wherein, protective layer 9 is directly over channel region 6, and the IGZO that exposes is heat-treated in hydrogen; making becomes the source of conductor nature electrode 4 and drain electrode 5, and drain electrode 5 is connected with pixel electrode 7.
IGZO can be used as the material of active layer, and after heat-treating in hydrogen, IGZO can conduct electricity, the present embodiment utilizes this characteristic of IGZO, form simultaneously channel region, source region and drain region by a composition technique, afterwards the IGZO in source region and drain region processed, made it become respectively source electrode and the drain electrode, thereby reduced the composition technique of making together source electrode and drain electrode.
Particularly, can utilize magnetron sputtering on the substrate 1 of completing steps 2 deposit thickness for the amorphous oxide thin film IGZO of 50nm as active layer, be the SiN of 500nm afterwards with the PECVD deposit thickness
xAs protective layer 9; apply photoresist on protective layer 9; utilize mask plate to photoresist expose, development and etching form structure as shown in Figure 6; wherein leave protective layer 9 on channel region 6, source region and drain region are what expose, in atmosphere of hydrogen; to the IGZO in the source region that exposes and drain region through 250-400 ℃ of high-temperature heat treatment 1-2 hour; make it become respectively source electrode 4 and the drain electrode 5 with conductor nature, etch away afterwards protective layer 9, form structure as shown in Figure 7.
Step 4: form the figure of passivation layer by the 4th composition technique on the substrate that forms active electrode and drain electrode.
As Fig. 8 and shown in Figure 9, deposit passivation layer on the substrate 1 of completing steps 3 forms the figure of the passivation layer 10 with via hole by the 4th composition technique, and source electrode 4 is connected with contact conductor 8 by via hole respectively with drain electrode 5.Contact conductor 8 is connected with peripheral drive circuit, and being used for provides data-signal to the source electrode.Particularly, passivation layer 10 can adopt SiO
2Or SiN
x
Particularly, can utilize PECVD deposit thickness on the substrate 1 of completing steps 3 to be the passivation layer 10 of 200nm ~ 400nm, apply one deck photoresist on passivation layer 10, utilize mask plate to photoresist expose, development and etching form structure as shown in Figure 9, and adopt contact conductor 8 to draw source electrode 4 and drain electrode 5.
Finally, formed array base palte as shown in Figure 9 through above-mentioned steps 1-4, this array base palte comprises:
Be positioned at gate electrode 2 and grid line on substrate 1;
Be positioned at the gate insulation layer 3 on the substrate 1 that is formed with gate electrode 2 and grid line;
Be positioned at the pixel electrode 7 on gate insulation layer 3;
Be positioned at channel region 6, source electrode 4 and drain electrode 5 on the substrate 1 that is formed with pixel electrode 7, drain electrode 5 is connected with pixel electrode 7;
Be positioned at the passivation layer that includes via hole 10 on the substrate 1 that is formed with channel region 6, source electrode 4 and drain electrode 5, source electrode 4 is connected with contact conductor 8 by via hole respectively with drain electrode 5.
in the utility model embodiment, the channel region of array base palte and source electrode, electric leakage very adopts a composition technique to form, adopt altogether four composition techniques to prepare the amorphous oxide thin film transistor (TFT) array substrate, by the active layer IGZO that exposes is heat-treated in atmosphere of hydrogen, making becomes the source of conductor nature electrode and drain electrode, do not need separately to add the manufacture craft of source electrode and drain electrode, simplified the manufacture craft of array base palte, reduced the deposition of exposure technology and metal level, greatly shortened the manufacturing time of array base palte, reduced the cost of manufacture of array base palte.
Further, as shown in Figure 10 and Figure 11, the array base palte of the utility model embodiment can also need not be made contact conductor, draws data wire from the edge of array base palte and gets final product input data signal.Further, as shown in figure 12, due to the incomplete cover data line 12 of passivation layer 10, therefore do not need to arrange passivation layer via hole, can make the data wire 12 external data-signals of transmission yet.
The utility model also provides a kind of display unit, comprises array base palte as above.Particularly, display unit can be liquid crystal indicator, such as liquid crystal panel, LCD TV, mobile phone, liquid crystal display etc., and it comprises the array base palte in color membrane substrates and above-described embodiment; Except liquid crystal indicator, display unit can also be the display unit of other types, and such as electronic reader etc., it does not comprise color membrane substrates, but comprises the array base palte in above-described embodiment.
It is more than preferred implementation of the present utility model; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection range of the present utility model.
Claims (8)
1. an array base palte, is characterized in that, the channel region of described array base palte and source electrode, electric leakage very adopt a composition technique to form.
2. array base palte according to claim 1, is characterized in that, the pixel electrode of described array base palte, channel region and source electrode, electric leakage very adopt a composition technique to form.
3. array base palte according to claim 1, is characterized in that, described channel region and source electrode, electric leakage very adopt metal oxide to form.
4. array base palte according to claim 2, is characterized in that, described pixel electrode, channel region and source electrode, electric leakage very adopt metal oxide to form.
5. according to claim 3 or 4 described array base paltes, is characterized in that, described metal oxide is IGZO or ZnO.
6. array base palte according to claim 1, is characterized in that, described array base palte comprises:
Be positioned at gate electrode and grid line on substrate;
Be positioned at the gate insulation layer on the substrate that is formed with described gate electrode and grid line;
Be positioned at the pixel electrode on described gate insulation layer;
Be positioned at channel region, source electrode and the drain electrode that is connected with described pixel electrode on the substrate that is formed with described pixel electrode;
Be positioned at the passivation layer on the substrate that is formed with described channel region, source electrode and drain electrode, described passivation layer includes to draw the via hole of described source electrode and drain electrode.
7. array base palte according to claim 1, is characterized in that, described array base palte comprises:
Be positioned at gate electrode and grid line on substrate;
Be positioned at the gate insulation layer on the substrate that is formed with described gate electrode and grid line;
Be positioned at pixel electrode, channel region, source electrode and the drain electrode that is connected with described pixel electrode on described gate insulation layer;
Be positioned at the passivation layer on the substrate that is formed with described channel region, source electrode and drain electrode.
8. a display unit, is characterized in that, comprises array base palte as described in any one in claim 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220694817 CN202977421U (en) | 2012-12-14 | 2012-12-14 | Array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220694817 CN202977421U (en) | 2012-12-14 | 2012-12-14 | Array substrate and display device |
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|---|---|
| CN202977421U true CN202977421U (en) | 2013-06-05 |
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| CN 201220694817 Expired - Lifetime CN202977421U (en) | 2012-12-14 | 2012-12-14 | Array substrate and display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021942A (en) * | 2012-12-14 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, display device |
| CN105185708A (en) * | 2015-09-21 | 2015-12-23 | 西安交通大学 | Amorphous IGZO transparent oxide thin film by H2 processing and preparation method thereof |
| WO2018232789A1 (en) * | 2017-06-22 | 2018-12-27 | 深圳市华星光电技术有限公司 | Metallic oxide film transistor, manufacturing method therefor, and display panel |
-
2012
- 2012-12-14 CN CN 201220694817 patent/CN202977421U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021942A (en) * | 2012-12-14 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, display device |
| CN103021942B (en) * | 2012-12-14 | 2015-08-12 | 京东方科技集团股份有限公司 | Array base palte and manufacture method, display unit |
| US9165954B2 (en) | 2012-12-14 | 2015-10-20 | Boe Technology Group Co., Ltd. | Array substrate and method for manufacturing the same, and display device |
| CN105185708A (en) * | 2015-09-21 | 2015-12-23 | 西安交通大学 | Amorphous IGZO transparent oxide thin film by H2 processing and preparation method thereof |
| WO2018232789A1 (en) * | 2017-06-22 | 2018-12-27 | 深圳市华星光电技术有限公司 | Metallic oxide film transistor, manufacturing method therefor, and display panel |
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Granted publication date: 20130605 |
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| CX01 | Expiry of patent term |