CN210156377U

CN210156377U - Oxide thin film transistor and display device

Info

Publication number: CN210156377U
Application number: CN201921705912.3U
Authority: CN
Inventors: 邵喜斌; 廖燕平; 郭会斌
Original assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Priority date: 2019-10-12
Filing date: 2019-10-12
Publication date: 2020-03-17
Anticipated expiration: 2029-10-12

Abstract

The utility model provides an oxide thin film transistor, display device relates to thin film transistor technical field, and the local degradation appears easily in the oxide active layer among the solution oxide thin film transistor, and then influences the problem of display panel yield. The oxide thin film transistor includes: a gate electrode; the first active layer structure comprises a first conductive connecting part and a second conductive connecting part which are oppositely arranged, and a first oxide semiconductor pattern which is respectively coupled with the first conductive connecting part and the second conductive connecting part; the second active layer structure comprises a third conductive connecting part and a fourth conductive connecting part which are oppositely arranged, and a second oxide semiconductor pattern which is respectively coupled with the third conductive connecting part and the fourth conductive connecting part; the second conductive connection portion is coupled to the third conductive connection portion. The utility model provides an oxide thin film transistor is used for driving the pixel and gives out light.

Description

Oxide thin film transistor and display device

Technical Field

The utility model relates to a thin film transistor technical field especially relates to an oxide thin film transistor, display device.

Background

The oxide thin film transistor is the first choice of a display panel with large size, high resolution, low power consumption and narrow frame due to the advantages of high electron mobility, low off-state current, simple preparation process and the like. However, in the manufacturing process of the oxide thin film transistor, the oxide active layer is easily locally degraded due to the instability of the preparation process of the oxide active layer, and the yield of the display panel is affected.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide an oxide thin film transistor, display device for local degradation appears easily in the oxide active layer among the solution oxide thin film transistor, and then influences the problem of display panel yield.

In order to achieve the above object, the present invention provides the following technical solutions:

a first aspect of the present invention provides an oxide thin film transistor, including:

a gate electrode disposed on the substrate;

at least two active layer structures that arrange in proper order along first direction, at least two active layer structures include first active layer structure and second active layer structure, first active layer structure includes: the semiconductor device comprises a first conductive connecting part, a second conductive connecting part and a first oxide semiconductor pattern, wherein the first conductive connecting part and the second conductive connecting part are oppositely arranged, and the first oxide semiconductor pattern is positioned between the first conductive connecting part and the second conductive connecting part and is respectively coupled with the first conductive connecting part and the second conductive connecting part; the second active layer structure includes: a third conductive connection portion and a fourth conductive connection portion which are oppositely arranged, and a second oxide semiconductor pattern which is located between the third conductive connection portion and the fourth conductive connection portion and is respectively coupled with the third conductive connection portion and the fourth conductive connection portion; the orthographic projection of the first oxide semiconductor pattern on the substrate and the orthographic projection of the second oxide semiconductor pattern on the substrate are both positioned inside the orthographic projection of the grid electrode on the substrate; the second conductive connection is coupled with the third conductive connection.

Optionally, an orthographic projection of the first conductive connection portion on the substrate and an orthographic projection of the first oxide semiconductor pattern on the substrate form a first overlapping region;

the orthographic projection of the second conductive connecting part on the substrate and the orthographic projection of the first oxide semiconductor pattern on the substrate form a second overlapping area;

the orthographic projection of the third conductive connecting part on the substrate and the orthographic projection of the second oxide semiconductor pattern on the substrate form a third overlapping area;

an orthographic projection of the fourth conductive connecting part on the substrate and an orthographic projection of the second oxide semiconductor pattern on the substrate form a fourth overlapping area;

the second and third overlap regions are located between the first and fourth overlap regions.

Optionally, the thin film transistor further includes a first strap, the second conductive connection portion and the third conductive connection portion are coupled by the first strap, and an orthographic projection of the first strap on the substrate does not overlap with an orthographic projection of the first oxide semiconductor pattern on the substrate and does not overlap with an orthographic projection of the second oxide semiconductor pattern on the substrate.

Optionally, the first oxide semiconductor pattern and the second oxide semiconductor pattern are sequentially arranged along a first direction, and are staggered along a second direction perpendicular to the first direction.

Optionally, an orthographic projection of the first oxide semiconductor pattern in the second direction forms a fifth overlapping region with an orthographic projection of the second oxide semiconductor pattern in the second direction, the second conductive connection portion, the first bridging portion and the third conductive connection portion form an integrated straight-line structure extending along the second direction, and a size of the fifth overlapping region in the first direction is the same as a width of the straight-line structure along the first direction.

Optionally, the first oxide semiconductor pattern and the second oxide semiconductor pattern are formed as an integrated structure, and the second conductive connection portion is multiplexed as the third conductive connection portion.

Optionally, the first conductive connection portion includes a first portion extending in a second direction perpendicular to the first direction, and a second portion extending from the first portion in the second direction, an orthographic projection of the first portion on the substrate and an orthographic projection of the first oxide semiconductor pattern on the substrate form the first overlap region, and an orthographic projection of the second portion on the substrate and an orthographic projection of the first oxide semiconductor pattern on the substrate do not overlap.

Optionally, the fourth conductive connection portion includes a third portion and a fourth portion, the third portion extends along a second direction perpendicular to the first direction, and an orthographic projection of the third portion on the substrate overlaps with an orthographic projection of the second oxide semiconductor pattern on the substrate to form the fourth overlapping area;

the fourth portion extends along the first direction, an orthographic projection of the fourth portion on the substrate does not overlap with an orthographic projection of the second oxide semiconductor pattern on the substrate, the fourth portion is coupled with a first end of the third portion, and the orthographic projection of the first end on the substrate does not overlap with the orthographic projection of the second oxide semiconductor pattern on the substrate.

in a second direction perpendicular to the first direction, the second overlap region and the third overlap region are located on a first side of the first oxide semiconductor pattern, the first overlap region and the fourth overlap region are located on a second side of the second oxide semiconductor pattern, and the first side and the second side are opposite.

Optionally, the thin film transistor further includes a second strap, the second conductive connection portion and the third conductive connection portion are coupled by the second strap, and an orthographic projection of the second strap on the substrate does not overlap with an orthographic projection of the first oxide semiconductor pattern on the substrate and does not overlap with an orthographic projection of the second oxide semiconductor pattern on the substrate;

the second conductive connection portion, the second lap joint portion, and the third conductive connection portion are formed in a straight structure along the first direction.

Optionally, the first conductive connection portion includes a fifth portion and a sixth portion coupled to each other, the fifth portion extends along the first direction, and an orthographic projection of the fifth portion on the substrate and an orthographic projection of the first oxide semiconductor pattern on the substrate form the first overlap region; the sixth portion extends in the second direction, and an orthogonal projection of the sixth portion on the substrate does not overlap with an orthogonal projection of the first oxide semiconductor pattern on the substrate.

Optionally, the fourth conductive connecting part includes a seventh part, an eighth part and a ninth part; wherein the content of the first and second substances,

the seventh portion extends in the first direction, and an orthographic projection of the seventh portion on the substrate and an orthographic projection of the second oxide semiconductor pattern on the substrate form the fourth overlap region;

the ninth portion extends in the first direction, and an orthogonal projection of the ninth portion on the substrate does not overlap an orthogonal projection of the second oxide semiconductor pattern on the substrate;

the eighth portion extends in the second direction, an orthogonal projection of the eighth portion on the substrate is located between an orthogonal projection of the seventh portion on the substrate and an orthogonal projection of the ninth portion on the substrate, and does not overlap with an orthogonal projection of the second oxide semiconductor pattern on the substrate, and the seventh portion is coupled to the ninth portion through the eighth portion.

Optionally, the first oxide semiconductor pattern and the second oxide semiconductor pattern are disposed in the same layer and the same material.

Based on the technical scheme of above-mentioned oxide thin film transistor, the utility model discloses a second aspect provides a display device, includes above-mentioned oxide thin film transistor.

The utility model provides an among the technical scheme, include in setting up Oxide thin film transistor at least two active layer structures, make Oxide thin film transistor can form the channel structure of two at least series connection at the during operation, works as like when Oxide semiconductor figure in the active layer structure among the Oxide thin film transistor takes place to deteriorate, only can influence the performance of the sub Oxide TFT that this active layer structure corresponds, even make the characteristic curve of this sub Oxide TFT take place to move to the left, and other sub Oxide TFTs still keep normal operating condition.

In more detail, when the Oxide semiconductor pattern of one sub Oxide TFT is deteriorated, both the on-state current Ion and the off-state current Ioff of the sub Oxide TFT are increased, so that under the condition that each sub Oxide TFT is controlled to be in a conducting state and the whole Oxide thin film transistor is conducted, the on-state current Ion of the whole Oxide thin film transistor is increased under the influence of the on-state current Ion of the sub Oxide TFT, and the charging capability of the Oxide thin film transistor is effectively improved; on the other hand, when the Oxide thin film transistor is turned off, each of the sub Oxide TFTs is in an off state, and therefore, even if the off-state current Ioff of the sub Oxide TFT increases, the off-state current Ioff of the entire Oxide thin film transistor is not affected by the increased off-state current Ioff, and the off-state current Ioff of the entire Oxide thin film transistor can be maintained at a low level. Therefore, the embodiment of the utility model provides an oxide thin film transistor not only has higher stability, has stronger driving force moreover, is using the utility model provides a when the pixel among the oxide thin film transistor drive display panel is luminous, it is bad to have avoided display panel to produce drive bright spot and sand grain mura.

Drawings

The accompanying drawings, which are described herein, serve to provide a further understanding of the invention and constitute a part of this specification, and the exemplary embodiments and descriptions thereof are provided for explaining the invention without unduly limiting it. In the drawings:

fig. 1 is a schematic view of a first structure of an oxide thin film transistor according to an embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating the degradation of the active layer structure of an oxide thin film transistor of a first structure;

fig. 3 is a schematic diagram of a second structure of an oxide thin film transistor according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating the degradation of the active layer structure of an oxide TFT of a second structure;

fig. 5 is a schematic diagram of a third structure of an oxide thin film transistor according to an embodiment of the present invention;

FIG. 6 is a schematic cross-sectional view taken along line A1A2 in FIG. 5;

fig. 7 is a schematic diagram showing the deterioration of the active layer structure of the oxide thin film transistor of the third structure;

fig. 8 is a fourth schematic structural diagram of an oxide thin film transistor according to an embodiment of the present invention;

fig. 9 is a schematic diagram showing the deterioration of the active layer structure of the oxide thin film transistor having the fourth structure.

Reference numerals:

1-a substrate, 2-a gate,

31-a first active layer structure, 311-a first conductive connection,

3110-first part, 3111-second part,

3112-fifth part, 3113-sixth part,

312-the first oxide semiconductor pattern, 313-the second conductive connection,

32-a second active layer structure, 321-a third conductive connection,

322-second oxide semiconductor pattern, 323-fourth conductive connection portion,

3230-third section, 3231-fourth section,

3232-seventh section, 3233-eighth section,

3234-ninth portion, 4-first lap joint,

5-second strap, 6-gate insulation layer.

Detailed Description

In order to further explain the oxide thin film transistor and the display device provided by the embodiments of the present invention, the following detailed description is made with reference to the accompanying drawings.

Based on the foregoing related art, the inventor of the present invention has found that when the Oxide semiconductor pattern in an Oxide Thin Film Transistor (Oxide Thin Film Transistor, hereinafter referred to as Oxide TFT) is locally degraded, the display panel may have driving bright spots and sand mura defects, which are the main reasons for the defects: when the Oxide semiconductor pattern (as an active layer of an Oxide thin film transistor) is locally degraded, an initial threshold voltage Vth in a characteristic curve of the Oxide TFT is shifted to the left, and an off-state current Ioff of the Oxide TFT is too large, so that when the Oxide TFT is used for driving a pixel to emit light, the pixel is continuously driven to generate a driving bright point and sand mura defects.

The utility model discloses an inventor has found through the research that the Oxide semiconductor figure in the Oxide TFT is when local degradation appears, and the degradation range is very little, only several micron scope, consequently only produces the influence to single Oxide TFT, consequently, the utility model discloses the consideration sets up a plurality of Oxide semiconductor figures that the Oxide TFT includes the series connection, is about to an Oxide TFT and sets up to the son Oxide TFT including a plurality of series connections to when the Oxide semiconductor figure that realizes in a son Oxide TFT takes place the degradation, still can guarantee that the Oxide TFT has good working property.

Referring to fig. 1 and 2, an embodiment of the present invention provides an oxide thin film transistor, including:

a gate electrode 2 disposed on the substrate 1;

at least two active layer structures arranged in sequence along a first direction, the at least two active layer structures including a first active layer structure 31 and a second active layer structure 32, the first active layer structure 31 including: a first conductive connection part 311 and a second conductive connection part 313 which are oppositely arranged, and a first oxide semiconductor pattern 312 which is positioned between the first conductive connection part 311 and the second conductive connection part 313, wherein the first oxide semiconductor pattern 312 is respectively coupled with the first conductive connection part 311 and the second conductive connection part 313; the second active layer structure 32 includes: a third conductive connection part 321 and a fourth conductive connection part 323 which are oppositely disposed, and a second oxide semiconductor pattern 322 between the third conductive connection part 321 and the fourth conductive connection part 323, the second oxide semiconductor pattern 322 being coupled with the third conductive connection part 321 and the fourth conductive connection part 323, respectively; an orthographic projection of the first oxide semiconductor pattern 312 on the substrate 1 and an orthographic projection of the second oxide semiconductor pattern 322 on the substrate 1 are both positioned inside an orthographic projection of the gate electrode 2 on the substrate 1; the second conductive connection portion 313 is coupled to the third conductive connection portion 321.

Specifically, the material of the substrate 1 may be selected according to actual needs, for example, a glass substrate 1 or a flexible substrate 1 made of other materials is selected, and when the oxide thin film transistor is manufactured on the substrate 1, film layers such as a buffer layer and a light shielding layer may be formed on the substrate 1, and then the oxide thin film transistor is continuously manufactured on the side of the substrate 1 on which the buffer layer and the light shielding layer are formed. In manufacturing an oxide thin film transistor, for example, the gate electrode 2 and the at least two active layer structures may be sequentially formed in a direction away from the substrate 1.

The number of the active layer structures may be set according to actual needs, and for example, the at least two active layer structures may be set to include a first active layer structure 31 and a second active layer structure 32; the first active layer structure 31 includes: a first conductive connection portion 311 and a second conductive connection portion 313 oppositely arranged in a direction parallel to the substrate 1, and further including a first oxide semiconductor pattern 312 between the first conductive connection portion 311 and the second conductive connection portion 313, the first oxide semiconductor pattern 312 being coupled to the first conductive connection portion 311 and the second conductive connection portion 313, respectively; the second active layer structure 32 includes: the third and fourth

conductive connection parts

321 and 323, which are oppositely disposed in a direction parallel to the substrate 1, further include a second oxide semiconductor pattern 322 between the third and fourth

conductive connection parts

321 and 323, the second oxide semiconductor pattern 322 being coupled to the third and fourth

conductive connection parts

321 and 323, respectively.

When the at least two active layer structures include the first active layer structure 31 and the second active layer structure 32, the first conductive connection part 311 in the first active layer structure 31 and the fourth conductive connection part 323 in the second active layer structure 32 may be used as two electrodes (e.g., a source electrode and a drain electrode) of the oxide thin film transistor in a one-to-one correspondence.

It is to be noted that the first conductive connection portion 311 and the second conductive connection portion 313 may be formed using a single conductive material, or may be formed by doping opposite ends of the first oxide semiconductor pattern 312; also, the third conductive connection part 321 and the fourth conductive connection part 323 may be formed using a single conductive material, or may be formed by doping opposite ends of the second oxide semiconductor pattern 322.

In the Oxide thin film transistor with the above structure, by disposing the orthographic projection of the first Oxide semiconductor pattern 312 on the substrate 1 and the orthographic projection of the second Oxide semiconductor pattern 322 on the substrate 1 to be both located inside the orthographic projection of the gate electrode 2 on the substrate 1, the first active layer structure 31 and the gate electrode 2 are formed together into a first sub Oxide TFT structure, and the second active layer structure 32 and the gate electrode 2 are formed together into a second sub Oxide TFT structure, so that the Oxide thin film transistor provided by the embodiment of the present invention is formed into a structure including two sub Oxide TFTs connected in series.

When the Oxide thin film transistor works, a driving signal can be applied to the gate 2 of the Oxide thin film transistor, the second conductive connection part 313 and the fourth conductive connection part 323, and both the first sub Oxide TFT and the second sub Oxide TFT included in the Oxide thin film transistor are turned on under the control of the driving signal, so that the whole Oxide thin film transistor is in a turned-on state, and the driving signal is output.

It should be noted that the oxide thin film transistor may include a plurality (more than two) of the active layer structures, and the plurality of the active layer structures may adopt a connection relationship similar to the first active layer structure 31 and the second active layer structure 32, so as to form the plurality of the active layer structures into a serial connection structure in sequence, and the conductive connection portions at the head end and the conductive connection portions at the tail end in the serial connection structure may be used as two electrodes of the oxide thin film transistor in a one-to-one correspondence manner.

According to the specific structure and the working process of the above Oxide thin film transistor, the embodiment of the present invention provides an Oxide thin film transistor, which includes the at least two active layer structures, so that the Oxide thin film transistor can form at least two channel structures connected in series when in operation, and thus when an Oxide semiconductor pattern in one active layer structure of the Oxide thin film transistor deteriorates, the performance of the sub Oxide TFT corresponding to the active layer structure is only affected, that is, the characteristic curve of the sub Oxide TFT moves to the left, and the other sub Oxide TFTs still maintain a normal working state.

In the oxide thin film transistor provided in the above embodiment, when the at least two active layer structures include the first active layer structure 31 and the second active layer structure 32, specific arrangement structures of the first active layer structure 31 and the second active layer structure 32 are various, and several specific structures are given below.

As shown in fig. 1, 3 and 5, in some embodiments, an orthographic projection of the first conductive connection portion 311 on the substrate 1 forms a first overlap region with an orthographic projection of the first oxide semiconductor pattern 312 on the substrate 1; an orthographic projection of the second conductive connecting portion 313 on the substrate 1 and an orthographic projection of the first oxide semiconductor pattern 312 on the substrate 1 form a second overlapping region; an orthographic projection of the third conductive connecting portion 321 on the substrate 1 and an orthographic projection of the second oxide semiconductor pattern 322 on the substrate 1 form a third overlapping region; an orthographic projection of the fourth conductive connecting portion 323 on the substrate 1 forms a fourth overlapping area with an orthographic projection of the second oxide semiconductor pattern 322 on the substrate 1; the second and third overlap regions are located between the first and fourth overlap regions.

Specifically, the coupling between the first conductive connection portion 311 and the first oxide semiconductor pattern 312, and the coupling between the second conductive connection portion 313 and the first oxide semiconductor pattern 312 may be achieved in various ways.

For example, an orthographic projection of the first conductive connection portion 311 on the substrate 1 may be arranged to form a first overlapping region with an orthographic projection of the first oxide semiconductor pattern 312 on the substrate 1, and an orthographic projection of the second conductive connection portion 313 on the substrate 1 may form a second overlapping region with an orthographic projection of the first oxide semiconductor pattern 312 on the substrate 1; when an insulating layer is provided between the conductive connection portion and the oxide semiconductor pattern, a first via hole may be provided in the insulating layer corresponding to the first overlapping region, and a second via hole may be provided in the insulating layer corresponding to the second overlapping region, such that the first conductive connection portion 311 is coupled to the first oxide semiconductor pattern 312 through the first via hole, and the second conductive connection portion 313 is coupled to the first oxide semiconductor pattern through the second via hole; when there is no insulating layer between the conductive connection portion and the oxide semiconductor pattern, the first conductive connection portion 311 and the second conductive connection portion 313 are directly formed on the surface of the first oxide semiconductor pattern 312 facing away from the substrate 1, so that the first conductive connection portion 311 may directly overlap with the first oxide semiconductor pattern in the first overlapping region, and the second conductive connection portion 313 may directly overlap with the first oxide semiconductor pattern 312 in the second overlapping region.

Similarly, when an insulating layer is provided between the conductive connection portion and the oxide semiconductor pattern, a third via may be provided in the insulating layer corresponding to the third overlap region, and a fourth via may be provided in the insulating layer corresponding to the fourth overlap region, such that the third conductive connection portion 321 is coupled to the second oxide semiconductor pattern 322 through the third via, and the fourth conductive connection portion 323 is coupled to the second oxide semiconductor pattern 322 through the fourth via; when there is no insulating layer between the conductive connection portion and the oxide semiconductor pattern, that is, the third conductive connection portion 321 and the fourth conductive connection portion 323 are directly formed on the surface of the second oxide semiconductor pattern 322 facing away from the substrate 1, so that the third conductive connection portion 321 can directly overlap with the second oxide semiconductor pattern in the third overlap region, and the fourth conductive connection portion 323 can directly overlap with the second oxide semiconductor pattern 322 in the fourth overlap region.

In addition, in the above embodiments, the specific distribution positions of the first overlapping region, the second overlapping region, the third overlapping region and the fourth overlapping region may be set according to actual needs, and for example, the second overlapping region and the third overlapping region may be both located between the first overlapping region and the fourth overlapping region, so that the second conductive connection portion 313 and the third conductive connection portion 321 are closer to each other, thereby facilitating the coupling between the third conductive connection portion 321 and the fourth conductive connection portion 323, and further facilitating the reduction of the occupied area of the oxide thin film transistor.

In the oxide thin film transistor provided in the above embodiment, specific coupling manners between the second conductive connection portion 313 and the third conductive connection portion 321 are various, and several specific coupling manners are listed below.

As shown in fig. 1 and 2, in some embodiments, the thin film transistor further includes a first strap 4, the second conductive connection 313 and the third conductive connection 321 are coupled by the first strap 4, and an orthographic projection of the first strap 4 on the substrate 1 does not overlap with an orthographic projection of the first oxide semiconductor pattern 312 on the substrate 1 and does not overlap with an orthographic projection of the second oxide semiconductor pattern 322 on the substrate 1.

Specifically, when the second conductive connection portion 313 and the third conductive connection portion 321 are coupled by the first lap joint portion 4, the specific shape and layout of the first lap joint portion 4 are various, for example: the first direction is an X direction of the coordinate axes, and when the first oxide semiconductor pattern 312 and the second oxide semiconductor pattern 322 are arranged along the X direction, the first landing part 4 may be disposed as a stripe pattern extending along the X direction, and a first end of the stripe pattern along the X direction is coupled to the second conductive connection part 313, and a second end of the stripe pattern along the X direction is coupled to the third conductive connection part 321; in addition, according to actual needs, an orthogonal projection of the first bonding portion 4 on the substrate 1 may be arranged to overlap or not overlap an orthogonal projection of the first oxide semiconductor pattern 312 on the substrate 1; and the orthographic projection of the first bridging portion 4 on the substrate 1 overlaps or does not overlap with the orthographic projection of the second oxide semiconductor pattern 322 on the substrate 1.

In more detail, as shown in fig. 1, the second conductive connection portion 313 and the third conductive connection portion 321 are each a stripe pattern extending along a Y direction in a coordinate axis, and orthogonal projections of the second conductive connection portion 313, the third conductive connection portion 321, and the first bridging portion 4 on the substrate 1 may be collectively formed in an i shape.

As shown in fig. 3 and 4, in some embodiments, the first oxide semiconductor pattern 312 and the second oxide semiconductor pattern 322 may be further disposed to be sequentially arranged along a first direction and staggered along a second direction perpendicular to the first direction.

Illustratively, the first direction is an X direction, the second direction is a Y direction, and when the first oxide semiconductor pattern 312 and the second oxide semiconductor pattern 322 are laid out, the first oxide semiconductor pattern 312 and the second oxide semiconductor pattern 322 may be sequentially arranged along the X direction and shifted along the Y direction perpendicular to the X direction.

In some embodiments, an orthographic projection of the first oxide semiconductor pattern 312 in the second direction may be provided, a fifth overlap region may be formed with an orthographic projection of the second oxide semiconductor pattern 322 in the second direction, the second conductive connection portion 313, the first lap joint portion 4, and the third conductive connection portion 321 may be formed as an integrated straight line structure extending in the second direction, and a size of the fifth overlap region in the first direction may be the same as a width of the straight line structure in the first direction.

Specifically, when the first oxide semiconductor pattern 312 and the second oxide semiconductor pattern 322 are arranged in sequence along a first direction and are staggered along a second direction perpendicular to the first direction, an orthographic projection of the first oxide semiconductor pattern 312 in the second direction may be further provided to form a fifth overlapping region with an orthographic projection of the second oxide semiconductor pattern 322 in the second direction, so that the second conductive connection portion 313, the first bridging portion 4, and the third conductive connection portion 321 may be formed in an integrated straight-line structure extending along the second direction, thereby simplifying the manufacturing process flow to the maximum extent and reducing the layout area of the oxide thin film transistor.

Furthermore, the size of the fifth overlapping area in the first direction may be set to be the same as the width of the first-type structure along the first direction, and this setting mode reduces the occupied area of the integrated first-type structure to the maximum extent while ensuring a larger contact area between the second conductive connection portion 313 and the first oxide semiconductor pattern 312 and a larger contact area between the third conductive connection portion 321 and the second oxide semiconductor pattern 322, thereby achieving effective reduction of the occupied space of the oxide thin film transistor while ensuring the operating performance of the oxide thin film transistor.

As shown in fig. 5 to 7, in some embodiments, the first oxide semiconductor pattern 312 and the second oxide semiconductor pattern 322 may be further provided to be formed as an integrated structure, and the second conductive connection portion 313 is multiplexed as the third conductive connection portion 321.

Specifically, the first oxide semiconductor pattern 312 and the second oxide semiconductor pattern 322 are formed into an integrated structure, and the second conductive connection portion 313 is multiplexed as the third conductive connection portion 321, so that the area of the oxide semiconductor pattern corresponding to the oxide thin film transistor is larger, which is more beneficial to improving the working stability of the oxide thin film transistor, and in addition, when the oxide semiconductor pattern 121 is manufactured, the composition process flow can be effectively simplified, and the occupied space of the oxide thin film transistor is effectively reduced.

In fig. 6, a gate insulating layer 6 is formed between the gate electrode 2 and the oxide semiconductor pattern.

In the oxide thin film transistor provided in the above embodiment, specific structures and layout manners of the first conductive connection portion 311 and the second conductive connection portion 313 are various, and a specific embodiment corresponding to the first conductive connection portion 311 and the second conductive connection portion 313 is given below.

As shown in fig. 1, 3 and 5, in some embodiments, the first conductive connection portion 311 includes a first portion 3110 extending along the second direction, and a second portion 3111 extending from the first portion 3110 along the second direction, an orthogonal projection of the first portion 3110 on the substrate 1 and an orthogonal projection of the first oxide semiconductor pattern 312 on the substrate 1 form the first overlap region, and an orthogonal projection of the second portion 3111 on the substrate 1 and an orthogonal projection of the first oxide semiconductor pattern 312 on the substrate 1 do not overlap.

Specifically, it may be provided that the first conductive connection portion 311 includes a first portion 3110 and a second portion 3111, the first portion 3110 extends in the second direction, an orthographic projection of the first portion 3110 on the substrate 1 forms the first overlap region with an orthographic projection of the first oxide semiconductor pattern 312 on the substrate 1, the second portion 3111 is a structure extending from the first portion 3110 in the second direction, an orthographic projection of the second portion 3111 on the substrate 1 does not overlap with the first oxide semiconductor structure, and the first portion 3110 and the second portion 3111 are formed as an integrated strip-shaped structure extending in the second direction.

Further, the width of the first overlapping area along the first direction may be the same as the width of the integrated stripe structure, but is not limited thereto.

When the first conductive connection portion 311 is formed in the above structure, the first conductive connection portion 311 may serve as an input electrode (e.g., a drain electrode) of the oxide thin film transistor, which may further facilitate the coupling of the oxide thin film transistor with an external terminal.

In some embodiments, the fourth conductive connection part 323 includes a third portion 3230 and a fourth portion 3231, the third portion 3230 extends in a second direction perpendicular to the first direction, and an orthogonal projection of the third portion 3230 on the substrate 1 overlaps with an orthogonal projection of the second oxide semiconductor pattern 322 on the substrate 1, forming the fourth overlapping region; the fourth portion 3231 extends in the first direction, an orthogonal projection of the fourth portion 3231 on the substrate 1 does not overlap an orthogonal projection of the second oxide semiconductor pattern 322 on the substrate 1, and the fourth portion 3231 is coupled to a first end of the third portion 3230, an orthogonal projection of the first end on the substrate 1 does not overlap an orthogonal projection of the second oxide semiconductor pattern 322 on the substrate 1.

Specifically, the fourth conductive connection portion 323 may include a third portion 3230 and a fourth portion 3231, the third portion 3230 extends along the second direction, the third portion 3230 may include a first sub-portion and a second sub-portion, an orthographic projection of the first sub-portion on the substrate 1 and an orthographic projection of the second oxide semiconductor pattern 322 on the substrate 1 form the fourth overlap region, an orthographic projection of the second sub-portion on the substrate 1 and an orthographic projection of the second oxide semiconductor pattern 322 on the substrate 1 do not overlap, and the second sub-portion may be a structure that extends out from the first sub-portion along the second direction.

The fourth portion 3231 extends along the first direction, an orthogonal projection of the fourth portion 3231 on the substrate 1 does not overlap an orthogonal projection of the second oxide semiconductor pattern 322 on the substrate 1, and the fourth portion 3231 and the third portion 3230 have various coupling manners, for example, the fourth portion 3231 is coupled to a first end of the third portion 3230, and an orthogonal projection of the first end on the substrate 1 does not overlap an orthogonal projection of the second oxide semiconductor pattern 322 on the substrate 1, and in such a coupling manner, the fourth portion 3231 is formed into an L-shaped pattern or a T-shaped pattern.

Further, the fourth overlapping area may also have a width along the first direction, which is the same as the width of the third portion 3230, but is not limited thereto.

When the fourth conductive connection portion 323 is configured as described above, the third portion 3230 and the fourth portion 3231 may be formed as an integral structure, and the fourth conductive connection portion 323 may serve as an output electrode (e.g., a source electrode) of the oxide thin film transistor, so that when the thin film transistor is used as a driving transistor in a pixel driving circuit, the coupling between the output electrode of the driving transistor and a corresponding light emitting element is facilitated.

As shown in fig. 8 and 9, in some embodiments, an orthographic projection of the first conductive connection portion 311 on the substrate 1 may be further provided, forming a first overlap region with an orthographic projection of the first oxide semiconductor pattern 312 on the substrate 1; an orthographic projection of the second conductive connecting portion 313 on the substrate 1 and an orthographic projection of the first oxide semiconductor pattern 312 on the substrate 1 form a second overlapping region; an orthographic projection of the third conductive connecting portion 321 on the substrate 1 and an orthographic projection of the second oxide semiconductor pattern 322 on the substrate 1 form a third overlapping region; an orthographic projection of the fourth conductive connecting portion 323 on the substrate 1 forms a fourth overlapping area with an orthographic projection of the second oxide semiconductor pattern 322 on the substrate 1; in a second direction perpendicular to the first direction, the second overlap region and the third overlap region are located at a first side of the first oxide semiconductor pattern 312, and the first overlap region and the fourth overlap region are located at a second side of the second oxide semiconductor pattern 322, the first side and the second side being opposite along the second direction.

Specifically, when an insulating layer is provided between the conductive connection portion and the oxide semiconductor pattern, a first via may be provided in the insulating layer corresponding to the first overlap region, and a second via may be provided in the insulating layer corresponding to the second overlap region, such that the first conductive connection portion 311 is coupled to the first oxide semiconductor pattern 312 through the first via, and the second conductive connection portion 313 is coupled to the first oxide semiconductor pattern 312 through the second via; when there is no insulating layer between the conductive connection portion and the oxide semiconductor pattern, the first conductive connection portion 311 and the second conductive connection portion 313 are directly formed on the surface of the first oxide semiconductor pattern 312 facing away from the substrate 1, so that the first conductive connection portion 311 may directly overlap with the first oxide semiconductor pattern in the first overlapping region, and the second conductive connection portion 313 may directly overlap with the first oxide semiconductor pattern 312 in the second overlapping region.

In addition, in the above-described embodiment, the specific distribution positions of the first overlap region, the second overlap region, the third overlap region and the fourth overlap region may be set according to actual needs, and may be set in the second direction, for example, the second overlap region and the third overlap region are located on the first side of the first oxide semiconductor pattern 312, the first overlap region and the fourth overlap region are located on the second side of the second oxide semiconductor pattern 322, and the first side and the second side are opposite to each other along the second direction; this structure makes the channel region generated by the first oxide semiconductor pattern 312 and the channel region generated by the second oxide semiconductor pattern 322 independent from each other in operation, thereby preventing interference between adjacent channel regions during operation; moreover, the second conductive connection portion 313 and the third conductive connection portion 321 which are coupled to each other are closer to each other due to the structure, which not only facilitates the coupling between the second conductive connection portion 313 and the third conductive connection portion 321, but also is more beneficial to reducing the occupied area of the oxide thin film transistor.

As shown in fig. 8 and 9, the thin film transistor further includes a second strap 5, the second conductive connection portion 313 and the third conductive connection portion 321 are coupled by the second strap 5, an orthographic projection of the second strap 5 on the substrate 1 does not overlap with an orthographic projection of the first oxide semiconductor pattern 312 on the substrate 1, and does not overlap with an orthographic projection of the second oxide semiconductor pattern 322 on the substrate 1; the second conductive connection portion 313, the second lap portion 5, and the third conductive connection portion 321 are formed in a straight structure along the first direction.

Specifically, when the second conductive connection portion 313 and the third conductive connection portion 321 are coupled by the second strap, the second strap 5 has various specific shapes and layouts, and it is exemplified that: the first direction is an X direction of coordinate axes, and when the first oxide semiconductor patterns 312 and the second oxide semiconductor patterns 322 are arranged in the X direction, the second strap 5 may be provided in a stripe pattern extending in the X direction, and the second conductive connection portion 313 and the third conductive connection portion 321 may be provided in a stripe pattern extending in the X direction, such that a first end of the second strap 5 in the X direction may be coupled to the second conductive connection portion 313, and a second end of the second strap 5 in the X direction may be coupled to the third conductive connection portion 321, such that the second conductive connection portion 313, the second strap 5, and the third conductive connection portion 321 may be formed in a straight line structure in the X direction.

In addition, according to actual needs, an orthogonal projection of the second bonding portion 5 on the substrate 1 may be arranged to overlap or not overlap an orthogonal projection of the first oxide semiconductor pattern 312 on the substrate 1; and an orthographic projection of the second lap joint part 5 on the substrate 1 overlaps or does not overlap with an orthographic projection of the second oxide semiconductor pattern 322 on the substrate 1.

In addition, the linear structure formed by the second conductive connection portion 313, the second overlapping portion 5 and the third conductive connection portion 321 may be formed as an integrated structure, so that the linear structure may be formed through a one-step patterning process, thereby effectively simplifying the manufacturing process of the oxide thin film transistor and saving the manufacturing cost of the oxide thin film transistor.

As shown in fig. 8, further, it may be further provided that the first conductive connection portion 311 includes a fifth portion 3112 and a sixth portion 3113 coupled to each other, the fifth portion 3112 extends along the first direction, and an orthographic projection of the fifth portion 3112 on the substrate 1 and an orthographic projection of the first oxide semiconductor pattern 312 on the substrate 1 form the first overlap region; the sixth portion 3113 extends in the second direction, and an orthogonal projection of the sixth portion 3113 on the substrate 1 does not overlap an orthogonal projection of the first oxide semiconductor pattern 312 on the substrate 1.

Specifically, the first conductive connection portion 311 may include a fifth portion 3112 and a sixth portion 3113 coupled to each other, wherein the fifth portion 3112 may extend along the first direction, and an orthographic projection of the fifth portion 3112 on the substrate 1 may overlap with an orthographic projection of the first oxide semiconductor pattern 312 on the substrate 1, forming the first overlapping area; the sixth portion 3113 may extend along the second direction, an orthographic projection of the sixth portion 3113 on the substrate 1 may not overlap an orthographic projection of the first oxide semiconductor pattern 312 on the substrate 1, the sixth portion 3113 may be coupled to a first end of the fifth portion 3112, the orthographic projection of the first end on the substrate 1 may not be coupled to the first oxide semiconductor pattern 312, and the first conductive connection portion 311 formed after the fifth portion 3112 is coupled to the sixth portion 3113 may be L-shaped or T-shaped.

In addition, it may be further provided that the width of the first overlapping area is the same as the width of the fifth section 3112 in the second direction, but is not limited thereto.

Further, the fourth conductive connection part 323 includes a seventh portion 3232, an eighth portion 3233, and a ninth portion 3234; wherein the seventh portion 3232 extends along the first direction, and an orthographic projection of the seventh portion 3232 on the substrate 1 and an orthographic projection of the second oxide semiconductor pattern 322 on the substrate 1 form the fourth overlapping region; the ninth portion 3234 extends in the first direction, and an orthogonal projection of the ninth portion 3234 on the substrate 1 does not overlap with an orthogonal projection of the second oxide semiconductor pattern 322 on the substrate 1; the eighth portion 3233 extends along the second direction, an orthogonal projection of the eighth portion 3233 on the substrate 1 is located between an orthogonal projection of the seventh portion 3232 on the substrate 1 and an orthogonal projection of the ninth portion 3234 on the substrate 1, and does not overlap with an orthogonal projection of the second oxide semiconductor pattern 322 on the substrate 1, and the seventh portion 3232 is coupled to the ninth portion 3234 through the eighth portion 3233.

Specifically, the fourth conductive connection portion 323 may be provided to include a seventh portion 3232, an eighth portion 3233, and a ninth portion 3234, the seventh portion 3232 extending along the first direction, an orthogonal projection of the seventh portion 3232 on the substrate 1 and an orthogonal projection of the second oxide semiconductor pattern 322 on the substrate 1 forming the fourth overlap region, and further, an orthogonal projection of the seventh portion 3232 on the substrate 1 may be provided inside an orthogonal projection of the second oxide semiconductor pattern 322 on the substrate 1.

Along the second direction, the ninth portion 3234 may be disposed opposite to the seventh portion 3232, the ninth portion 3234 extends along the first direction, and an orthogonal projection of the ninth portion 3234 on the substrate 1 does not overlap an orthogonal projection of the second oxide semiconductor pattern 322 on the substrate 1.

The eighth portion 3233 extends along the second direction, an orthogonal projection of the eighth portion 3233 on the substrate 1 is located between an orthogonal projection of the seventh portion 3232 on the substrate 1 and an orthogonal projection of the ninth portion 3234 on the substrate 1, one end of the eighth portion 3233 near the seventh portion 3232 is coupled to the seventh portion 3232, and one end of the eighth portion 3233 near the ninth portion 3234 is coupled to the ninth portion 3234, such that the fourth conductive connection 323 collectively formed by the seventh portion 3232, the eighth portion 3233 and the ninth portion 3234 has an i-shape.

It is further noted that, according to actual requirements, the entire projection of the eighth portion 3233 on the substrate 1 may or may not overlap with the orthogonal projection of the second oxide semiconductor pattern 322 on the substrate 1.

Further, the ninth portion 3234 may have a width greater than that of the seventh portion 3232 along the second direction, so as to ensure better connection performance of the fourth conductive connection portion 323 with the outside.

When the fourth conductive connection part 323 is configured as described above, the seventh part 3232, the eighth part 3233, and the ninth part 3234 may be formed as an integral structure, and the fourth conductive connection part 323 may serve as an output electrode (e.g., a source) of the oxide thin film transistor, so that when the thin film transistor is used as a driving transistor in a pixel driving circuit, coupling between the output electrode of the driving transistor and a corresponding light emitting element is facilitated.

In the oxide thin film transistor provided in the above embodiments, the oxide semiconductor patterns included in each of the active layer structures may be disposed in various manners, and in some embodiments, the oxide semiconductor patterns in each of the active layer structures may be disposed in the same layer and the same material, and specifically, the first oxide semiconductor pattern 312 and the second oxide semiconductor pattern 322 may be disposed in the same layer and the same material.

When the oxide semiconductor patterns in the active layer structures are arranged on the same layer and the same material, the step of manufacturing the oxide semiconductor patterns in the active layer structures specifically comprises the following steps: firstly, an oxide semiconductor film is made of an oxide semiconductor material, and a photoresist covering the oxide semiconductor film is formed, then, the photoresist is exposed by using a mask plate comprising a light transmitting area and a light shading area to form a photoresist reserving area and a photoresist removing area, the photoresist retention region corresponds to a region where the oxide semiconductor pattern in each of the active structures is located, the photoresist removing region corresponds to other regions except the region where the oxide semiconductor pattern in each active structure is located, the photoresist in the photoresist removing region is removed by using a developing solution to expose the oxide semiconductor film in the photoresist removing region, and then removing the exposed oxide semiconductor film by adopting an etching process, and finally stripping the residual photoresist to form an oxide semiconductor pattern in each active layer structure.

The oxide semiconductor patterns in the active layer structures are arranged on the same layer and the same material, so that the oxide semiconductor patterns in the active layer structures can be formed simultaneously through a one-step composition process, the manufacturing process flow of the oxide thin film transistor provided by the embodiment is effectively simplified, and the production cost is reduced.

The "same layer" refers to a layer structure formed by fabricating a film layer for forming a specific pattern by using the same film formation process and then performing a patterning process using the same mask plate. Depending on the specific pattern, the single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and the specific patterns may be at different heights or have different thicknesses.

When the oxide semiconductor patterns in each of the active layer structures are disposed in the same layer as the material, the step of fabricating the oxide semiconductor patterns in each of the active layer structures may include: manufacturing an oxide semiconductor film layer for forming each oxide semiconductor pattern by adopting the same film forming process; and then patterning the oxide semiconductor film layer through a one-step patterning process, and simultaneously forming an oxide semiconductor pattern in each active layer structure.

In the oxide thin film transistor provided in the above embodiment, specific arrangement manners of the first conductive connection portion 311, the second conductive connection portion 313, the third conductive connection portion 321, and the fourth conductive connection portion 323 are various, and for example, the first conductive connection portion 311, the second conductive connection portion 313, the third conductive connection portion 321, and the fourth conductive connection portion 323 are arranged in the same layer and by the same material.

Specifically, the first conductive connection portion 311, the second conductive connection portion 313, the third conductive connection portion 321, and the fourth conductive connection portion 323 are disposed on the same layer and the same material, so that the first conductive connection portion 311, the second conductive connection portion 313, the third conductive connection portion 321, and the fourth conductive connection portion 323 can be formed simultaneously in the same patterning process, thereby effectively simplifying the process flow of the oxide thin film transistor.

The embodiment of the utility model provides a display device is still provided, including the oxide thin film transistor that above-mentioned embodiment provided.

Because the oxide thin film transistor that the above-mentioned embodiment provided not only has higher stability, but also has stronger driving force, when using the utility model discloses when the pixel among the oxide thin film transistor drive display panel that the embodiment provided gives out light, avoided display panel to produce and drive bright spot and sand grain mura bad; therefore, the embodiment of the present invention provides a display device, when including the above-mentioned oxide thin film transistor, can avoid producing drive bright spot and sand mura harmfully equally.

In addition, because the oxide thin film transistor that above-mentioned embodiment provided has advantages such as the preparation process flow is simple, the cost of manufacture is lower, whole area occupied is less, consequently, the embodiment of the utility model provides a display device has advantages such as the preparation process flow is simple, the cost of manufacture is lower equally when including above-mentioned oxide thin film transistor, and is favorable to realizing beneficial effect such as high resolution.

The display device may be: any product or component with a display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer and the like.

The driving method for driving the oxide thin film transistor provided by the above embodiment includes:

a driving signal is applied to the gate electrode 2 of the oxide thin film transistor, the second conductive connection part 313 included in the first active layer structure 31, and the fourth conductive connection part 323 included in the second active layer structure 32 to turn on the oxide thin film transistor.

Specifically, when the Oxide thin film transistor operates, a driving signal may be applied to the gate electrode 2 of the Oxide thin film transistor, the second conductive connection portion 313 included in the first active layer structure 31, and the fourth conductive connection portion 323 included in the second active layer structure 32, and each sub Oxide TFT included in the Oxide thin film transistor is turned on under the control of the driving signal, so that the entire Oxide thin film transistor is in an on state, and the driving signal is output.

When the Oxide thin film transistor is driven by adopting the driving method, the Oxide thin film transistor comprises the at least two active layer structures, so that at least two serially connected channel structures can be formed when the Oxide thin film transistor works, and thus when an Oxide semiconductor pattern in one active layer structure in the Oxide thin film transistor is deteriorated, the performance of the sub Oxide TFT corresponding to the active layer structure is only influenced, namely the characteristic curve of the sub Oxide TFT is shifted to the left, and other sub Oxide TFTs still keep normal working states.

In more detail, when the Oxide semiconductor pattern of one sub Oxide TFT is deteriorated, both the on-state current Ion and the off-state current Ioff of the sub Oxide TFT are increased, so that under the condition that each sub Oxide TFT is controlled to be in a conducting state and the whole Oxide thin film transistor is conducted, the on-state current Ion of the whole Oxide thin film transistor is increased under the influence of the on-state current Ion of the sub Oxide TFT, and the charging capability of the Oxide thin film transistor is effectively improved; on the other hand, when the Oxide thin film transistor is turned off, each of the sub Oxide TFTs is in an off state, and therefore, even if the off-state current Ioff of the sub Oxide TFT increases, the off-state current Ioff of the entire Oxide thin film transistor is not affected by the increased off-state current Ioff, and the off-state current Ioff of the entire Oxide thin film transistor can be maintained at a low level. Therefore, when the oxide thin film transistor is driven by the driving method, the oxide thin film transistor not only has higher stability, but also has stronger driving capability, and when the oxide thin film transistor is used for driving pixels in the display panel to emit light, the display panel is prevented from generating driving bright spots and sand mura.

It should be noted that, in the present specification, all the embodiments are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the method embodiments, since they are substantially similar to the product embodiments, they are described simply, and reference may be made to the partial description of the product embodiments for relevant points.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which the invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected," "coupled," or "connected," and the like, are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and all should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. An oxide thin film transistor, comprising:

a gate electrode disposed on the substrate;

2. The oxide thin film transistor according to claim 1, wherein an orthographic projection of the first conductive connecting portion on the substrate forms a first overlap region with an orthographic projection of the first oxide semiconductor pattern on the substrate;

3. The oxide thin film transistor according to claim 2, further comprising a first bridging portion, the second conductive connection portion and the third conductive connection portion being coupled by the first bridging portion, an orthogonal projection of the first bridging portion on the substrate being non-overlapping with an orthogonal projection of the first oxide semiconductor pattern on the substrate and being non-overlapping with an orthogonal projection of the second oxide semiconductor pattern on the substrate.

4. The oxide thin film transistor according to claim 3, wherein the first oxide semiconductor pattern and the second oxide semiconductor pattern are arranged in order in a first direction and are staggered in a second direction perpendicular to the first direction.

5. The oxide thin film transistor according to claim 4, wherein an orthographic projection of the first oxide semiconductor pattern in the second direction forms a fifth overlapping region with an orthographic projection of the second oxide semiconductor pattern in the second direction, the second conductive connection portion, the first lap portion, and the third conductive connection portion are formed as an integrated in-line structure extending in the second direction, and a size of the fifth overlapping region in the first direction is the same as a width of the in-line structure in the first direction.

6. The oxide thin film transistor according to claim 2, wherein the first oxide semiconductor pattern and the second oxide semiconductor pattern are formed as an integrated structure, and the second conductive connection portion is multiplexed as the third conductive connection portion.

7. The oxide thin film transistor according to any one of claims 3 to 6, wherein the first conductive connection portion includes a first portion extending in a second direction perpendicular to the first direction, and a second portion extending from the first portion in the second direction, an orthogonal projection of the first portion on the substrate and an orthogonal projection of the first oxide semiconductor pattern on the substrate form the first overlap region, and an orthogonal projection of the second portion on the substrate and an orthogonal projection of the first oxide semiconductor pattern on the substrate do not overlap.

8. The oxide thin film transistor according to any one of claims 3 to 6, wherein the fourth conductive connection portion comprises a third portion and a fourth portion, the third portion extends in a second direction perpendicular to the first direction, and an orthographic projection of the third portion on the substrate overlaps with an orthographic projection of the second oxide semiconductor pattern on the substrate to form the fourth overlapping area;

9. The oxide thin film transistor according to claim 1,

the orthographic projection of the first conductive connecting part on the substrate and the orthographic projection of the first oxide semiconductor pattern on the substrate form a first overlapping area;

10. The oxide thin film transistor according to claim 9,

the thin film transistor further includes a second strap, the second conductive connection portion and the third conductive connection portion being coupled through the second strap, an orthographic projection of the second strap on the substrate being non-overlapping with an orthographic projection of the first oxide semiconductor pattern on the substrate and non-overlapping with an orthographic projection of the second oxide semiconductor pattern on the substrate;

11. The oxide thin film transistor according to claim 9 or 10, wherein the first conductive connection portion includes a fifth portion and a sixth portion coupled to each other, the fifth portion extending in the first direction, an orthogonal projection of the fifth portion on the substrate and an orthogonal projection of the first oxide semiconductor pattern on the substrate forming the first overlap region; the sixth portion extends in the second direction, and an orthogonal projection of the sixth portion on the substrate does not overlap with an orthogonal projection of the first oxide semiconductor pattern on the substrate.

12. The oxide thin film transistor according to claim 9 or 10, wherein the fourth conductive connection portion includes a seventh portion, an eighth portion, and a ninth portion; wherein the content of the first and second substances,

13. The oxide thin film transistor according to claim 1, wherein the first oxide semiconductor pattern and the second oxide semiconductor pattern are provided in the same layer of the same material.

14. A display device comprising the oxide thin film transistor according to any one of claims 1 to 13.