CN111627962A - Display panel, display device and manufacturing method of display panel - Google Patents
Display panel, display device and manufacturing method of display panel Download PDFInfo
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- CN111627962A CN111627962A CN202010423212.6A CN202010423212A CN111627962A CN 111627962 A CN111627962 A CN 111627962A CN 202010423212 A CN202010423212 A CN 202010423212A CN 111627962 A CN111627962 A CN 111627962A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
Abstract
The application provides a display panel, a display device and a manufacturing method of the display panel, wherein the display panel is provided with a display area and comprises the following steps: the light-emitting diode comprises a substrate, a light-emitting layer, a first circuit layer and a second circuit layer, wherein the light-emitting layer is arranged on the substrate, the first circuit layer is arranged on one side, close to the substrate, of the light-emitting layer, the first circuit layer comprises a first thin film transistor, the first thin film transistor is electrically connected with the light-emitting layer, the second circuit layer is arranged on one side, close to or far away from the substrate, of the first circuit layer, the second circuit layer comprises a second thin film transistor, the second thin film transistor is electrically connected with the first thin film transistor so as to control the light-emitting condition of the light-emitting layer, and the first thin film transistor and the second thin film transistor; the scheme reduces the size of the frame around the display panel and improves the screen occupation ratio of the display panel.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a display device, a display panel, and a method for manufacturing the display panel.
Background
The GOA (Gate Driver on Array, Array substrate line Driver) technology directly manufactures the Gate driving circuit on the Array substrate to replace the external silicon wafer, and has the characteristics of saving materials and simplifying process.
However, in the conventional OLED (Organic Light-Emitting display) display panel, the GOA circuit is generally located in the peripheral area of the display area, and the GOA circuit and the pixel driving circuit of the display area are disposed on the same layer, which is limited by the electrical stability and uniformity of the GOA circuit, and it is difficult to reduce the size of the GOA circuit to reduce the size of the peripheral area of the display area, resulting in a low screen ratio of the OLED display panel.
Therefore, it is necessary to provide a display panel and a display device that can improve the screen ratio of the OLED display panel.
Disclosure of Invention
The application aims to provide a display panel, a display device and a manufacturing method of the display panel, and the second thin film transistor is arranged in a display area and arranged on a different layer from the first thin film transistor layer, so that the problem that the screen occupation ratio of the OLED display panel is low due to the fact that the existing GOA circuit is arranged in a non-display area to occupy more frame areas is solved.
The embodiment of the present application provides a display panel, display panel has the display area, display panel includes:
a substrate;
a light emitting layer disposed on the substrate;
the first circuit layer is arranged on one side, close to the substrate, of the light emitting layer and comprises a first thin film transistor, the first thin film transistor is arranged in the display area, and the first thin film transistor is electrically connected with the light emitting layer;
the second circuit layer is arranged on one side, close to or far away from the substrate, of the first circuit layer and comprises a second thin film transistor, the second thin film transistor is arranged in the display area and is electrically connected with the first thin film transistor so as to control the light emitting condition of the light emitting layer.
In one embodiment, the display panel further includes:
an insulating layer disposed between the first circuit layer and the second circuit layer;
the via hole is formed in the insulating layer, and the second thin film transistor is electrically connected with the first thin film transistor through the via hole.
In one embodiment, the light-emitting layer includes a plurality of light-emitting portions that emit light to a side away from the substrate, and a black matrix provided between the plurality of light-emitting portions, and the first thin film transistor and/or the second thin film transistor are provided opposite to the light-emitting portions and/or the black matrix.
In one embodiment, the plurality of light emitting portions further emit light to a side close to the substrate, and the plurality of first thin film transistors and the plurality of second thin film transistors are each disposed opposite to the black matrix.
In one embodiment, a projection of the second thin film transistor on the first circuit layer overlaps the first thin film transistor.
In an embodiment, the display panel includes a bending region and a non-bending region, the bending region is used for bending the display panel, and the second thin film transistor is disposed in the non-bending region.
In one embodiment, the first thin film transistor includes a first metal layer and a second metal layer, the second metal layer includes a first metal portion and a second metal portion, the second thin film transistor includes a third metal layer and a fourth metal layer, the fourth metal layer includes a third metal portion and a fourth metal portion;
the data line is electrically connected with the third metal part, the scanning line is electrically connected with the third metal layer, the fourth metal part is electrically connected with the first metal layer, the first metal part is loaded with working voltage, the second metal part is electrically connected with the light-emitting layer, and the data line and the scanning line control the light-emitting condition of the light-emitting layer by controlling the fourth metal part.
In an embodiment, the first thin film transistor and/or the second thin film transistor is one of a bottom gate thin film transistor, a top gate thin film transistor, or a dual gate thin film transistor.
An embodiment of the present application further provides a manufacturing method of a display panel, for manufacturing the display panel as described in any one of the above, where the display panel has a display area, and the method includes:
providing a substrate;
forming a circuit layer on the substrate, wherein the circuit layer comprises a first circuit layer and a second circuit layer, the first circuit layer comprises a first thin film transistor, the second circuit layer is arranged on one side, close to or far away from the substrate, of the first circuit layer, the second circuit layer comprises a second thin film transistor, the first thin film transistor and the second thin film transistor are both arranged in the display area, and the second thin film transistor is electrically connected with the first thin film transistor;
and a light emitting layer is formed on the circuit layer, the first thin film transistor is electrically connected with the light emitting layer, and the second thin film transistor controls the light emitting condition of the light emitting layer by controlling the first thin film transistor.
An embodiment of the present application further provides a display device, which includes the display panel as described in any one of the above.
The application provides a display panel, a display device and a manufacturing method of the display panel, the display panel comprises a substrate, a luminous layer, a first circuit layer and a second circuit layer, the first circuit layer comprises a first thin film transistor, the second circuit layer comprises a second thin film transistor, the second thin film transistor is arranged in a display area and is arranged on a different layer with the first thin film transistor layer, the second thin film transistor does not occupy a non-display area of the display panel, the size of the non-display area around the display panel is reduced, and the screen occupation ratio of the display panel is improved.
Drawings
The present application is further illustrated by the following figures. It should be noted that the drawings in the following description are only for illustrating some embodiments of the present application, and that other drawings may be obtained by those skilled in the art without inventive effort.
Fig. 1 is a schematic cross-sectional view of a first display panel according to an embodiment of the present disclosure.
Fig. 2 is a schematic cross-sectional view of a second display panel according to an embodiment of the present disclosure.
Fig. 3 is a schematic cross-sectional view of a third display panel according to an embodiment of the present disclosure.
Fig. 4 is a schematic cross-sectional view of a fourth display panel provided in the embodiment of the present application.
Fig. 5 is a schematic cross-sectional view of a fifth display panel according to an embodiment of the present disclosure.
Fig. 6 is a schematic cross-sectional view of a sixth display panel according to an embodiment of the present application.
Fig. 7 is a schematic cross-sectional view of a seventh display panel according to an embodiment of the present disclosure.
Fig. 8 is a schematic cross-sectional view of an eighth display panel according to an embodiment of the present application.
Fig. 9 is a schematic top view of a display panel according to an embodiment of the present disclosure.
Fig. 10 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present application.
Detailed Description
The technical solution in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "upper", "lower", "around", "one side", and the like indicate an orientation or positional relationship based on the orientation or positional relationship shown in the drawings, for example, "upper" simply means that a surface is above an object, and specifically refers to directly above, obliquely above, and an upper surface, as long as it is above the object level; "opposite" refers to two positions relative to each other, which are indicative of objects that can be embodied in the figures, and the two positions can be in direct/indirect contact with the objects, and the above orientation or positional relationship is merely for convenience of describing the present application and simplifying the description, and does not indicate or imply that the referred device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.
It should be noted that the drawings only provide the structures and steps which are relatively close to the present application, and some details which are not related to the present application are omitted, so as to simplify the drawings and make the application point clear, but not to show that the actual device and/or method is the same as the drawings and not to limit the actual device and method.
The present application provides a display device including, but not limited to, a display panel in the following embodiments.
In one embodiment, as shown in fig. 1 to 9, the display panel 00 has a display area 01 and a non-display area 02 located around the display area 01, and the display panel 00 includes: the light emitting diode comprises a substrate 10, a light emitting layer 20, a first circuit layer 30 and a second circuit layer 40, wherein the first circuit layer 30 is arranged on one side of the light emitting layer 20 close to the substrate 10, the first circuit layer 30 comprises a first thin film transistor 301, the first thin film transistor 301 is electrically connected with the light emitting layer 20, the second circuit layer 40 is arranged on one side of the first circuit layer 30 close to or far away from the substrate 10, the second circuit layer 40 comprises a second thin film transistor 401, and the second thin film transistor 401 is electrically connected with the first thin film transistor 301 to control the light emitting condition of the light emitting layer 20.
In particular, the first thin film transistor 301 and the second thin film transistor 401 are both disposed in the display area 01, so as to avoid occupying an area of the non-display area 02, which results in an excessively large non-display area 02 to reduce a screen occupation ratio.
The substrate 10 may be a glass substrate or a metal substrate.
In an embodiment, a flexible substrate and a buffer layer may be sequentially included between the substrate 10 and the first circuit layer 30 from bottom to top, a constituent material of the flexible substrate may be one of polyimide, polystyrene, or polydimethylsiloxane, a constituent material of the buffer layer may include at least one of silicon nitride, silicon oxide, titanium oxide, and aluminum oxide, and further, the buffer layer may also be a composite layer formed by the above inorganic materials, respectively.
In one embodiment, in the display region 01, the light emitting layer 20 includes a plurality of light emitting portions 201 and a black matrix 202 disposed between the plurality of light emitting portions 201, the plurality of light emitting portions 201 emit light to a side away from the substrate 10, and the first thin film transistor 301 and/or the second thin film transistor 401 are disposed opposite to the light emitting portions 201 and/or the black matrix 202.
The light emitting portions 201 may be OLED devices for emitting light in the display panel 00 or other devices for emitting light, and it can be understood that each light emitting portion 201 can emit light of a specific color, which corresponds to a sub-pixel, and a plurality of light emitting portions 201 or a plurality of sub-pixels may constitute a pixel unit; it is understood that when the light emitting parts 201 emit light to a side away from the substrate 10, on one hand, metal traces such as scan lines and data lines in the first thin film transistor 301, the second thin film transistor 401 and the first circuit layer 30 and the second circuit layer 40 can be disposed in the display area 01 so as not to occupy the non-display area 02 to reduce the screen occupation ratio of the display panel 00, and further, the first thin film transistor 301 and the second thin film transistor 401 are disposed in different layers so as to reduce the complexity of the circuit structure in the same layer and improve the reliability of signal transmission in the circuit, and on the other hand, the first thin film transistor 301, the second thin film transistor 401 and the first circuit layer 30 and the second circuit layer 40 are disposed in different layers such as to reduce the complexity of the circuit structure in the same layer and improve the reliability of signal transmission in the circuit The metal traces such as the trace lines and the data lines may be intensively disposed in the non-display region 02, so that when the light emitted from the light emitting part 201 is reflected to the first circuit layer 30 and the second circuit layer 40, the light may be reflected again for multiple times and then emitted out of the display panel 00, and the light utilization rate of the light emitting part 201 may be improved.
In one embodiment, the plurality of light emitting portions 201 also emit light to a side close to the substrate 10, and the plurality of first thin film transistors 301 and the plurality of second thin film transistors 401 are disposed opposite to the black matrix 202.
It should be noted that, when the plurality of light emitting parts 201 emit light toward the side close to the substrate 10, the light emitted from the light emitting parts 201 passes through the first circuit layer 30 and the second circuit layer 40 and then is emitted from the substrate 10, and therefore, the light transmittance of the region of the first circuit layer 30 and the second circuit layer 40 opposite to the light emitting parts 201 affects the aperture ratio of the sub-pixels. It is understood that, by disposing the plurality of first thin film transistors 301 and the plurality of second thin film transistors 401, and the metal traces such as the scan lines and the data lines in the first circuit layer 30 and the second circuit layer 40 in the display area 01, further, by disposing the metal traces opposite to the black matrix 202, the aperture ratio of the sub-pixels and the light utilization ratio of the light emitting portion 201 can be improved.
In one embodiment, as shown in fig. 2, a projection of the second thin film transistor 401 on the first circuit layer 30 may overlap with the first thin film transistor 301. It can be understood that, since the second thin film transistor 401 is electrically connected to the first thin film transistor 301, the distance between the two can be reduced, the reliability of the electrical connection between the two can be improved, the area can be saved in the horizontal direction, and the aperture ratio of the sub-pixel can be improved to the greatest extent when other conditions are the same.
In one embodiment, as shown in fig. 3, the display panel 00 further includes an insulating layer and a via hole, the insulating layer includes a first insulating layer 501, the first insulating layer 501 is disposed between the first circuit layer 30 and the second circuit layer 40, the via hole includes a first via hole 601, the first via hole 601 is disposed on the first insulating layer 501, and the second thin film transistor 401 is electrically connected to the first thin film transistor 301 through the first via hole 601.
Further, the insulating layer further includes a second insulating layer 502, the second insulating layer 502 is disposed between the second circuit layer 40 and the light emitting layer 20, the via hole further includes a second via hole 602, the second via hole 602 is disposed on the first insulating layer 501, the second circuit layer 40 and the second insulating layer 502, and the light emitting layer 20 is electrically connected to the first thin film transistor 301 through the second via hole 602. It is understood that, in order to increase the aperture ratio of the sub-pixel, the second via 602 may be disposed opposite to the black matrix 202, but the first thin film transistor 301 is electrically connected to the light emitting portion 201 through the second via 602 to control the light emitting condition of the light emitting layer 20.
In some embodiments, as shown in fig. 1-6, the second thin film transistor 401 may be disposed over the first thin film transistor 301. The first thin film transistor 301 and/or the second thin film transistor 401 may be one of a bottom gate thin film transistor, a top gate thin film transistor, or a dual gate thin film transistor, and may specifically include the following embodiments.
In one embodiment, as shown in fig. 4, the first thin film transistor 301 includes a first metal layer including a plurality of metal portions 3014 and a second metal layer including a first metal portion 3012 and a second metal portion 3013, the second thin film transistor 401 includes a third metal layer 4011 and a fourth metal layer including a third metal portion 4013 and a fourth metal portion 4014; the data line is electrically connected to the third metal portion 4013, the scan line is electrically connected to the third metal layer 4011, the fourth metal portion 4014 is electrically connected to the metal portion 3014 in the first metal layer, the first metal portion 3012 is loaded with a working voltage, the second metal portion 3013 is electrically connected to the light emitting layer 20, and the data line and the scan line control the fourth metal portion 4014 to control the light emitting condition of the light emitting layer 20.
Further, the first thin film transistor 301 further includes a first conductive layer 3011, a material of the first conductive layer 3011 may include polysilicon to serve as an active layer of the first thin film transistor 301, and specifically, the first conductive layer 3011 may be made by using a low temperature polysilicon technology to have a higher electron mobility, so that when the first thin film transistor 301 charges the light emitting layer 20, a larger driving current may be generated to increase a charging speed, and both ends of the first conductive layer 3011 may be further doped with particles to form a doped region to serve as an ohmic contact layer to reduce a contact resistance between the first conductive layer 3011 and the first metal portion 3012 and the second metal portion 3013; a first gate insulating layer 3015 may be disposed on the first conductive layer 3011 and the substrate 10 to isolate the metal portion 3014 of the first metal layer from the first conductive layer 3011, a material of the first gate insulating layer 3015 may include at least one of an inorganic dielectric material and an organic dielectric material, specifically, the inorganic dielectric material may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the organic dielectric material may be a polymer material such as polyimide-based resin, epoxy-based resin, or acryl-based resin; the metal portion 3014 may be disposed opposite to the first conductive layer 3011 to serve as a gate of the first thin film transistor 301, and disposed opposite to the first via 601 to be electrically connected to the fourth metal portion 4014; an inter-insulating layer 70 may be disposed on the metal portion 3014 and the first gate insulating layer 3015, and is configured to isolate the metal portion 3014 of the first metal layer from the first metal portion 3012 and the second metal portion 3013 located above the metal portion 3014, where a composition material of the inter-insulating layer 70 may refer to a related description of a composition material of the first gate insulating layer 3015; third via holes 603 and fourth via holes 604 are respectively formed in the first gate insulating layer 3015 and the inter-layer insulating layer 70 at positions opposite to the first metal portion 3012 and the second metal portion 3013, and the first metal portion 3012 and the second metal portion 3013 are electrically connected to the first conductive layer 3011 through the third via holes 603 and the fourth via holes 604, respectively.
Further, the third metal layer 4011 may be disposed on the first insulating layer 501 as a gate of the second thin film transistor 401; the second thin film transistor 401 further includes a second conductive layer 4012, the second conductive layer 4012 and the third metal layer 4011 are oppositely disposed to serve as an active layer of the second thin film transistor 401, two ends of the second conductive layer 4012 are respectively connected to the third metal portion 4013 and the fourth metal portion 4014, and the second conductive layer 4012 may be made of indium gallium zinc oxide, so that the second thin film transistor has the advantages of low preparation temperature, high mobility, small leakage current and the like; a second gate insulating layer 4015 may be disposed over the second conductive layer 4012 and the first insulating layer 501, for isolating the third metal layer 4011 from the second conductive layer 4012; when preparing third metal portion 4013, fourth metal portion 4014, can also prepare fifth metal portion 4016 on the same layer, fifth metal portion 4016 can with second metal portion 3013 sets up relatively, and is further in first insulating layer 501 on the second gate insulating layer 4015 with can set up fifth via hole 605 on the position that fifth metal portion 4016 is relative, with electric connection fifth metal portion 4016 with second metal portion 3013.
Further, a flat layer 503 is disposed between the second circuit layer 40 and the light emitting layer 20, and the second via 602 is disposed on the flat layer 503 at a position opposite to the fifth metal portion 4016, so as to electrically connect the fifth metal portion 4016 and the light emitting layer 20. It is understood that the data line and the scan line control the fourth metal portion 4014 of the second thin film transistor 401, the fourth metal portion 4014 controls the second metal portion 3013 of the first thin film transistor 401 through the first via, and the second metal portion 3013 controls the light emission of the light emitting layer 20 through the fifth via 605, the fifth metal portion 4016 and the second via 602.
In one embodiment, as shown in fig. 5, the embodiment shown in fig. 5 differs from the embodiment shown in fig. 4 mainly in that: the specific structure of the first thin film transistor 301 is different. Specifically, the first conductive layer 3011 may include indium gallium zinc oxide as an active layer of the first thin film transistor 301, and both ends of the first conductive layer 3011 may be further doped with particles to form doped regions; the first gate insulating layer 3015 may be provided only on the first conductive layer 3011 to isolate the first conductive layer 3011 and the metal portion 3014; a third insulating layer 505 may be provided over the second thin film transistor 401 and the interlayer insulating layer 70, and a material of the third insulating layer 505 may be the same as that of the interlayer insulating layer 70; in order to save the manufacturing process of the fifth metal portion 4016, the first metal portion 3012 and the second metal portion 3013 may be disposed on the third insulating layer 505, and the third via 603 and the fourth via 604 may be disposed on the inter-insulating layer 70 and the third insulating layer 505, respectively, and the light emitting layer 20 is electrically connected to the second metal portion 3013 through the second via 602.
In one embodiment, as shown in fig. 6, the embodiment shown in fig. 6 differs from the embodiment shown in fig. 4 mainly in that: the specific structure of the first thin film transistor 301 is different. Specifically, the first conductive layer 3011 may include indium gallium zinc oxide as an active layer of the first thin film transistor 301, and the first conductive layer 3011 is disposed above the metal portion 3014; the second thin film transistor 401 and the first thin film transistor 301 are partially overlapped in the longitudinal direction, and the metal portion 3014 and the second thin film transistor 401 are partially overlapped in the longitudinal direction, so that the second thin film transistor 401 can be electrically connected with the metal portion 3014 through the first via hole 601; the first metal portion 3012 and the second metal portion 3013 are respectively disposed at two ends of the first conductive layer 3011 and directly connected to the first conductive layer 3011.
In some embodiments, as shown in fig. 7-8, the second thin film transistor 401 may also be disposed above the first thin film transistor 301. Specifically, as shown in fig. 7, the first thin film transistor 301 has a top-gate structure, and is different from the embodiment shown in fig. 5 only in that: the second thin film transistor 401 is disposed below the first thin film transistor 301, and reference may be made to the description of the embodiment shown in fig. 5 for related description; as shown in fig. 8, the first thin film transistor 301 has a bottom gate structure, and is different from the embodiment shown in fig. 6 only in that: the second thin film transistor 401 is disposed below the first thin film transistor 301, and reference may be made to the description of the embodiment shown in fig. 6 for related description.
It is understood that the first via 601, the second via 602, the third via 603, the fourth via 604 and the fifth via 605 are all provided with conductive materials for electrically connecting to corresponding structures.
In some embodiments, the composition materials of the first insulating layer 501, the third insulating layer 505, the first gate insulating layer 3015, the second gate insulating layer 4015 and the inter-insulating layer 70 may refer to the description related to the composition material of the buffer layer; or may include at least one of polymethyl methacrylate and polyimide, or may be a composite layer formed of each of the organic materials, or may be a composite layer formed of the inorganic material or the organic material.
In some embodiments, the active layer of the first thin film transistor 301 and/or the second thin film transistor 401 may be formed of amorphous silicon, single crystal silicon, or amorphous zinc tin oxide, in addition to the above-mentioned polycrystalline silicon or indium gallium zinc oxide.
In an embodiment, as shown in fig. 9, the display panel 00 includes a bending region 03 and a non-bending region 04, the bending region 30 is used for bending the display panel 00, and the second thin film transistor 401 is disposed in the non-bending region 04. It can be understood that, since the first thin film transistor 301 controls the light emitting portion 201 in the light emitting layer 20 to emit light, and the light emitting portions 201 are all disposed in the display area 01, the first thin film transistor 301 should be disposed in the display area 01 and correspond to the light emitting portions 201 one by one, or only disposed in the area where the display area 01 overlaps the non-bending area 04, so as to prevent the first thin film transistor 301 from falling off after the bending area 03 is bent many times; in addition, since the second thin film transistor 401 may be electrically connected to the plurality of first thin film transistors 301 in the same row or the same column through the first via holes 601, in order to reduce the risk of the second thin film transistor 401 falling off and improve the screen occupation ratio of the display panel 00, the second thin film transistor 401 may be disposed at any position of the overlapping region of the display region 01 and the non-bending region 04, so as to reduce the requirements on the circuit design and process of the second circuit layer 40, improve the flexibility of the circuit design and manufacture of the second circuit layer 40, and further, in order to improve the aperture ratio of the pixel, the second thin film transistor 401 may be disposed at a position corresponding to the black matrix 202 in the non-bending region 04.
The present application further provides a method for manufacturing a display panel, which is used for manufacturing the display panel as described in any one of the above, wherein the display panel has a display area, as shown in fig. 10, and the method includes the following steps.
S10, providing a substrate.
Wherein, the substrate can be a glass substrate or a metal substrate.
S20, forming a circuit layer on the substrate, wherein the circuit layer comprises a first circuit layer and a second circuit layer, the first circuit layer comprises a first thin film transistor, the second circuit layer is arranged on one side, close to or far away from the substrate, of the first circuit layer, the second circuit layer comprises a second thin film transistor, the first thin film transistor and the second thin film transistor are arranged in the display area, and the second thin film transistor is electrically connected with the first thin film transistor.
In an embodiment, the substrate and the circuit layer may further include a flexible substrate and a buffer layer in sequence from bottom to top, the flexible substrate may be made of one of polyimide, polystyrene, or polydimethylsiloxane, the buffer layer may be made of at least one of silicon nitride, silicon oxide, titanium oxide, and aluminum oxide, and the buffer layer may also be a composite layer formed by the above inorganic materials.
Particularly, the first thin film transistor and the second thin film transistor are arranged in the display area, so that the area of the non-display area is prevented from being occupied, and the non-display area is prevented from being too large to reduce the screen occupation ratio.
And S30, forming a light emitting layer on the circuit layer, wherein the first thin film transistor is electrically connected with the light emitting layer, and the second thin film transistor controls the light emitting condition of the light emitting layer by controlling the first thin film transistor.
In one embodiment, in the display region, the light-emitting layer includes a plurality of light-emitting portions that emit light to a side away from the substrate, and a black matrix provided between the plurality of light-emitting portions, and the first thin film transistor and/or the second thin film transistor are provided opposite to the light-emitting portions and/or the black matrix.
The light emitting parts may be OLED devices for emitting light in the display panel or other devices for emitting light, and it can be understood that each light emitting part can emit light of a specific color, which corresponds to one sub-pixel, and a plurality of light emitting parts or a plurality of sub-pixels may constitute one pixel unit; it can be understood that, when the light-emitting portions emit light to a side away from the substrate, on one hand, the first thin film transistor, the second thin film transistor, and metal traces such as scan lines and data lines in the first circuit layer and the second circuit layer may be disposed in the display region so as not to occupy the non-display region to reduce the screen occupation ratio of the display panel, and further, the first thin film transistor and the second thin film transistor disposed in different layers may reduce the complexity of the circuit structure in the same layer and improve the reliability of signal transmission in the circuit, and on the other hand, the first thin film transistor, the second thin film transistor, and metal traces such as scan lines and data lines in the first circuit layer and the second circuit layer may be disposed in different layers, The metal wires such as the data wires can be intensively arranged in the non-display area, so that when the light emitted by the light emitting part is reflected to the first circuit layer and the second circuit layer, the light can be reflected out of the display panel after being reflected for multiple times, and the light utilization rate of the light emitting part can be improved.
In one embodiment, the plurality of light emitting portions further emit light to a side close to the substrate, and the plurality of first thin film transistors and the plurality of second thin film transistors are disposed opposite to the black matrix.
It should be noted that, when the plurality of light emitting parts emit light toward the side close to the substrate, light emitted from the light emitting parts passes through the first circuit layer and the second circuit layer and then is emitted from the substrate, and therefore, the light transmittance of the region of the first circuit layer and the second circuit layer, which is opposite to the light emitting parts, affects the aperture ratio of the sub-pixel. It is understood that, by disposing the plurality of first thin film transistors and the plurality of second thin film transistors and the metal wirings, such as the scan lines and the data lines, in the first circuit layer and the second circuit layer in the display area, further, by disposing the metal wirings opposite to the black matrix, the aperture ratio of the sub-pixels and the light utilization ratio of the light emitting part can be improved.
In an embodiment, a projection of the second thin film transistor on the first circuit layer may overlap with the first thin film transistor. It can be understood that, since the second thin film transistor is electrically connected to the first thin film transistor, the distance between the two is reduced, the reliability of the electrical connection between the two is improved, the area in the horizontal direction can be saved, and the aperture ratio of the sub-pixel can be improved to the greatest extent under the same other conditions.
In an embodiment, the display panel further includes an insulating layer and a via hole, the insulating layer includes a first insulating layer, the first insulating layer is disposed between the first circuit layer and the second circuit layer, the via hole includes a first via hole, the first via hole is disposed on the first insulating layer, and the second thin film transistor is electrically connected to the first thin film transistor through the first via hole.
Further, the insulating layer still includes the second insulating layer, the second insulating layer locate the second circuit layer with between the luminescent layer, the via hole still includes the second via hole, the second via hole is located the first insulating layer, the second circuit layer and on the second insulating layer, the luminescent layer pass through the second via hole with first thin film transistor electric connection. It is understood that, in order to increase the aperture ratio of the sub-pixel, the second via hole may be disposed opposite to the black matrix, but the first thin film transistor is electrically connected to the light emitting part through the second via hole to control the light emission of the light emitting layer.
It will be appreciated that the method also includes other embodiments, reference being made to the above description relating to the display panel.
The application provides a display panel, a display device and a manufacturing method of the display panel, the display panel comprises a substrate, a luminous layer, a first circuit layer and a second circuit layer, the first circuit layer comprises a first thin film transistor, the second circuit layer comprises a second thin film transistor, the second thin film transistor is arranged in a display area and is arranged on a different layer with the first thin film transistor layer, the second thin film transistor does not occupy a non-display area of the display panel, the size of the non-display area around the display panel is reduced, and the screen occupation ratio of the display panel is improved.
The structures of the display panel and the display device provided by the embodiments of the present application and the manufacturing method of the display panel are described in detail above, and a specific example is applied in the present application to explain the principle and the implementation of the present application, and the description of the above embodiments is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A display panel having a display area, the display panel comprising:
a substrate;
a light emitting layer disposed on the substrate;
the first circuit layer is arranged on one side, close to the substrate, of the light emitting layer and comprises a first thin film transistor, the first thin film transistor is arranged in the display area, and the first thin film transistor is electrically connected with the light emitting layer;
the second circuit layer is arranged on one side, close to or far away from the substrate, of the first circuit layer and comprises a second thin film transistor, the second thin film transistor is arranged in the display area and is electrically connected with the first thin film transistor so as to control the light emitting condition of the light emitting layer.
2. The display panel of claim 1, wherein the display panel further comprises:
an insulating layer disposed between the first circuit layer and the second circuit layer;
the via hole is formed in the insulating layer, and the second thin film transistor is electrically connected with the first thin film transistor through the via hole.
3. The display panel according to claim 1, wherein the light-emitting layer includes a plurality of light-emitting portions that emit light to a side away from the substrate, and a black matrix provided between the plurality of light-emitting portions, and wherein the first thin film transistor and/or the second thin film transistor is provided so as to be opposed to the light-emitting portions and/or the black matrix.
4. The display panel according to claim 3, wherein the plurality of light emitting portions further emit light to a side close to the substrate, and wherein the plurality of first thin film transistors and the plurality of second thin film transistors are each disposed opposite to the black matrix.
5. The display panel according to claim 3 or 4, wherein a projection of the second thin film transistor on the first circuit layer overlaps with the first thin film transistor.
6. The display panel according to claim 1, wherein the display panel comprises a bending region and a non-bending region, the bending region is used for bending the display panel, and the second thin film transistor is disposed in the non-bending region.
7. The display panel according to claim 1, wherein the first thin film transistor includes a first metal layer and a second metal layer, the second metal layer includes a first metal portion and a second metal portion, the second thin film transistor includes a third metal layer and a fourth metal layer, the fourth metal layer includes a third metal portion and a fourth metal portion;
the data line is electrically connected with the third metal part, the scanning line is electrically connected with the third metal layer, the fourth metal part is electrically connected with the first metal layer, the first metal part is loaded with working voltage, the second metal part is electrically connected with the light-emitting layer, and the data line and the scanning line control the light-emitting condition of the light-emitting layer by controlling the fourth metal part.
8. The display panel according to claim 1, wherein the first thin film transistor and/or the second thin film transistor is one of a bottom gate type thin film transistor, a top gate type thin film transistor, or a double gate type thin film transistor.
9. A method of manufacturing a display panel having a display area according to any one of claims 1 to 8, the method comprising:
providing a substrate;
forming a circuit layer on the substrate, wherein the circuit layer comprises a first circuit layer and a second circuit layer, the first circuit layer comprises a first thin film transistor, the second circuit layer is arranged on one side, close to or far away from the substrate, of the first circuit layer, the second circuit layer comprises a second thin film transistor, the first thin film transistor and the second thin film transistor are both arranged in the display area, and the second thin film transistor is electrically connected with the first thin film transistor;
and a light emitting layer is formed on the circuit layer, the first thin film transistor is electrically connected with the light emitting layer, and the second thin film transistor controls the light emitting condition of the light emitting layer by controlling the first thin film transistor.
10. A display device characterized in that it comprises a display panel according to any one of claims 1 to 8.
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| CN202010423212.6A CN111627962A (en) | 2020-05-19 | 2020-05-19 | Display panel, display device and manufacturing method of display panel |
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| CN202010423212.6A CN111627962A (en) | 2020-05-19 | 2020-05-19 | Display panel, display device and manufacturing method of display panel |
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