CN111863704A - 用于熔接和剥离的低密度硅氧化物的方法和结构 - Google Patents

用于熔接和剥离的低密度硅氧化物的方法和结构 Download PDF

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CN111863704A
CN111863704A CN202010326105.1A CN202010326105A CN111863704A CN 111863704 A CN111863704 A CN 111863704A CN 202010326105 A CN202010326105 A CN 202010326105A CN 111863704 A CN111863704 A CN 111863704A
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substrate
silicon oxide
oxide
substrates
semiconductor wafer
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CN111863704B (zh
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今井清隆
相泽宽和
前田宽
前川薰
三村裕司
末永治信
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Tokyo Electron Ltd
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Abstract

本文中描述的是一种接合以及/或者剥离基底的方法。在一个实施方案中，要被接合的基底的表面中的至少一个包括氧化物。在一个实施方案中，两个基底的表面均包括氧化物。然后，可以利用湿蚀刻通过蚀刻掉已经接合的层来剥离基底。在一个实施方案中，利用熔接工艺来接合两个基底，至少一个基底具有硅氧化物表面。在一种示例性蚀刻中，利用稀氢氟酸(DHF)蚀刻来蚀刻接合的硅氧化物表面，从而允许剥离两个接合的基底。在另一个实施方案中，硅氧化物可以是低密度硅氧化物。在一个实施方案中，两个基底都可以具有可以被熔接在一起的低密度硅氧化物的表面层。

Description

用于熔接和剥离的低密度硅氧化物的方法和结构
相关申请的交叉引用
本申请要求2019年4月24日提交的题为“Method And Structure for LowDensity Silicon Oxide for Fusion Bonding and Debonding”的美国临时专利申请第62/837,993号和2019年9月17日提交的题为“Method And Structure for Low DensitySilicon Oxide for Fusion Bonding and Debonding”的美国专利申请第16/573,775号的优先权，其全部公开内容通过引用明确地并入本文。
技术领域
本公开涉及基底的处理。特别地，本公开提供了一种用于使基底接合和剥离(脱开，debonding)的新方法。
背景技术
在各种工艺流程中利用基底的接合以处理基底。例如，在形成微机电系统(MEMS)、纳米机电系统(NEMS)、光电子学、绝缘体基底上硅、多层器件、三维器件以及其他半导体器件时，可以将基底接合用作工艺流程的一部分。在基底接合中，通常将两个基底接合在一起。图1示出了用于多基底结构100的一种示例性基底接合构造。如图1中所示，设置有上基底105和下基底110。
如图1中所示，两个基底被接合在一起。在图1中，上基底105(例如上晶片)具有正面器件区域112和背面器件区域114两者以及附加的背面区域115。在一个示例工艺流程中，上晶片可以经受处理以形成正面器件，并且然后上晶片可以被翻转并接合至下晶片，以允许背面器件区域的处理。然而，这样的工艺流程仅仅是示例性的，并且如在本领域中已知的，存在许多其他基底接合工艺流程和用途。
存在各种各样被用于将基底接合在一起的技术，包括熔接(也被称为直接接合)、阳极接合、共晶接合、热压接合、表面活化接合、等离子体活化接合、粘结剂接合等。传统的粘结剂接合通常使用厚度约为30um或更厚的胶粘剂。这样的技术的优点在于，粘结剂接合易于通过机械、热或激光技术剥离。然而，在粘结剂接合中使用的厚膜具有高的总厚度变化(TTV)，这使得后续精细间距光刻图案化变得困难。另外，接合后的处理条件由于粘结剂的热特性而受到温度限制。熔融(或直接)接合是一种常用的接合类型。在熔接(fusionbonding)中，在两个基底的两个表面之间形成化学键。通常，熔接工艺包括清洁基底表面和对准基底，并且然后使用某种形式的基底的退火(在高温或低温下)来完成化学接合。一种用于熔接的技术使作为硅的两个基底的表面用于熔接，但是可以使用其他材料。
在一些先进的基底处理流程中，可能期望在基底之一的背面处理完成之后使基底脱开。然而，由于熔接的强接合特性，在使用熔接时剥离是困难的。
期望提供一种提供良好的接合特性但使得能够易于剥离的接合工艺技术。
发明内容
本文中描述了一种用于使基底接合和/或剥离的新方法。在一个实施方案中，待接合的基底的表面中的至少一个表面包括氧化物。在一个实施方案中，两个基底的表面均包括氧化物。然后，可以执行基底的熔接。随后，然后可以利用湿蚀刻通过蚀刻掉已经接合的层来剥离基底。在一个实施方案中，利用熔接工艺来接合两个基底，至少一个基底具有硅氧化物表面。在一种示例性蚀刻中，利用稀氢氟酸(DFH)蚀刻来蚀刻接合的硅氧化物表面，使得两个接合的基底能够脱开。在一个实施方案中，硅氧化物可以是低密度硅氧化物。在一个实施方案中，两个基底可以都具有可以被熔接在一起的低密度硅氧化物的表面层。
在一个实施方案中，公开了一种用于处理第一基底和第二基底的方法。该方法包括在第一基底和第二基底中的至少一个上设置氧化物表面层。该方法还包括熔接第一基底和第二基底。该方法还包括通过使用氧化物蚀刻剂来使第一基底和第二基底脱开。
在方法的一些实施方案中，氧化物表面层包括硅氧化物。在一些实施方案中，氧化物蚀刻剂包括湿的氧化物蚀刻剂。氧化物蚀刻剂可以包括氢氟酸。在一些实施方案中，氧化物蚀刻剂包括稀氢氟酸。在其他实施方案中，第一基底具有第一氧化物表面层，并且第二基底具有第二氧化物表面层。在一些实施方案中，第一氧化物表面层包括硅氧化物，并且第二氧化物表面层包括硅氧化物。在一些实施方案中，熔接形成Si-O-Si键。
在另一个实施方案中，公开了一种多基底结构。多基底结构可以包括第一半导体晶片和第二半导体晶片。多基底结构还包括在第一半导体晶片与第二半导体晶片之间的硅氧化物层，第一半导体晶片和第二半导体晶片通过硅氧化物层熔接在一起。
在多基底结构的一些实施方案中，在第一半导体晶片和第二半导体晶片被熔接之前，第一半导体晶片和第二半导体晶片中之一具有硅氧化物表面。在其他实施方案中，在第一半导体晶片和第二半导体晶片被熔接之前，第一半导体晶片具有第一硅氧化物表面，并且第二半导体晶片具有第二硅氧化物表面。在又一实施方案中，硅氧化物层在第一半导体晶片与第二半导体晶片之间形成Si-O-Si键。在多基底结构的又一实施方案中，硅氧化物层的至少第一部分是第一半导体晶片的一部分，并且硅氧化物层的第二部分是第二半导体晶片的一部分。在又一实施方案中，第一半导体晶片或第二半导体晶片中的至少一个包括正面处理区域和背面处理区域。
附图说明
可以通过参考结合附图的以下描述来获取对本发明及其优点的更完整的理解，在附图中，相同的附图标记表示相同的特征。然而，应当注意，附图仅示出了所公开的构思的示例性实施方案，并且因此不应被视为对范围的限制，因为所公开的构思可以允许其他等效的实施方案。
图1示出了示例性多基底结构。
图2A示出了根据本文中公开的技术构造的接合之前的两个基底。
图2B示出了接合之后的图2A的两个基底。
图3A至图3B示出了根据本文中公开的技术构造的示例性多基底结构。
图4A至图4E示出了根据本文中公开的技术的示例性接合和剥离工艺。
图5示出了用于利用本文中公开的接合技术的示例性方法。
具体实施方式
本文中描述的是一种用于接合和/或剥离基底的新方法。在一个实施方案中，待接合的基底的表面中的至少一个表面包括氧化物。在一个实施方案中，两个基底的表面均包括氧化物。然后，可以执行基底的熔接。随后，然后可以利用湿蚀刻通过蚀刻掉已经接合的层来剥离基底。在一个实施方案中，利用熔接工艺来接合两个基底，至少一个基底具有硅氧化物表面。在一个示例性蚀刻中，利用稀氢氟酸(DHF)蚀刻来蚀刻接合的硅氧化物表面，允许两个接合的基底脱开。在一个实施方案中，硅氧化物可以是低密度硅氧化物。在一个实施方案中，两个基底可以都具有可以被熔接在一起的低密度硅氧化物的表面层。
可以在多种不同的基底的处理期间利用本文中公开的技术。基底可以是期望使用基底接合和/或剥离的任何基底。在一个实施方案中，至少一个基底可以是已经经受了多个半导体处理步骤的基底，所述多个半导体处理步骤产生了各种各样的结构和层，所有的这些结构和层在基底处理领域中都是已知的，并且可以被认为是基底的一部分。例如，在一个实施方案中，基底可以是在其上形成有一个或更多个半导体处理层的半导体晶片。可以在基底工艺流程的任何阶段例如前段制程(FEOL)处理步骤和/或后段制程(BEOL)处理步骤处利用本文中公开的构思。在一些实施方案中，基底之一可以仅仅是载体基底。在一些实施方案中，可以利用载体基底来在另一基底正被处理(例如背面处理)时保持另一基底。
在一个实施方案中，上基底(例如上晶片)和下基底(例如下晶片)两者均具有露出的氧化物表面(例如硅氧化物表面)。图2A示出了这样的布置，在该布置中，上基底205具有上基底氧化物表面206，并且下基底210具有下基底氧化物表面211。图2B示出了上基底205和下基底210的熔接。更特别地，图2A示出了在接合之前的每个基底和露出的表面。如图2B中所示，在熔接脱水缩合工艺之后，两个基底通过在两个基底之间产生Si-O-Si键而变为被接合。在所示的示例性实施方案中，上基底和下基底两者均具有氧化物层。然而，将认识到，即使仅一个表面具有露出的氧化物层，仍然可以利用本文中公开的技术。此外，在所示的示例性实施方案中，使用硅氧化物层来接合基底。将认识到，可以利用其他氧化物使用本文中公开的技术，所述其他氧化物包括例如但不限于碳氧化硅(SiOC)、SiCOH、氮氧化硅(SiON)等。
图3A示出了例如图2A和图2B中所示的工艺的多基底结构300和得到的接合的基底的示例性实施方案。
如图3A中所示，多基底结构300的上基底305(例如上晶片)具有正面器件区域316、基底主体318(例如硅)和背面器件区域320。还设置了下基底310(例如下晶片)。上基底305和下基底310通过接合硅氧化物层314接合在一起。在图3A中所示的实施方案中，两个基底之间的硅氧化物可以是低密度硅氧化物。接合硅氧化物层314可以被认为是上基底、下基底或两者的一部分。可以通过上述的接合工艺来形成接合硅氧化物层314，其中使用在接合之前的基底中的一个或两个基底的露出的表面上的硅氧化物层来将基底接合在一起。
如果期望使图3A的两个基底脱开，则可以将基底暴露于湿的稀氢氟酸(DHF)。DHF将提供对接合硅氧化物层314的高蚀刻速率。因此，如图3B中所示，可以将接合的基底暴露于DHF湿蚀刻。接合硅氧化物层314的低密度硅氧化物将具有对于DHF的高蚀刻速率，并且DHF将起到去除接合硅氧化物层314的作用。一旦去除接合硅氧化物层，然后就可以容易地分离上基底305和下基底310。将认识到，蚀刻剂不一定是湿蚀刻剂。例如，可以使用HF气相蚀刻。可替选地，可以利用其他硅氧化物蚀刻剂。此外，取决于所利用的氧化物，蚀刻剂还可以包括磷酸。
将认识到，用于将两个基底接合在一起的氧化物层的厚度可以取决于使用本文中公开的技术的特定应用而变化。在一个实施方案中，上基底和下基底可以各自具有厚度小于10um并且更特别地在5um至10nm的范围内并且甚至更特别地在500nm至100nm的范围内的氧化物。
图4A示出了利用本文中公开的技术的示例性工艺流程。如图4A中所示，第一基底405可以经受各种处理以在其上形成结构和器件。例如，基底可以经受标准的前段制程(FEOL)和/或后段制程(BEOL)半导体处理，以形成第一基底405的FEOL/BEOL区域410。第一基底405可以是图2A至图3B的示例中的上基底。接下来，第一基底405然后可以在其上形成硅氧化物层，在一个实施方案中为低密度硅氧化物(未示出)。接下来，如图4B中所示，第一基底405可以被翻转并接合至载体基底415(载体基底可以是图2至图3B的下基底)。如上所述，载体基底也可以具有硅氧化物的表面。然后，如图2A中所示，可以将两个基底熔接，以在两个基底之间提供Si-O-Si键连接。然后，第一基底405可以经受各种基底处理步骤中的任何一个。例如，如图4C中所示，第一基底405可以经受边缘修整、磨削和/或化学机械平坦化(CMP)工艺步骤，以将第一基底405减薄为经减薄的第一基底405A。然后，如图4D中所示，还可以执行任何附加的背面处理以形成背面处理区域420。最终，可以使用本文中所述的氧化物蚀刻剥离技术将第一基底405从载体基底415剥离，并且如图4E中所示，也可以对第一基底405进行切割。
如图4A至图4E中所述，提供了一种工艺，在该工艺中，甚至对于可能后续期望被剥离的基底，也可以获得并利用融合处理(fusion processing)的优点。在图4A至图4E的示例中，执行对基底的正面处理，并且然后执行该基底与载体晶片的接合，使得然后可以发生基底的背面处理。在所示的示例中，正面处理的基底被接合至载体基底，并且然后在背面处理之后，基底被剥离。
接合和剥离技术可以有利地被用在各种各样的应用中，而不限于图4A至图4E的示例。因此，在多种其他应用中可以使用先硅氧化物熔接然后进行蚀刻硅氧化物的剥离工艺的使用。实际上，期望熔接两个基底但是后续剥离基底的各种各样的工艺可以利用本文中描述的技术。此外，虽然本文中就一个或多个硅氧化物层和DHF蚀刻进行了描述，但是将认识到，可以利用其他氧化物和其他蚀刻剂。因此，例如，可以使用除硅氧化物之外的其他氧化物以用于接合工艺，并且可以使用用于这些氧化物的适当的蚀刻剂。此外，即使对于硅氧化物熔接，蚀刻剂也不限于DHF，因为可以利用其他硅氧化物蚀刻剂。将认识到，在剥离工艺之后，在进一步处理之前，基底可以经历清洁工艺。
如上所述，在一个实施方案中，低密度氧化物可以被用作熔接工艺的一部分。在一个特定实施方案中，该氧化物可以是低密度硅氧化物。如本文中所使用的，低密度硅氧化物可以是密度为2g/cm3或更小的氧化物。使用低密度氧化物的优点在于，低密度氧化物的蚀刻特性使得氧化物可以更快速且更容易地被去除。例如，可以使用DHF相对容易地去除低密度硅氧化物。
图5示出了用于使用本文中描述的处理技术的示例性方法。将认识到，图5的实施方案仅仅是示例性的，并且其他方法可以利用本文中描述的技术。此外，可以将附加的处理步骤添加至图5中所示的方法，因为所描述的步骤并非意在是排他性的。此外，步骤的顺序不限于附图中所示的顺序，因为可以发生不同的顺序以及/或者可以以组合的方式或同时执行各种步骤。
图5示出了用于处理第一基底和第二基底的方法。该方法包括在第一基底和第二基底中的至少一个上设置氧化物表面层的第一步骤505。该方法还包括熔接第一基底和第二基底的步骤510。该方法还包括通过使用氧化物蚀刻剂来使第一基底和第二基底脱开的步骤515。
鉴于该说明书，本发明的进一步修改和替选实施方案对于本领域技术人员将是明显的。因此，该描述应被理解为仅说明性的，并且是出于教导本领域技术人员实施本发明的方式的目的。应当理解，在本文中示出和描述的本发明的形式和方法将被视为当前的优选实施方案。等同的技术可以代替本文中所示和描述的那些技术，并且可以独立于使用其他特征来利用本发明的某些特征，所有这些在受益于本发明的该描述之后对于本领域技术人员而言将都是明显的。

Claims (20)

1.一种用于处理第一基底和第二基底的方法，包括：
在所述第一基底和所述第二基底中的至少一个上设置氧化物表面层；
熔接所述第一基底和所述第二基底；以及
通过使用氧化物蚀刻剂来使所述第一基底与所述第二基底脱开。
2.根据权利要求1所述的方法，其中，所述氧化物表面层包括低密度硅氧化物。
3.根据权利要求2所述的方法，其中，所述氧化物蚀刻剂包括氢氟酸。
4.根据权利要求3所述的方法，其中，所述氧化物蚀刻剂包括稀氢氟酸。
5.根据权利要求1所述的方法，其中，所述第一基底具有第一氧化物表面层，以及所述第二基底具有第二氧化物表面层。
6.根据权利要求5所述的方法，其中，所述第一氧化物表面层包括低密度硅氧化物，以及所述第二氧化物表面层包括低密度硅氧化物。
7.根据权利要求6所述的方法，其中，所述熔接形成Si-O-Si键。
8.根据权利要求7所述的方法，其中，所述氧化物蚀刻剂包括湿的氧化物蚀刻剂。
9.根据权利要求8所述的方法，其中，所述氧化物蚀刻剂包括氢氟酸。
10.根据权利要求1所述的方法，其中，所述氧化物蚀刻剂包括湿的氧化物蚀刻剂。
11.根据权利要求10所述的方法，其中，所述第一基底具有第一氧化物表面层，以及所述第二基底具有第二氧化物表面层。
12.根据权利要求11所述的方法，其中，所述第一氧化物表面层包括低密度硅氧化物，以及所述第二氧化物表面层包括低密度硅氧化物。
13.根据权利要求12所述的方法，其中所述熔接形成Si-O-Si键。
14.根据权利要求13所述的方法，其中，所述氧化物蚀刻剂包括氢氟酸。
15.一种多基底结构，包括：
第一半导体晶片；
第二半导体晶片；以及
在所述第一半导体晶片与所述第二半导体晶片之间的硅氧化物层，所述第一半导体晶片和所述第二半导体晶片通过所述硅氧化物层熔接在一起。
16.根据权利要求15所述的多基底结构，其中，在所述第一半导体晶片和所述第二半导体晶片被熔接之前，所述第一半导体晶片和所述第二半导体晶片中之一具有低密度的硅氧化物表面。
17.根据权利要求15所述的多基底结构，其中，在所述第一半导体晶片和所述第二半导体晶片被熔接之前，所述第一半导体晶片具有低密度第一硅氧化物表面，以及所述第二半导体晶片具有低密度第二硅氧化物表面。
18.根据权利要求15所述的多基底结构，其中，所述硅氧化物层在所述第一半导体晶片与所述第二半导体晶片之间提供Si-O-Si键。
19.根据权利要求18所述的多基底结构，其中，所述硅氧化物层的至少第一部分是所述第一半导体晶片的一部分，以及所述硅氧化物层的第二部分是所述第二半导体晶片的一部分。
20.根据权利要求19所述的多基底结构，其中，所述第一半导体晶片或所述第二半导体晶片中的至少之一包括正面处理区域和背面处理区域。
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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1689781A (zh) * 2004-01-28 2005-11-02 株式会社Jsp 厚壁发泡成型体及其制造方法
US20060071274A1 (en) * 2004-09-28 2006-04-06 International Business Machines Corporation Method and structure for bonded silicon-on-insulator wafer
CN102201368A (zh) * 2010-03-24 2011-09-28 美丽微半导体股份有限公司 硅晶片与基板共构表面粘着型二极管元件制造方法及构造
CN102583219A (zh) * 2012-03-29 2012-07-18 江苏物联网研究发展中心 一种晶圆级mems器件的真空封装结构及封装方法
CN103288043A (zh) * 2012-03-05 2013-09-11 台湾积体电路制造股份有限公司 高纵横比mems器件及其形成方法
US20140312436A1 (en) * 2013-04-23 2014-10-23 Matthieu Lagouge Method of fabricating mems device having release etch stop layer
US20170179155A1 (en) * 2009-10-12 2017-06-22 Monolithic 3D Inc. 3d memory device and structure
US20170263457A1 (en) * 2016-03-08 2017-09-14 Ostendo Technologies, Inc. Apparatus and Methods to Remove Unbonded Areas Within Bonded Substrates Using Localized Electromagnetic Wave Annealing
US20190043914A1 (en) * 2016-02-16 2019-02-07 G-Ray Switzerland Sa Structures, systems and methods for electrical charge transport across bonded interfaces

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19840421C2 (de) 1998-06-22 2000-05-31 Fraunhofer Ges Forschung Verfahren zur Fertigung von dünnen Substratschichten und eine dafür geeignete Substratanordnung
JP2002261281A (ja) 2001-03-01 2002-09-13 Hitachi Ltd 絶縁ゲートバイポーラトランジスタの製造方法
US7420147B2 (en) * 2001-09-12 2008-09-02 Reveo, Inc. Microchannel plate and method of manufacturing microchannel plate
US20070128827A1 (en) * 2001-09-12 2007-06-07 Faris Sadeg M Method and system for increasing yield of vertically integrated devices
US6875671B2 (en) * 2001-09-12 2005-04-05 Reveo, Inc. Method of fabricating vertical integrated circuits
US7163826B2 (en) * 2001-09-12 2007-01-16 Reveo, Inc Method of fabricating multi layer devices on buried oxide layer substrates
US7033910B2 (en) * 2001-09-12 2006-04-25 Reveo, Inc. Method of fabricating multi layer MEMS and microfluidic devices
TW200423261A (en) * 2002-11-20 2004-11-01 Reveo Inc Method of fabricating multi-layer devices on buried oxide layer substrates
US20080160274A1 (en) * 2006-12-31 2008-07-03 Chi Hung Dang Coefficient of thermal expansion adaptor
FR2926674B1 (fr) 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable
US20100104852A1 (en) 2008-10-23 2010-04-29 Molecular Imprints, Inc. Fabrication of High-Throughput Nano-Imprint Lithography Templates
US10043781B2 (en) * 2009-10-12 2018-08-07 Monolithic 3D Inc. 3D semiconductor device and structure
US9953972B2 (en) * 2009-10-12 2018-04-24 Monolithic 3D Inc. Semiconductor system, device and structure
EP2908335B1 (en) * 2014-02-14 2020-04-15 ams AG Dicing method
US10672674B2 (en) * 2018-06-29 2020-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor device package having testing pads on a topmost die
JP2021535613A (ja) * 2018-09-04 2021-12-16 中芯集成電路（寧波）有限公司 ウェハレベルパッケージ方法及びパッケージ構造

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1689781A (zh) * 2004-01-28 2005-11-02 株式会社Jsp 厚壁发泡成型体及其制造方法
US20060071274A1 (en) * 2004-09-28 2006-04-06 International Business Machines Corporation Method and structure for bonded silicon-on-insulator wafer
US20170179155A1 (en) * 2009-10-12 2017-06-22 Monolithic 3D Inc. 3d memory device and structure
CN102201368A (zh) * 2010-03-24 2011-09-28 美丽微半导体股份有限公司 硅晶片与基板共构表面粘着型二极管元件制造方法及构造
CN103288043A (zh) * 2012-03-05 2013-09-11 台湾积体电路制造股份有限公司 高纵横比mems器件及其形成方法
CN102583219A (zh) * 2012-03-29 2012-07-18 江苏物联网研究发展中心 一种晶圆级mems器件的真空封装结构及封装方法
US20140312436A1 (en) * 2013-04-23 2014-10-23 Matthieu Lagouge Method of fabricating mems device having release etch stop layer
US20190043914A1 (en) * 2016-02-16 2019-02-07 G-Ray Switzerland Sa Structures, systems and methods for electrical charge transport across bonded interfaces
US20170263457A1 (en) * 2016-03-08 2017-09-14 Ostendo Technologies, Inc. Apparatus and Methods to Remove Unbonded Areas Within Bonded Substrates Using Localized Electromagnetic Wave Annealing
KR20180132672A (ko) * 2016-03-08 2018-12-12 오스텐도 테크놀로지스 인코포레이티드 국부 전자파 어닐링을 이용하여 접착된 기판들내의 비접착 영역들을 제거하기 위한 장치 및 방법

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
T. SUNI等: "Characterization of Bonded Interface by HF Etching Method", 《SEMICONDUCTOR WAFER BONDING VII: SCIENCE, TECHNOLOGY AND APPLICATIONS, ELECTROCHEMICAL SOCIETY》 *

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