TW202107537A - 用於低密度矽氧化物的熔融接合與脫接方法及結構 - Google Patents

用於低密度矽氧化物的熔融接合與脫接方法及結構 Download PDF

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TW202107537A
TW202107537A TW109113470A TW109113470A TW202107537A TW 202107537 A TW202107537 A TW 202107537A TW 109113470 A TW109113470 A TW 109113470A TW 109113470 A TW109113470 A TW 109113470A TW 202107537 A TW202107537 A TW 202107537A
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substrate
silicon oxide
semiconductor wafer
substrates
oxide
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TW109113470A
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TWI836062B (zh
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今井清隆
相澤宏一
前田浩史
前川薰
三村勇之
末永晴信
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日商東京威力科創股份有限公司
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Abstract

本文所描述的係一種用於將複數基板接合及/或脫接的方法。在一實施例中，待接合的該等基板之至少一表面係包括氧化物。在一實施例中，兩個基板的表面均包括氧化物。濕蝕刻可接著應用以透過將已接合的層蝕刻掉使該等基板脫接。在一實施例中，使用熔融接合處理以接合兩基板，其中至少一基板係具有矽氧化物表面。在一示例性蝕刻中，使用稀氫氟酸（DHF）蝕刻來蝕刻已接合的矽氧化物表面，以允許兩個已接合基板進行脫接。在另一實施例中，矽氧化物可為低密度矽氧化物。在一實施例中，兩基板均可具有可熔融接合在一起的低密度矽氧化物之表面層。

Description

用於低密度矽氧化物的熔融接合與脫接方法及結構
本揭露係關於基板的處理。具體而言，本揭露提供一種用於將基板接合（bonding）與脫接（debonding）的創新方法。 [相關申請案的交互參照]
本申請案是主張於2019年4月24日提交的美國臨時專利申請案第62/837,993號且標題為「Method And Structure for Low Density Silicon Oxide for Fusion Bonding and Debonding」，以及於2019年9月17日提交的美國專利申請案第16/573,775號且標題為「Method And Structure for Low Density Silicon Oxide for Fusion Bonding and Debonding」的優先權，其所有揭露內容皆以參照的方法明確地引入本文。
基板的接合係應用在基板處理的各種處理流程中。舉例而言，基板的接合可應用作為形成微機電系統（MEMS）、奈米機電系統（NEMS）、光電元件、絕緣層上覆矽的基板、多層裝置、三維裝置、以及其他半導體裝置的處理流程之一部分。在基板的接合中，通常係將兩基板接合在一起。圖1繪示多基板（multi-substrate）結構100所用的一種示例性基板接合配置。如圖1中所顯示，提供上部基板105及下部基板110。
如圖1中所顯示，兩基板係接合在一起。在圖1中，上部基板105（例如，上部晶圓）具有前側裝置區域112與背側裝置區域114兩者、以及附加背側區域115。在一示例性處理流程中，上部晶圓可能已歷經處理以形成前側裝置，接著可將該上部晶圓翻轉並與下部晶圓接合以允許背側裝置區域的處理。然而，這樣的處理流程僅為示例性的，並且存在著許多其他處理流程以及如本領域中所習知的基板接合之使用。
存在著應用於將基板接合在一起的各式各樣技術，包括熔融接合（亦稱為直接接合）、陽極接合、共熔接合、熱壓接合、表面活化接合、電漿活化接合、黏著劑接合等。習知的黏著劑接合通常係使用厚度大約為30微米或更厚的黏膠。這種技術的優點在於黏著劑接合係易於透過機械、熱、或雷射技術來進行脫接。然而，在黏著劑接合中所使用的厚膜具有高的總厚度變異值（TTV），使得後續的細間距（fine pitch）微影圖案化變得困難。此外，後接合處理的條件係溫度受限於黏著劑的熱特性。熔融（或直接）接合係一種常用的接合類型。在熔融接合中，在兩基板的兩表面之間會形成化學鍵結。一般而言，熔融接合處理包括清潔基板表面、將基板對準、並接著使用一些基板的退火形式（在高溫或低溫下）以完成化學接合。熔融接合的一種技術係兩基板的表面為矽，然而其他材料可用於熔融接合。
在一些進階基板處理流程中，在其中一基板的背側處理完成後可能需要將基板脫接。然而，當使用熔融接合時，由於熔融接合的強接合特性，脫接係難以進行的。
需要提供一種提供良好接合特性但能易於脫接的接合處理技術。
本文所描述的係一種用於將複數基板接合及/或脫接的創新方法。在一實施例中，待接合的該等基板之至少一表面係包括氧化物。在一實施例中，兩基板的表面均包括氧化物。接著，可執行該等基板的熔融接合。隨後，可接著應用濕蝕刻，透過將已接合的層蝕刻掉使該等基板脫接。在一實施例中，使用熔融接合處理以接合兩基板，其中至少一基板係具有矽氧化物表面。在一示例性蝕刻中，使用稀氫氟酸（DHF）蝕刻來蝕刻已接合的矽氧化物表面，以允許兩個已接合基板進行脫接。在一實施例中，矽氧化物可為低密度矽氧化物。在一實施例中，兩基板均可具有可熔融接合在一起的低密度矽氧化物之表面層。
在一實施例中，揭露一種第一基板及第二基板的處理方法。該方法包括在第一基板及第二基板的至少一者上提供氧化物表面層。該方法更包括將第一基板及第二基板進行熔融接合。該方法更包括透過使用氧化物蝕刻劑使第一基板及第二基板脫接。
在該方法的一些實施例中，氧化物表面層包括矽氧化物。在一些實施例中，該氧化物蝕刻劑包括濕式氧化物蝕刻劑。氧化物蝕刻劑可包括氫氟酸。在一些實施例中，該氧化物蝕刻劑包括稀氫氟酸。在其他實施例中，第一基板具有第一氧化物表面層，且第二基板具有第二氧化物表面層。在一些實施例中，第一氧化物表面層包括矽氧化物，且第二氧化物表面層包括矽氧化物。在一些實施例中，該熔融接合形成Si-O-Si鍵。
在另一實施例中，揭露一種多基板結構。該多基板結構可包括第一半導體晶圓及第二半導體晶圓。該多基板結構更包括介於該第一半導體晶圓與該第二半導體晶圓之間的矽氧化物層，該第一半導體晶圓及該第二半導體晶圓係透過該矽氧化物層而熔融接合在一起。
在多基板結構的一些實施例中，在第一半導體晶圓及第二半導體晶圓進行熔融接合之前，該第一半導體晶圓及該第二半導體晶圓的其中一者具有矽氧化物表面。在其他實施例中，在第一半導體晶圓及第二半導體晶圓進行熔融接合之前，該第一半導體晶圓具有第一矽氧化物表面，且該第二半導體晶圓具有第二矽氧化物表面。在又另一實施例中，矽氧化物層在第一半導體晶圓與第二半導體晶圓之間形成Si-O-Si鍵。在多基板結構的仍另一實施例中，至少矽氧化物層的第一部分為第一半導體晶圓的一部份，且該矽氧化物層的第二部分為第二半導體晶圓的一部份。在仍另一實施例中，第一及第二半導體晶圓的至少一者包括前側處理區域及後側處理區域。
本文所描述的係一種用於將複數基板接合及/或脫接的創新方法。在一實施例中，待接合的該等基板之至少一表面係包括氧化物。在一實施例中，兩基板的表面均包括氧化物。接著，可執行該等基板的熔融接合。隨後，可接著應用濕蝕刻，透過將已接合的層蝕刻掉使該等基板脫接。在一實施例中，使用熔融接合處理以接合兩基板，其中至少一基板係具有矽氧化物表面。在一示例性蝕刻中，使用稀氫氟酸（DHF）蝕刻來蝕刻已接合的矽氧化物表面，以允許兩個已接合基板進行脫接。在一實施例中，矽氧化物可為低密度矽氧化物。在一實施例中，兩基板均可具有可熔融接合在一起的低密度矽氧化物之表面層。
本文所揭露的技術可在各種基板進行處理的期間所使用。所述基板可為需要使用基板接合及/或脫接的任何基板。在一實施例中，至少一基板可為已歷經複數半導體處理步驟的基板，其中該等半導體處理步驟產出各種結構與層體，該等結構與層體均為基板處理領域中所習知並可被視為是基板的一部分。舉例來說，在一實施例中，基板可為具有一或更多半導體處理層形成在其上的半導體晶圓。本文所揭露的概念可應用在基板處理流程的任何階段，例如前端製程（FEOL）處理步驟及/或後端製程（BEOL）處理步驟。在一些實施例中，其中一基板可僅為載體基板。在一些實施例中，當其他基板正在進行處理（例如，背側處理）的同時，載體基板可用以固持所述的其他基板。
在一實施例中，上部基板（例如，上部晶圓）及下部基板（例如，下部晶圓）兩者各具有暴露的氧化物表面（例如，矽氧化物表面）。圖2A繪示這樣的配置，其中上部基板205具有上部基板氧化物表面206，而下部基板210具有下部基板氧化物表面211。圖2B繪示上部基板205與下部基板210的熔融接合。更具體而言，圖2A繪示接合之前的各基板及暴露表面。如圖2B中所顯示，在熔融接合的脫水縮合處理之後，透過在兩基板之間形成Si-O-Si鍵來接合兩基板。在所顯示的示例性實施例中，上部及下部基板兩者均具有氧化物層。然而，將能理解的是，即便是僅一表面具有暴露的氧化物層仍可應用本文所揭露的技術。此外，在所顯示的示例性實施例中，係使用矽氧化物層來接合基板。將能理解的是，本文所揭露的技術可利用其他氧化物來進行應用，包括：例如但不限於矽氧化物碳化物（SiOC）、SiCOH、矽氮氧化物（SiON）等。
圖3A繪示多基板結構300、以及例如圖2A及2B中所見之處理所得到的已接合基板之示例性實施例。
如圖3A中所顯示，多基板結構300提供具有前側裝置區域316、基板本體318（例如，矽）、及背側裝置區域320的上部基板305（例如，上部晶圓）。還提供下部基板310（例如，下部晶圓）。上部基板305及下部基板310係利用鍵結的矽氧化物層314來接合在一起。在圖3A中所顯示的實施例，介於兩基板之間的矽氧化物可為低密度矽氧化物。鍵結的矽氧化物層314可被視為是上部基板、下部基板、或兩者的一部分。可藉由上述的接合處理來形成鍵結的矽氧化物層314，其中在使用鍵結以將基板接合在一起之前，矽氧化物層係位在一或二基板的暴露表面上。
假使需要將圖3A中的兩基板脫接，可將該等基板暴露於濕式稀氫氟酸（DHF）。DHF將提供鍵結的矽氧化物層314的高蝕刻速率。因此，如圖3B中所顯示，可將已接合的基板暴露至DHF濕蝕刻。鍵結的矽氧化物層314的低密度矽氧化物將具有對於DHF的高蝕刻速率，且DHF將會作用以移除鍵結的矽氧化物層314。在移除鍵結的矽氧化物層之後，則可將上部基板305及下部基板310輕易分離。將能理解的是，蝕刻劑不必為濕式蝕刻劑。例如，可使用HF氣相蝕刻。或者，可使用其他矽氧化物蝕刻劑。此外，根據所應用的氧化物，蝕刻劑還可包括磷酸。
將能理解的是，用以將兩基板接合在一起的氧化物層之厚度可取決於本文揭露之技術所使用的特定用途而有所改變。在一實施例中，上部及下部基板可各具有厚度小於10 um的氧化物，且更具體地是在5 um至10 nm的範圍中，且甚至更具體地為500 nm至100 nm。
圖4A繪示應用本文所揭露之技術的示例性處理流程。如圖4A中所顯示，第一基板405可歷經各種處理以在其上形成結構及裝置。舉例而言，基板可歷經標準前端製程（FEOL）及/或後端製程（BEOL）的半導體處理，以形成第一基板405的FEOL/ BEOL區域410。第一基板405可為圖2A~3B之示例中的上部基板。接下來，第一基板405可接著具有形成在其上的矽氧化物層，在一實施例中為低密度矽氧化物（未顯示）。接著，如圖4B中所顯示，可將第一基板405翻轉並與載體基板415接合（該載體基板可為圖2A~3B的下部基板）。載體基板還可具有如上所述的矽氧化物表面。接著可將兩基板進行熔融接合，例如圖2A中所顯示在兩基板之間提供Si-O-Si鍵連接。接著，第一基板405可歷經各種基板處理步驟的任何一種。舉例而言，第一基板405可歷經邊緣修整、研磨、及/或化學機械平坦化（CMP）處理步驟，以將第一基板405薄化成為如圖4C中所顯示的薄化第一基板405A。接著，還可執行任何附加的背側處理以形成如圖4D中所顯示的背側處理區域420。最後，可使用本文所述的氧化物蝕刻脫接技術以將第一基板405從載體基板415上脫接，且還可將第一基板405切成如圖4E中所顯示的小塊。
如圖4A~4E中所描述，提供了一種處理，其中可得到熔融處理的優點，並且還應用於後續可能需要進行脫接的基板。在圖4A~4E中的示例中，執行基板的前側處理並且接著執行將該基板接合至載體晶圓，使得基板的背側處理可接著發生。在所顯示的示例中，係將已處理前側的基板接合至載體基板，並接著在進行背側處理之後將基板脫接。
接合及脫接技術可有利地使用在各種應用中，然而，其並不受限於圖4A~4E的示例。因此，在各種其他的應用中可使用矽氧化物的熔融接合，之後接著將矽氧化物進行蝕刻的脫接處理。實際上，需要將兩基板熔融接合但後續將該等基板脫接的各種處理可應用本文所述的技術。此外，雖然在本文中所描述的是關於矽氧化物層與DHF蝕刻，但將能理解到可應用其他氧化物及其他蝕刻劑。因此，舉例來說，可將矽氧化物之外的其他氧化物用於接合處理，並可將合適的蝕刻劑用於這些氧化物。此外，即便是矽氧化物的熔融接合，蝕刻劑並不受限於DHF而是可應用其他的矽氧化物蝕刻劑。將能理解的是，於脫接處理之後，在進行進一步處理之前可將基板經歷清潔處理。
如上所述，在一實施例中可將低密度氧化物使用作為熔融接合處理的一部分。在一特定實施例中，氧化物可為低密度矽氧化物。如本文中所使用，低密度矽氧化物可為2 g/cm3 或更低密度的氧化物。使用低密度氧化物的優勢在於低密度氧化物的蝕刻特性，使得氧化物可更快速且輕易地被移除。例如，低密度矽氧化物可相對較容易地利用DHF來進行移除。
圖5繪示用於使用本文所述之處理技術的示例性方法。將能理解的是，圖5的實施例僅為示例性的，且額外的方法可應用本文所述的技術。此外，可將額外的處理步驟添加至圖5中所顯示的方法，因此所描述的步驟之用意並非為排他性的。另外，該等步驟的順序並不受限於圖中所顯示的順序，因此可存在不同順序、及/或可結合或同時執行各種步驟。
圖5繪示用於處理第一基板及第二基板的方法。該方法包括第一步驟505，以在第一基板及第二基板的至少一者上提供氧化物表面層。該方法更包括步驟510，以將第一基板及第二基板進行熔融接合。該方法還包括步驟515，以透過使用氧化物蝕刻劑使第一基板及第二基板脫接。
由於此實施方式，本發明的進一步修改及替代實施例對於本領域中具有通常知識者將為顯而易知的。因此，係將此實施方式僅解釋為說明性的，且目的係為了教示本領域中具有通常知識者實施本發明的方法。應當理解到，本文中所顯示及描述的發明形式及方法將被視為當前的較佳實施例。在受益於本發明的此實施方式後，對於本領域中具有通常知識者將為顯而易知的是，等效性技術可取代在本文中繪示及描述的那些技術，且本發明的某些特徵可獨立於其他特徵的使用來進行應用。
100:多基板結構 105:上部基板 110:下部基板 112:前側裝置區域 114:背側裝置區域 115:附加背側區域 205:上部基板 206:上部基板氧化物表面 210:下部基板 211:下部基板氧化物表面 300:多基板結構 305:上部基板 310:下部基板 314:鍵結的矽氧化物層 316:前側裝置區域 318:基板本體 320:背側裝置區域 405:第一基板 405A:薄化第一基板 410:FEOL/ BEOL區域 415:載體基板 420:背側處理區域 505, 510, 515:步驟
透過參照以下結合附圖所進行的描述，可獲得對本發明及其優點的更完整理解，其中相同的元件符號表示相同特徵。然而，應當注意的是，附圖僅繪示所揭露概念的示例性實施例，且因此不應被認為是對範圍的限制，所揭露的概念係可容納其他等效的實施例。
圖1繪示出示例性的多基板結構。
圖2A繪示在進行接合之前根據本文揭露的技術所配置的兩基板。
圖2B繪示在圖2A的兩基板進行接合之後。
圖3A~3B繪示根據本文揭露的技術所配置的示例性多基板結構。
圖4A~4E繪示根據本文揭露之技術的示例性接合與脫接處理。
圖5繪示用於應用本文所揭露之接合技術的示例性方法。
505,510,515:步驟

Claims (20)

  1. 一種第一基板及第二基板的處理方法，包括： 在該第一基板及該第二基板的至少一者上提供一氧化物表面層； 將該第一基板及該第二基板進行熔融接合；以及 透過使用一氧化物蝕刻劑使該第一基板及該第二基板脫接。
  2. 如請求項1之第一基板及第二基板的處理方法，其中該氧化物表面層包括低密度矽氧化物。
  3. 如請求項2之第一基板及第二基板的處理方法，其中該氧化物蝕刻劑包括氫氟酸。
  4. 如請求項3之第一基板及第二基板的處理方法，其中該氧化物蝕刻劑包括稀氫氟酸。
  5. 如請求項1之第一基板及第二基板的處理方法，其中該第一基板具有一第一氧化物表面層，且該第二基板具有一第二氧化物表面層。
  6. 如請求項5之第一基板及第二基板的處理方法，其中該第一氧化物表面層包括一低密度矽氧化物，且該第二氧化物表面層包括一低密度矽氧化物。
  7. 如請求項6之第一基板及第二基板的處理方法，其中該熔融接合形成Si-O-Si鍵。
  8. 如請求項7之第一基板及第二基板的處理方法，其中該氧化物蝕刻劑包括濕式氧化物蝕刻劑。
  9. 如請求項8之第一基板及第二基板的處理方法，其中該氧化物蝕刻劑包括氫氟酸。
  10. 如請求項1之第一基板及第二基板的處理方法，其中該氧化物蝕刻劑包括濕式氧化物蝕刻劑。
  11. 如請求項10之第一基板及第二基板的處理方法，其中該第一基板具有一第一氧化物表面層，且該第二基板具有一第二氧化物表面層。
  12. 如請求項11之第一基板及第二基板的處理方法，其中該第一氧化物表面層包括一低密度矽氧化物，且該第二氧化物表面層包括一低密度矽氧化物。
  13. 如請求項12之第一基板及第二基板的處理方法，其中該熔融接合形成Si-O-Si鍵。
  14. 如請求項13之第一基板及第二基板的處理方法，其中該氧化物蝕刻劑包括氫氟酸。
  15. 一種多基板結構，包括： 一第一半導體晶圓； 一第二半導體晶圓；及 一矽氧化物層，介於該第一半導體晶圓與該第二半導體晶圓之間，該第一半導體晶圓及該第二半導體晶圓係透過該矽氧化物層而熔融接合在一起。
  16. 如請求項15之多基板結構，其中在該第一半導體晶圓及該第二半導體晶圓進行熔融接合之前，該第一半導體晶圓及該第二半導體晶圓的其中一者具有一低密度矽氧化物表面。
  17. 如請求項15之多基板結構，其中在該第一半導體晶圓及該第二半導體晶圓進行熔融接合之前，該第一半導體晶圓具有一低密度第一矽氧化物表面，且該第二半導體晶圓具有一低密度第二矽氧化物表面。
  18. 如請求項15之多基板結構，其中該矽氧化物層在該第一半導體晶圓與該第二半導體晶圓之間提供Si-O-Si鍵。
  19. 如請求項18之多基板結構，其中至少該矽氧化物層的一第一部分為該第一半導體晶圓的一部份，且該矽氧化物層的一第二部分為該第二半導體晶圓的一部份。
  20. 如請求項19之多基板結構，其中該第一半導體晶圓及該第二半導體晶圓的至少一者包括一前側處理區域及一後側處理區域。
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Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3294934B2 (ja) * 1994-03-11 2002-06-24 キヤノン株式会社 半導体基板の作製方法及び半導体基板
DE19840421C2 (de) * 1998-06-22 2000-05-31 Fraunhofer Ges Forschung Verfahren zur Fertigung von dünnen Substratschichten und eine dafür geeignete Substratanordnung
JP2002261281A (ja) * 2001-03-01 2002-09-13 Hitachi Ltd 絶縁ゲートバイポーラトランジスタの製造方法
US7163826B2 (en) * 2001-09-12 2007-01-16 Reveo, Inc Method of fabricating multi layer devices on buried oxide layer substrates
US7033910B2 (en) * 2001-09-12 2006-04-25 Reveo, Inc. Method of fabricating multi layer MEMS and microfluidic devices
US7420147B2 (en) * 2001-09-12 2008-09-02 Reveo, Inc. Microchannel plate and method of manufacturing microchannel plate
US6875671B2 (en) * 2001-09-12 2005-04-05 Reveo, Inc. Method of fabricating vertical integrated circuits
US20070128827A1 (en) * 2001-09-12 2007-06-07 Faris Sadeg M Method and system for increasing yield of vertically integrated devices
TW200421497A (en) * 2002-11-20 2004-10-16 Reveo Inc Method and system for increasing yield of vertically integrated devices
TW200533701A (en) * 2004-01-28 2005-10-16 Jsp Corp Thick foam molding and process for production thereof
US7358586B2 (en) * 2004-09-28 2008-04-15 International Business Machines Corporation Silicon-on-insulator wafer having reentrant shape dielectric trenches
US20080160274A1 (en) * 2006-12-31 2008-07-03 Chi Hung Dang Coefficient of thermal expansion adaptor
FR2926674B1 (fr) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable
US20100104852A1 (en) * 2008-10-23 2010-04-29 Molecular Imprints, Inc. Fabrication of High-Throughput Nano-Imprint Lithography Templates
US9953972B2 (en) * 2009-10-12 2018-04-24 Monolithic 3D Inc. Semiconductor system, device and structure
US10043781B2 (en) * 2009-10-12 2018-08-07 Monolithic 3D Inc. 3D semiconductor device and structure
US10388863B2 (en) * 2009-10-12 2019-08-20 Monolithic 3D Inc. 3D memory device and structure
CN102201368B (zh) * 2010-03-24 2013-06-19 美丽微半导体股份有限公司 硅晶片与基板共构表面粘着型二极管元件制造方法及构造
US8828772B2 (en) * 2012-03-05 2014-09-09 Taiwan Semiconductor Manufacturing Co., Ltd. High aspect ratio MEMS devices and methods for forming the same
CN102583219A (zh) * 2012-03-29 2012-07-18 江苏物联网研究发展中心 一种晶圆级mems器件的真空封装结构及封装方法
US8932893B2 (en) * 2013-04-23 2015-01-13 Freescale Semiconductor, Inc. Method of fabricating MEMS device having release etch stop layer
EP2908335B1 (en) * 2014-02-14 2020-04-15 ams AG Dicing method
US9299736B2 (en) * 2014-03-28 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding with uniform pattern density
JP2019511834A (ja) * 2016-02-16 2019-04-25 ジーレイ スイッツァーランド エスアー 接合インターフェースを横断する電荷輸送のための構造、システムおよび方法
US10373830B2 (en) * 2016-03-08 2019-08-06 Ostendo Technologies, Inc. Apparatus and methods to remove unbonded areas within bonded substrates using localized electromagnetic wave annealing
US10672674B2 (en) * 2018-06-29 2020-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor device package having testing pads on a topmost die
JP2021535613A (ja) * 2018-09-04 2021-12-16 中芯集成電路（寧波）有限公司 ウェハレベルパッケージ方法及びパッケージ構造

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