CN111710671A - Packaging structure and packaging method of high-voltage power semiconductor chip - Google Patents
Packaging structure and packaging method of high-voltage power semiconductor chip Download PDFInfo
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- CN111710671A CN111710671A CN202010768651.0A CN202010768651A CN111710671A CN 111710671 A CN111710671 A CN 111710671A CN 202010768651 A CN202010768651 A CN 202010768651A CN 111710671 A CN111710671 A CN 111710671A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 181
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 109
- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 76
- 238000012360 testing method Methods 0.000 claims description 77
- 238000007747 plating Methods 0.000 claims description 37
- 238000005245 sintering Methods 0.000 claims description 28
- 239000000919 ceramic Substances 0.000 claims description 26
- 239000000523 sample Substances 0.000 claims description 22
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- 238000003466 welding Methods 0.000 claims description 9
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- 238000005137 deposition process Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 229920001296 polysiloxane Polymers 0.000 claims description 4
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- 239000010410 layer Substances 0.000 description 47
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 10
- 229910010271 silicon carbide Inorganic materials 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
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- 229910000962 AlSiC Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
A packaging structure and a packaging method of a high-voltage power semiconductor chip are provided, the packaging structure of the high-voltage power semiconductor chip comprises: a substrate; the high-voltage power semiconductor chip is positioned on the substrate, and a grid electrode is arranged on one surface of the high-voltage power semiconductor chip, which is opposite to the substrate; the first packaging frame cover covers the high-voltage power semiconductor chip, the first packaging frame cover is provided with a first top plate, and a grid electrode reserved opening is formed in the first top plate; and one end of the grid electrode leading-out part is positioned in the grid electrode reserved opening and is electrically connected with the grid electrode. The parasitic inductance of the packaging structure of the high-voltage power semiconductor chip is reduced.
Description
Technical Field
The invention relates to the field of power semiconductor device packaging, in particular to a packaging structure and a packaging method of a high-voltage power semiconductor chip.
Background
In order to meet the large-scale development and utilization of renewable energy sources, the traditional power grid is developing towards the smart power grid represented by the wide application of power electronic technology, and the power electronic device plays an irreplaceable role in various fields such as the strong smart power grid construction of national power grid companies, FACTS high-voltage power transmission, new energy access and the like, so that higher requirements on high-voltage, high-capacity, high-frequency and high-temperature resistant power electronic devices are undoubtedly provided. Most of the high-power electronic devices of the existing power system adopt silicon-based power electronic devices to realize control and conversion of electric energy, and the silicon-based power electronic devices are limited by physical characteristics of materials such as voltage resistance, working temperature and the like, so that the reliability and stability of high-power electronic equipment are fundamentally improved, the overall loss of the system is reduced, the control conversion efficiency of energy sources is improved, and novel power electronic devices with higher voltage resistance, lower power consumption and high temperature resistance need to be researched and developed. The Silicon Carbide (SiC) based device is one of the most mature and widely applied third-generation semiconductor power electronic devices, can break through the physical limit of the traditional Silicon-based device, has the advantages of high voltage level, large through-current capacity, small loss, quick heat dissipation and the like, can be widely applied to novel power electronic equipment such as a solid-state transformer and a solid-state circuit breaker and traditional FACTS and direct-current transmission equipment, has important influence on the aspects of economic safety operation and the like of a power system, and realizes the innovation of the power grid technology.
The grid of a traditional silicon-based power electronic device usually adopts another conducting layer from which a bonding lead is led out, and a grid testing electrode and the conducting layer are sintered or welded together.
At present, the packaging structure of a high-voltage silicon carbide-based device is less, the high-voltage silicon carbide-based device needs low parasitic inductance, however, if the high-voltage silicon carbide-based device adopts the same packaging form as a silicon-based power electronic device, the performance requirement of the high-voltage silicon carbide-based device is difficult to meet due to the defect of larger parasitic inductance caused by more bonding leads.
Disclosure of Invention
The invention aims to overcome the defect of high parasitic inductance of a high-voltage power semiconductor chip in the prior art.
In order to solve the above technical problem, the present invention provides a package structure of a high voltage power semiconductor chip, including: a substrate; the high-voltage power semiconductor chip is positioned on the substrate, and a grid electrode is arranged on one surface of the high-voltage power semiconductor chip, which is opposite to the substrate; the first packaging frame cover covers the high-voltage power semiconductor chip, the first packaging frame cover is provided with a first top plate, and a grid electrode reserved opening is formed in the first top plate; and one end of the grid electrode leading-out part is positioned in the grid electrode reserved opening and is electrically connected with the grid electrode.
Optionally, the area of the top surface of the gate lead-out portion is larger than the area of the top surface of the gate.
Optionally, the opening area of the gate reservation port is smaller than the top surface area of the gate.
Optionally, the opening area of the gate reserved opening is 0.8-0.9 times of the area of the top surface of the gate.
Optionally, the top surface of the gate lead-out portion includes a test connection region, and the area of the test connection region is 2 to 8 times that of the top surface of the gate.
Optionally, the gate reservation port penetrates through the first top plate; the first top plate is also provided with an additional groove which is positioned in the thickness of the first top plate part, the opening of the additional groove faces away from the high-voltage power semiconductor chip, and the additional groove is positioned on the side part of the grid reserved opening and is communicated with the grid reserved opening; the grid lead-out part is also positioned in the additional groove.
Optionally, the gate lead-out portion includes a first lead-out portion and a second lead-out portion, one end of the second lead-out portion is connected to one end of the first lead-out portion, the first lead-out portion and the second lead-out portion form an "L" shape, the first lead-out portion is located in the gate reserved opening and electrically connected to the gate, and the second lead-out portion is located in the additional groove.
Optionally, the method further includes: and the first test electrode assembly comprises a first electrode connecting piece and a first main test electrode connected with the first electrode connecting piece, and the first electrode connecting piece is positioned on the first packaging frame cover and is respectively electrically connected with the grid lead-out part.
Optionally, the first electrode connector covers the entire top surface of the gate lead-out portion.
Optionally, the gate reservation port is located in the first top plate with a partial thickness, and an opening of the gate reservation port faces the high-voltage power semiconductor chip; the grid electrode leading-out part comprises a spring probe and a conducting strip connected with the spring probe, the spring probe is positioned in the grid electrode reserved opening and is electrically connected with the grid electrode, and the conducting strip is embedded in the first top plate; the first top plate also has a gate connection trench therein on a region of the conductive sheet portion.
Optionally, the method further includes: the first testing electrode assembly comprises a first electrode connecting piece, a plurality of second electrode connecting pieces and a first main testing electrode, wherein the second electrode connecting pieces are located in the grid connecting grooves and electrically connected with the conducting strips, the first electrode connecting piece is located on the first packaging frame cover and respectively connected with the second electrode connecting pieces, and the first main testing electrode is connected with the first electrode connecting piece.
Optionally, the first electrode connecting piece is in a rectangular ring structure, and the first main test electrode is connected with a part of the inner ring side wall of the first electrode connecting piece.
Optionally, the method further includes: and the grid sintering plating layer is positioned between one end of the grid lead-out part and the grid.
Optionally, a first emitter is further disposed on a surface of the high-voltage power semiconductor chip opposite to the substrate; a discrete first plating layer atop said first emitter portion; the first top plate is also provided with a plurality of discrete first electrode grooves penetrating through the first top plate, and the first electrode grooves are positioned above the first plating layer and are discrete from the grid reserved openings.
Optionally, the first plating layer is in a long strip shape.
Optionally, the method further includes: a second test electrode assembly, the second test electrode assembly comprising: third electrode connecting members respectively located in the first electrode grooves; a fourth electrode connecting member respectively connected to the third electrode connecting member and positioned on the first package frame cover; a second test main electrode connected to the fourth electrode connection.
Optionally, the material of the first package bezel includes polyimide or ceramic.
Optionally, the substrate comprises a ceramic main substrate and a conductive adhesion layer positioned on the surface of the ceramic main substrate; the high-voltage power semiconductor chip is electrically connected with the conductive adhesion layer.
Optionally, the thickness of the ceramic main substrate is 2mm to 3 mm.
Optionally, the method further includes: the packaging outer frame is positioned on the side part of the substrate, the high-voltage power semiconductor chip and the first packaging frame cover; and the silicone gel layer is positioned between the packaging outer frame and the first packaging frame cover and between the packaging outer frame and the substrate.
The invention also provides a packaging method for preparing the packaging structure of the high-voltage power semiconductor chip, which comprises the following steps: providing a substrate, a high-voltage power semiconductor chip, a first packaging frame cover and a grid lead-out part, wherein one surface of the high-voltage power semiconductor chip is provided with a grid, the first packaging frame cover is provided with a first top plate, and a grid reserved opening is formed in the first top plate; fixedly connecting the high-voltage power semiconductor chip to the substrate, wherein the grid electrode is opposite to the substrate; placing the first packaging frame cover and the grid electrode leading-out part on the high-voltage power semiconductor chip, wherein the grid electrode reserved opening faces to the grid electrode, and one end of the grid electrode leading-out part is positioned in the grid electrode reserved opening; and after the first packaging frame cover and the grid electrode lead-out part are arranged on the high-voltage power semiconductor chip, one end of the grid electrode lead-out part and the grid electrode are sintered together.
Optionally, the area of the top surface of the gate lead-out part is larger than that of the top surface of the gate; the grid electrode reserved opening penetrates through the first top plate; the first top plate is also provided with an additional groove which is positioned in the thickness of the first top plate part, and the additional groove is positioned on the side part of the grid reserved opening and is communicated with the grid reserved opening; placing the first package frame cover and the gate lead-out portion on the high voltage power semiconductor chip, including: placing the first package frame cover on the high-voltage power semiconductor chip, wherein an opening of the additional groove faces away from the high-voltage power semiconductor chip; and placing the grid lead-out part in the grid reserved opening and the additional groove.
Optionally, providing a first test electrode assembly comprising a first electrode connector and a first main test electrode connected to the first electrode connector; after sintering one end of the grid electrode lead-out part and the grid electrode together, placing the first electrode connecting piece on the first packaging frame cover and covering the grid electrode lead-out part; and sintering or welding the first electrode connecting piece and the grid electrode leading-out part together.
Optionally, the area of the top surface of the gate lead-out part is larger than that of the top surface of the gate; the grid electrode reserved opening is positioned in the first top plate with partial thickness, the grid electrode leading-out part comprises a spring probe and a conducting strip connected with the spring probe, the spring probe is positioned in the grid electrode reserved opening, the conducting strip is embedded in the first top plate, and a grid connecting groove positioned on a partial area of the conducting strip is further formed in the first top plate; placing the first package frame cover and the gate lead-out portion on the high voltage power semiconductor chip, including: covering a first packaging frame embedded with a grid electrode lead-out part on the high-voltage power semiconductor chip, wherein the grid connecting groove faces away from the high-voltage power semiconductor chip; sintering one end of the gate lead-out part together with the gate, including: sintering the spring probe and the grid together.
Optionally, the method further comprises providing a first test electrode assembly, wherein the first test electrode assembly comprises a first electrode connecting piece, a plurality of second electrode connecting pieces and a first main test electrode, the first electrode connecting piece is respectively connected with the second electrode connecting pieces, and the first main test electrode is connected with the first electrode connecting piece; after sintering one end of the grid electrode leading-out part and the grid electrode together, placing the second electrode connecting piece in the grid connecting groove, wherein the first electrode connecting piece is positioned on the first packaging frame cover; and after the second electrode connecting piece is arranged in the grid connecting groove, sintering or welding the second electrode connecting piece and the conducting strip at the bottom of the grid connecting groove together.
Correspondingly, the invention also provides a packaging method for preparing the packaging structure of the high-voltage power semiconductor chip, which comprises the following steps: providing a substrate, a high-voltage power semiconductor chip and a first packaging frame cover, wherein a grid is arranged on one surface of the high-voltage power semiconductor chip, the first packaging frame cover is provided with a first top plate, a grid reserved opening is formed in the first top plate, the grid reserved opening penetrates through the first top plate, an additional groove located in the thickness of part of the first top plate is further formed in the first top plate, and the additional groove is located on the side portion of the grid reserved opening and is communicated with the grid reserved opening; fixedly connecting the high-voltage power semiconductor chip to the substrate, wherein the grid electrode is opposite to the substrate; placing the first packaging frame cover on the high-voltage power semiconductor chip, wherein the reserved opening of the grid electrode faces towards the grid electrode, and the opening of the additional groove faces away from the high-voltage power semiconductor chip; and after the first packaging frame cover is arranged on the high-voltage power semiconductor chip, a grid leading-out part is formed in the grid reserved opening and the additional groove by adopting a deposition process or an electroplating process, and the grid leading-out part is contacted with the grid.
The technical scheme of the invention has the following advantages:
1. according to the packaging structure of the high-voltage power semiconductor chip, the first packaging frame cover and the grid electrode leading-out part are arranged, one end of the grid electrode leading-out part is electrically connected with the grid electrode, the first packaging frame cover is adopted to position the grid electrode leading-out part, and the position between one end of the grid electrode leading-out part and the grid electrode can be well controlled. The invention adopts the grid lead-out part to lead out from the grid, and avoids adopting a bonding lead to lead out from the grid, thereby reducing the parasitic inductance.
2. In the packaging structure of the high-voltage power semiconductor chip provided by the technical scheme of the invention, the area of the top surface of the grid lead-out part is larger than that of the top surface of the grid, the extension part (the second lead-out part) of the grid lead-out part is isolated from the high-voltage power semiconductor chip by the first packaging frame cover, and the grid lead-out part is not easily connected with the high-voltage power semiconductor chip except the grid. Because the area of the top surface of the grid electrode leading-out part is larger than that of the top surface of the grid electrode, and the grid electrode leading-out part is electrically connected with the first test electrode assembly, the first test electrode assembly and the grid electrode leading-out part are easier to sinter or weld together, and the problem that the larger first test electrode and the grid electrode are difficult to sinter is avoided.
3. The packaging structure of the high-voltage power semiconductor chip provided by the technical scheme of the invention also comprises the packaging outer frame, and the packaging outer frame is adopted to combine the first packaging frame cover and the second packaging frame cover, so that the internal insulating strength of the packaging structure is improved.
4. In the packaging structure of the high-voltage power semiconductor chip provided by the technical scheme of the invention, the substrate comprises a ceramic main substrate and a conductive adhesion layer positioned on the surface of the ceramic main substrate, and the conductive adhesion layer is electrically connected with a collector of the high-voltage power semiconductor chip. The substrate is made of a ceramic aluminum clad plate, so that the heat dissipation capability of the packaging structure is improved. In addition, the thickness of the ceramic main substrate is 2 mm-3 mm, and the thickness of the ceramic main substrate is thicker, so that the insulating capability and the voltage withstanding capability of the ceramic main substrate can be improved, and the ceramic main substrate is better suitable for the packaging requirement of a high-voltage power semiconductor chip.
5. In the packaging method provided by the technical scheme of the invention, the first packaging frame cover and the grid lead-out part are arranged on the high-voltage power semiconductor chip, the grid reserved opening faces to the grid, one end of the grid lead-out part is positioned in the grid reserved opening, and then one end of the grid lead-out part and the grid are sintered together. By arranging the first packaging frame cover and the grid electrode leading-out part, one end of the grid electrode leading-out part is electrically connected with the grid electrode, and the first packaging frame cover is adopted to position the grid electrode leading-out part, so that the position between one end of the grid electrode leading-out part and the grid electrode can be well controlled. The invention adopts the grid lead-out part to lead out from the grid, and avoids adopting a bonding lead to lead out from the grid, thereby reducing the parasitic inductance.
6. In the packaging method provided by the technical scheme of the invention, because the area of the top surface of the grid lead-out part is larger than that of the top surface of the grid, and the grid lead-out part is used for being electrically connected with the first test electrode assembly, the first test electrode assembly and the grid lead-out part are easier to sinter or weld together, and the problem that the larger first test electrode and the grid are difficult to sinter due to direct sintering is avoided.
7. In the packaging method provided by the technical scheme of the invention, after the first packaging frame cover is arranged on the high-voltage power semiconductor chip, a gate lead-out part is formed in the gate reserved opening and the additional groove by adopting a deposition process or an electroplating process. The invention adopts the grid lead-out part to lead out from the grid, and avoids adopting a bonding lead to lead out from the grid, thereby reducing the parasitic inductance.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic perspective view of a package structure of a high voltage power semiconductor chip according to an embodiment of the invention;
FIG. 2 is an exploded view corresponding to FIG. 1;
FIG. 3 is a schematic diagram of a high voltage power semiconductor chip, an additional power semiconductor chip, and a substrate packaged together according to an embodiment of the invention;
FIG. 4 is a diagram illustrating a first package bezel in accordance with an embodiment of the present invention;
FIG. 5 is a schematic view of a gate lead-out portion according to an embodiment of the present invention;
fig. 6 is a flow chart of a packaging method provided in another embodiment of the invention.
Detailed Description
The technical scheme of the invention is clearly and completely described in the following with reference to the accompanying drawings.
An embodiment of the present invention provides a package structure of a high voltage power semiconductor chip, referring to fig. 1, including:
a substrate 10;
the high-voltage power semiconductor chip 20 is positioned on the substrate 10, and a grid 201 is arranged on one side, opposite to the substrate 10, of the high-voltage power semiconductor chip 20;
a first package frame cover 30 covering the high voltage power semiconductor chip 20, the first package frame cover 30 having a first top plate 301, the first top plate 301 having a gate reservation opening 302 therein;
and a gate lead-out part 40, wherein one end of the gate lead-out part 40 is positioned in the gate reserving hole 302 and is electrically connected with the gate 201.
It should be noted that fig. 2 is provided for more clearly describing the internal structure of the package structure, and fig. 2 is an exploded view corresponding to fig. 1. Fig. 3 is a schematic diagram of the high voltage power semiconductor chip 20, the additional power semiconductor chip 50 and the substrate 10 packaged together. Fig. 4 is a schematic view of the first package bezel 30. Fig. 5 is a schematic view of the gate lead-out portion 40.
In this embodiment, the substrate 10 includes a ceramic main substrate and a conductive adhesive layer on a surface of the ceramic main substrate, and the conductive adhesive layer is used for electrically connecting with a collector of a high-voltage power semiconductor chip. The material of the ceramic main substrate can be AlN or Si3N4Or AlSiC. The material of the conductive adhesion layer may be aluminum. In this embodiment, the substrate is a ceramic aluminum clad plate, which increases the heat dissipation capability of the package structure. The thickness of the ceramic main substrate is 2 mm-3 mm, the thickness of the ceramic main substrate is 2 times larger than that of a common substrate, and the ceramic main substrate has the advantages that: the ceramic main bodyThe substrate is thick, so that the insulating capability and the voltage resistance of the ceramic main substrate can be improved, and the packaging requirement of the high-voltage power semiconductor chip can be better met.
The high-voltage power semiconductor chip 20 includes a SiC-based semiconductor chip, the high-voltage power semiconductor chip 20 is a three-pole power semiconductor chip, one surface of the high-voltage power semiconductor chip 20 has a gate 201 and a first emitter, the first emitter is separated from the gate 201, and the other surface of the high-voltage power semiconductor chip 20 has a first collector, specifically, the high-voltage power semiconductor chip 20 may be a SiC-based IGBT chip or a MOSFET-based IGBT chip.
In the package structure, a first current collector faces the substrate 10, and the first current collector and the conductive adhesion layer are soldered or sintered together.
The package structure further includes: a discrete first plating layer 203 on top of the first emitter portion. The first plating layer 203 functions to: in the process of sintering or welding the second test electrode assembly and the first emitter together, stress release and uniform pressure application in the pressure application process are facilitated, and damage to the high-voltage power semiconductor chip caused by pressure application is avoided.
The first plating layer 203 is elongated.
Specifically, the pitch between each of the first plating layers 203 is equal for any one of the high-voltage power semiconductor chips 20. During the process of sintering or welding the second test electrode assembly and the first emitter together, the first emitter is uniformly pressurized.
In this embodiment, the material of the first plating layer 203 is a conductive material, such as Ag.
The total top surface area of the first plating layer 203 on the first emitter occupies 40% to 60% of the top surface area of the first emitter; the thickness of the first plating layer 203 is 10 to 12 micrometers.
The SiC-based high-voltage power semiconductor chip 20 has the advantages of high voltage resistance, low power consumption, large through-current capacity, quick heat dissipation, high temperature resistance and the like, can be widely applied to novel power electronic equipment such as solid-state transformers and solid-state circuit breakers and the like, and traditional Flexible Alternating Current Transmission Systems (FACTS) and direct current transmission equipment, and has important influence on aspects such as economic safety operation of power systems, and the innovation of power grid technology is realized.
The SiC-based high-voltage power semiconductor chip 20 has the advantage of a high junction temperature.
In the high-voltage power semiconductor chip 20, the top surface area of the gate 201 is smaller, and the top surface area of the gate 201 is usually designed to be 0.4mm by 0.6mm, so that the area of the gate 201 occupying the surface of the high-voltage power semiconductor chip 20 is smaller, and the integration level of the high-voltage power semiconductor chip 20 is improved. In the high voltage power semiconductor chip 20, the top surface area of the gate 201 is smaller than the top surface area of the first emitter and smaller than the top surface area of the first collector.
In this embodiment, the package structure further includes: an additional power semiconductor chip 50, the additional power semiconductor chip 50 being a bipolar power semiconductor chip, which may be, for example, a SiC-based FRD chip. The additional power semiconductor chip 50 is separate from the high voltage power semiconductor chip 20.
One side of the additional power semiconductor chip 50 has a second emitter and the other side of the additional power semiconductor chip has a second collector.
In the package structure, a second current collector faces the substrate 10, and the second current collector and the conductive adhesion layer are soldered or sintered together.
The number of the high-voltage power semiconductor chips 20 is one or more. In this embodiment, the number of the high voltage power semiconductor chips 20 is plural, and the plural high voltage power semiconductor chips 20 are separated from each other. The number of the additional power semiconductor chips 50 is one or more, and in this embodiment, the number of the additional power semiconductor chips 50 is more than one.
In this embodiment, the package structure further includes: a discrete second plating layer 502 on top of the second emitter portion. The second plating layer 502 functions as: in the process of sintering or welding the second test electrode assembly and the second emitter together, pressure diffusion is facilitated, and damage to the additional power semiconductor chip caused by pressurization is avoided.
The second plating layer 502 is shaped like a stripe. In this embodiment, the material of the second plating layer 502 is a conductive material, such as Ag.
The total top surface area of the second plating layer 502 on the second emitter electrode occupies 40% to 60% of the top surface area of the second emitter electrode; the thickness of the second plating layer 502 is 10 to 12 micrometers.
The spacing between each second plating layer 502 is equal for any additional power semiconductor chip 50. During the sintering or welding of the second test electrode assembly to the second emitter electrode, the second emitter electrode is uniformly compressed.
The material of the first package bezel 30 includes polyimide or ceramic, so that the first package bezel 30 has high insulating property. The first sealing bezel 30 has a first top plate 301 and a first side plate 303, and the first side plate 303 is connected to an edge region of the first top plate 301. In the package structure, the first side plate 303 surrounds the side wall of the high voltage power semiconductor chip 20, and the first top plate 301 is located on the top of the high voltage power semiconductor chip 20. A high voltage power semiconductor chip 20 is covered by a first package bezel 30.
In this embodiment, the opening area of the gate reservation port 302 is smaller than the top surface area of the gate 201, which is advantageous in that: in the process of sintering one end of the gate lead-out part 40 and the gate 201 together, even if there is a certain deviation in the alignment between the gate reserve opening 302 and the gate 201, the gate lead-out part 40 will not be sintered on the electrical terminal near the gate 201 around the gate 201, so as to avoid short circuit between the gate lead-out part 40 and the electrical terminal near the gate 201, and reduce the requirement for the alignment accuracy between the gate reserve opening 302 and the gate 201.
If the opening area of the gate reservation port 302 is smaller than 0.8 times of the area of the top surface of the gate 201, the area of the gate 201 exposed by the gate reservation port 302 is too small, and the difficulty in sintering the gate 201 and one end of the gate lead-out portion 40 is increased; if the opening area of the gate reservation opening 302 is greater than 0.9 times of the area of the top surface of the gate 201, it is not obvious to avoid short circuit between the gate lead-out portion 40 and the electrical terminal near the gate 201 and reduce the requirement for alignment accuracy of the gate reservation opening 302 and the gate 201. Therefore, in a specific embodiment, the opening area of the gate reservation port 302 is 0.8 to 0.9 times the area of the top surface of the gate 201.
In this embodiment, the gate opening 302 penetrates through the first top plate 301; the first top plate 301 is further provided with an additional groove 304 positioned in the thickness of a part of the first top plate 301, the opening of the additional groove 304 faces away from the high-voltage power semiconductor chip 20, and the additional groove 304 is positioned on the side of the gate reserving hole 302 and is communicated with the gate reserving hole 302; the gate lead-out portion 40 is also located in the additional groove 304.
In this embodiment, the first top plate 301 further has a plurality of discrete first electrode grooves 305 penetrating through the first top plate, and the first electrode grooves 305 are located above the first plating layer 203 and are discrete from the gate electrode reserved opening 302. The first electrode slot 305 is also separate from the additional slot 304.
In this embodiment, the top surface area of the gate lead-out portion 40 is larger than that of the gate 201.
In this embodiment, the gate lead-out portion 40 includes a first lead-out portion 401 and a second lead-out portion 402, one end of the second lead-out portion 402 is connected to one end of the first lead-out portion 401, the first lead-out portion 401 and the second lead-out portion 402 form an "L" shape, the first lead-out portion 401 is located in the gate reserve opening 302 and electrically connected to the gate 201, and the second lead-out portion 402 is located in the additional groove 304.
In this embodiment, the material of the first lead-out portion 401 and the second lead-out portion 402 is a conductive material, such as a metal, and specifically, may be copper, aluminum, or silver.
In this embodiment, one end of the gate lead-out portion 40 is located in the gate reserving hole 302 and electrically connected to the gate 201, and the top surface area of the gate lead-out portion 40 is larger than that of the gate 201. In this embodiment, the top surface area of the second lead portion 402 is larger than the top surface area of the gate 201.
The top surface of the gate lead-out 40 includes a test connection region for electrical connection with a first test electrode assembly.
In this embodiment, the entire top surface of the gate lead-out portion 40 serves as a test connection region. In this embodiment, the area of the test connection region is 2 to 8 times the area of the top surface of the gate. This makes the area of the test connection region large, the area of the first test electrode assembly in contact with the test connection region large, and the first test electrode assembly easily sinters or is welded with the gate lead-out portion 40.
In this embodiment, the package structure further includes: and a first test electrode assembly 60, the first test electrode assembly 60 including a first electrode connector 601 and a first main test electrode 602 connected to the first electrode connector 601, the first electrode connector 601 being positioned on the first package frame cover 30 and electrically connected to the gate lead-out part 40, respectively. When the high voltage power semiconductor chips 20 are plural, the first electrode connecting member 601 is electrically connected to the gate lead-out portions 40 of the plural high voltage power semiconductor chips 20.
In this embodiment, the first electrode connector 601 is a rectangular ring structure, and the first main test electrode 602 is connected to a part of the inner ring sidewall of the first electrode connector 601.
In this embodiment, the first electrode connector 601 covers the entire top surface of the gate lead-out portion 40.
In this embodiment, the first electrode connector 601 and the gate lead-out portion 40 are sintered or welded together.
In this embodiment, the package structure further includes: and a gate sintered plating layer 204 between one end of the gate lead-out portion 40 and the gate electrode 201. Specifically, the gate sintered plating layer 204 is located between the first lead portion 401 and the gate electrode 201.
The material of the gate sintered plating layer 204 includes Ag.
In this embodiment, the package structure further includes: a second package bezel 70 covering the additional power semiconductor chip 50, the second package bezel 70 having a second top plate 701 and a second side plate 702, the second side plate 702 being connected to an edge region of the second top plate 701. In the package structure, the second side plate 702 surrounds the side wall of the additional power semiconductor chip 50, and the second top plate 701 is located on the top of the additional power semiconductor chip 50. An additional power semiconductor chip 50 is covered by a second package bezel 70.
The material of the second package bezel 70 includes polyimide or ceramic, so that the second package bezel 70 has high insulating property.
The second top plate 701 is provided with a plurality of discrete second electrode grooves 703 penetrating through the second top plate 701, and the second electrode grooves 703 are located above the second plating layer.
In this embodiment, the package structure further includes: a second test electrode assembly 80, the second test electrode assembly 80 comprising: third electrode connection members 801 respectively positioned in the first electrode grooves 305; fourth electrode connectors 802 respectively connected to the third electrode connectors 801 and located on the first package frame cover 30; a second test main electrode 803, said second test main electrode 803 being connected to said fourth electrode connection 802.
When the number of the high voltage power semiconductor chips 20 is plural, the fourth electrode connecting members 802 are connected to the third electrode connecting members 801 on the respective high voltage power semiconductor chips 20, respectively.
In this embodiment, when the additional power semiconductor chip 50 is present, the second test electrode assembly 80 is further electrically connected to the second emitter, and specifically, the second test electrode assembly 50 further includes: a third additional electrode connection 804, the third additional electrode connection 804 being located in the second electrode slot 703; the fourth electrode connections 802 are also connected to the third additional electrode connections 804, respectively.
In this embodiment, the package structure further includes: a package outer frame (not shown) on the side of the substrate 10, and on the substrate 10, the high voltage power semiconductor chip 20 and the first package frame cover 30, and on the additional power semiconductor chip 50 and the second package frame cover 70; a silicone gel layer between the package outer frame and the first package bezel 30, between the package outer frame and the second package bezel 70, and between the package outer frame and the substrate 10. The package outer frame also covers the first electrode connector 601 and exposes the first main test electrode 602; the package outer frame also covers the third electrode connector 801, the fourth electrode connector 802 and the third additional electrode connector 804, and exposes the second test main electrode 803. In this embodiment, in the package structure, the first package frame cover 30 and the second package frame cover 70 are combined by using a package outer frame, so as to improve the insulation strength inside the package structure.
In this embodiment, by providing the gate lead-out portion 40, one end of the gate lead-out portion 40 and the gate 201 are sintered together, so that the contact resistance between the one end of the gate lead-out portion 40 and the gate 201 is reduced; secondly, the area of the test connection area for electrically connecting with the first test electrode assembly is larger than the area of the top surface of the grid 201, so that the first test electrode assembly and the grid lead-out part 40 are easier to sinter or weld together, and the problem that the larger first test electrode and the grid 201 are difficult to sinter due to direct sintering is avoided; and bonding wire leading-out on the grid 201 is avoided, so that parasitic inductance is reduced.
In this embodiment, the first package frame cover 30 is used to position the gate lead-out portion 40, so that the position between one end of the gate lead-out portion 40 and the gate 201 can be controlled well, and in the process of sintering the gate lead-out portion 40 and the gate 201, the extension portion (second lead-out portion) of the gate lead-out portion 40 is isolated from the high-voltage power semiconductor chip 20 by the first package frame cover 30, so that the gate lead-out portion 40 is not easily connected to the high-voltage power semiconductor chip 20 other than the gate 201.
Accordingly, the present embodiment further provides a packaging method for preparing the packaging structure of the high voltage power semiconductor chip, referring to fig. 6, including the following steps:
s1, providing a substrate 10, a high-voltage power semiconductor chip 20, a first packaging frame cover 30 and a grid lead-out part 40, wherein one side of the high-voltage power semiconductor chip 20 is provided with a grid 201, the first packaging frame cover 30 is provided with a first top plate 301, a grid reserved opening 302 is formed in the first top plate 301, and the top surface area of the grid lead-out part 40 is larger than that of the grid 201;
s2: fixedly connecting the high-voltage power semiconductor chip 20 to the substrate 10, wherein the gate 201 is opposite to the substrate 10;
s3, placing the first packaging frame cover 30 and the grid lead-out part 40 on the high-voltage power semiconductor chip 20, wherein the grid reserved opening 302 faces the grid 201, and one end of the grid lead-out part 40 is located in the grid reserved opening 302;
s4, after the first package frame cover 30 and the gate lead-out portion 40 are placed on the high voltage power semiconductor chip 20, one end of the gate lead-out portion 40 and the gate 201 are sintered together.
In this embodiment, specifically, an Ag plating layer is formed on the surface of the conductive adhesion layer of the substrate 10 by using a vacuum ion sputtering process, then the high-voltage power semiconductor chip 20 is welded or sintered on the substrate 10 through the Ag plating layer, and the additional power semiconductor chip 50 is welded or sintered on the substrate 10 through the Ag plating layer. In particular, a first collector electrode of the high voltage power semiconductor chip 20 and a second collector electrode of the additional power semiconductor chip 50 are electrically connected to said conductive adhesion layer.
In this embodiment, placing the first package frame cover 30 and the gate lead-out portion 40 on the high voltage power semiconductor chip 20 includes: placing the first package frame cover 30 on the high-voltage power semiconductor chip 20, with the gate reservation opening 302 facing the gate 201 and the opening of the additional slot 304 facing away from the high-voltage power semiconductor chip 20; the gate lead-out 40 is placed in the gate reserve hole 302 and the additional groove 304. In this embodiment, the first lead-out portion 401 is located in the gate reserved opening 302 and electrically connected to the gate 201, and the second lead-out portion 402 is located in the additional groove 304.
In this embodiment, the method further includes: providing a second package frame cover, and covering the second package frame cover on the additional power semiconductor chip.
In this embodiment, one end of the gate lead portion 40 and the gate electrode 201 are sintered together, and specifically, the first lead portion 401 and the gate electrode 201 are sintered together. Specifically, before the first package frame cover 30 is placed on the high-voltage power semiconductor chip 20, a gate sintered plating layer 204 is formed on the surface of the gate 201, and the process for forming the gate sintered plating layer 204 may be a vacuum ion sputtering process; the first lead portion 401 is sintered with the gate electrode 201 through the gate sintered plating layer 204.
In this embodiment, the method further includes: providing a first test electrode assembly 60; after one end of the gate lead-out portion 40 and the gate electrode 201 are sintered together, a first electrode connector 601 is placed on the first package frame cover 30 and covers the gate lead-out portion 40; the first electrode connector 601 and the gate lead-out portion are sintered 40 together or welded together.
In this embodiment, the method further includes: providing a second test electrode assembly 80; after one end of the gate lead-out portion 40 and the gate electrode 201 are sintered together, a third electrode connection 801 is placed in the first electrode groove 305, and a third additional electrode connection 804 is placed in the second electrode groove 703; the third electrode connection 801 and the first emitter are sintered or welded together by the first plating layer 203, and the third additional electrode connection 804 and the second emitter are sintered or welded together by the second plating layer.
In this embodiment, the method further includes: providing a packaging outer frame; placing a package outer frame on the side of the substrate 10, and on the substrate 10, the high voltage power semiconductor chip 20 and the first package frame cover 30, the package outer frame also being located on the additional power semiconductor chip 50 and the second package frame cover 70; a silicone gel layer is injected between the package outer frame and the first package bezel 30, between the package outer frame and the second package bezel 70, and between the package outer frame and the substrate 10; and then carrying out vacuum high-temperature curing on the silica gel layer.
The package outer frame also covers the first electrode connector 601 and exposes the first main test electrode 602; the package outer frame also covers the third electrode connector 801, the fourth electrode connector 802 and the third additional electrode connector 804, and exposes the second test main electrode 803. In this embodiment, in the package structure, the first package frame cover 30 and the second package frame cover 70 are combined by using a package outer frame, so as to improve the insulation strength inside the package structure.
Another embodiment of the present invention further provides a package structure, which is different from the package structure in the previous embodiment in that the structure of the first package frame cover in the present embodiment is different from that of the first package frame cover in the previous embodiment, the gate lead-out portion in the present embodiment is different from that in the previous embodiment, and the first test electrode assembly in the present embodiment is different from that in the previous embodiment. The same contents of this embodiment as those of the previous embodiment will not be described in detail.
The first package frame cover in this embodiment includes a first top plate, the first top plate has a gate reservation opening therein, the gate reservation opening is located in the first top plate with a partial thickness, and an opening of the gate reservation opening faces the high-voltage power semiconductor chip.
In this embodiment, the gate lead-out portion includes a spring probe and a conductive sheet connected to the spring probe, the spring probe is located in the gate reserved opening and electrically connected to the gate, and the conductive sheet is embedded in the first top plate.
The first top plate also has a gate connecting trench therein with a gate connecting trench located on the conductive sheet segment region. The exposed conducting strip of the gate connecting groove is used for forming a test connecting area.
In this embodiment, the gate sintered plating is located between the spring probe and the gate.
The first test electrode assembly comprises a first electrode connecting piece, a plurality of second electrode connecting pieces and a first main test electrode, wherein the second electrode connecting pieces are located in the grid connecting grooves and electrically connected with the conducting strips, the first electrode connecting pieces are located on the first packaging frame cover and respectively connected with the second electrode connecting pieces, and the first main test electrode is connected with the first electrode connecting pieces.
The first electrode connecting piece is of a rectangular annular structure, and the first main test electrode is connected with part of the inner ring side wall of the first electrode connecting piece.
Correspondingly, another embodiment of the invention also provides a packaging method. Placing the first package frame cover and the gate lead-out portion on the high voltage power semiconductor chip, including: and arranging a first packaging frame cover embedded with a grid lead-out part on the high-voltage power semiconductor chip, wherein the grid connecting groove faces away from the high-voltage power semiconductor chip.
Sintering one end of the gate lead-out part together with the gate, including: sintering the spring probe and the grid together. Specifically, the spring probe and the grid are sintered together through a grid sintering plating layer.
After sintering one end of the grid electrode leading-out part and the grid electrode together, placing the second electrode connecting piece in the grid connecting groove, wherein the first electrode connecting piece is positioned on the first packaging frame cover; and after the second electrode connecting piece is arranged in the grid connecting groove, sintering or welding the second electrode connecting piece and the conducting strip at the bottom of the grid connecting groove together.
The same parts of the packaging method of the present embodiment as those of the previous embodiment will not be described in detail.
Correspondingly, the invention also provides a packaging method, which comprises the following steps: providing a substrate, a high-voltage power semiconductor chip and a first packaging frame cover, wherein a grid is arranged on one surface of the high-voltage power semiconductor chip, the first packaging frame cover is provided with a first top plate, a grid reserved opening is formed in the first top plate, the grid reserved opening penetrates through the first top plate, an additional groove located in the thickness of part of the first top plate is further formed in the first top plate, and the additional groove is located on the side portion of the grid reserved opening and is communicated with the grid reserved opening; fixedly connecting the high-voltage power semiconductor chip to the substrate, wherein the grid electrode is opposite to the substrate; placing the first packaging frame cover on the high-voltage power semiconductor chip, wherein the reserved opening of the grid electrode faces towards the grid electrode, and the opening of the additional groove faces away from the high-voltage power semiconductor chip; and after the first packaging frame cover is arranged on the high-voltage power semiconductor chip, a grid leading-out part is formed in the grid reserved opening and the additional groove by adopting a deposition process or an electroplating process, and the grid leading-out part is contacted with the grid.
The same parts of the present packaging method as those of the packaging method described above will not be described in detail. The present packaging method is not suitable for a case where the gate lead-out portion includes a spring probe and a conductive sheet connected to the spring probe.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (26)
1. A package structure of a high-voltage power semiconductor chip is characterized by comprising:
a substrate;
the high-voltage power semiconductor chip is positioned on the substrate, and a grid electrode is arranged on one surface of the high-voltage power semiconductor chip, which is opposite to the substrate;
the first packaging frame cover covers the high-voltage power semiconductor chip, the first packaging frame cover is provided with a first top plate, and a grid electrode reserved opening is formed in the first top plate;
and one end of the grid electrode leading-out part is positioned in the grid electrode reserved opening and is electrically connected with the grid electrode.
2. The package structure of a high voltage power semiconductor chip according to claim 1, wherein the top surface area of the gate lead-out portion is larger than the top surface area of the gate.
3. The package structure of the high-voltage power semiconductor chip as claimed in claim 1, wherein the opening area of the gate opening is smaller than the top surface area of the gate.
4. The package structure of the high-voltage power semiconductor chip as claimed in claim 3, wherein the opening area of the gate opening is 0.8-0.9 times the area of the top surface of the gate.
5. The package structure of a high-voltage power semiconductor chip according to claim 2, wherein the top surface of the gate lead-out portion includes a test connection region having an area 2 to 8 times that of the top surface of the gate.
6. The package structure of the high-voltage power semiconductor chip as claimed in claim 2, wherein the gate opening is formed through the first top plate; the first top plate is also provided with an additional groove which is positioned in the thickness of the first top plate part, the opening of the additional groove faces away from the high-voltage power semiconductor chip, and the additional groove is positioned on the side part of the grid reserved opening and is communicated with the grid reserved opening; the grid lead-out part is also positioned in the additional groove.
7. The package structure of a high-voltage power semiconductor chip as claimed in claim 6, wherein the gate lead-out portion includes a first lead-out portion and a second lead-out portion, one end of the second lead-out portion is connected to one end of the first lead-out portion, the first lead-out portion and the second lead-out portion form an "L" shape, the first lead-out portion is located in the gate opening and electrically connected to the gate, and the second lead-out portion is located in the additional groove.
8. The package structure of a high voltage power semiconductor chip according to claim 6, further comprising: and the first test electrode assembly comprises a first electrode connecting piece and a first main test electrode connected with the first electrode connecting piece, and the first electrode connecting piece is positioned on the first packaging frame cover and is respectively electrically connected with the grid lead-out part.
9. The package structure of a high voltage power semiconductor chip according to claim 8, wherein the first electrode connection member covers an entire top surface of the gate lead-out portion.
10. The package structure of the high-voltage power semiconductor chip as claimed in claim 2, wherein the gate opening is located in a portion of the thickness of the first top board, and the gate opening is open towards the high-voltage power semiconductor chip;
the grid electrode leading-out part comprises a spring probe and a conducting strip connected with the spring probe, the spring probe is positioned in the grid electrode reserved opening and is electrically connected with the grid electrode, and the conducting strip is embedded in the first top plate;
the first top plate also has a gate connection trench therein on a region of the conductive sheet portion.
11. The package structure of a high voltage power semiconductor chip according to claim 10, further comprising: the first testing electrode assembly comprises a first electrode connecting piece, a plurality of second electrode connecting pieces and a first main testing electrode, wherein the second electrode connecting pieces are located in the grid connecting grooves and electrically connected with the conducting strips, the first electrode connecting piece is located on the first packaging frame cover and respectively connected with the second electrode connecting pieces, and the first main testing electrode is connected with the first electrode connecting piece.
12. The package structure of the high voltage power semiconductor chip as claimed in claim 8 or 11, wherein the first electrode connector has a rectangular ring structure, and the first main test electrode is connected to a portion of the inner ring sidewall of the first electrode connector.
13. The package structure of a high voltage power semiconductor chip according to claim 1, further comprising: and the grid sintering plating layer is positioned between one end of the grid lead-out part and the grid.
14. The package structure of the high voltage power semiconductor chip as claimed in claim 1, wherein a first emitter is further disposed on a side of the high voltage power semiconductor chip opposite to the substrate; a discrete first plating layer atop said first emitter portion;
the first top plate is also provided with a plurality of discrete first electrode grooves penetrating through the first top plate, and the first electrode grooves are positioned above the first plating layer and are discrete from the grid reserved openings.
15. The package structure of a high voltage power semiconductor chip according to claim 14, wherein the first plating layer has an elongated shape.
16. The package structure of a high voltage power semiconductor chip according to claim 14, further comprising: a second test electrode assembly, the second test electrode assembly comprising: third electrode connecting members respectively located in the first electrode grooves; a fourth electrode connecting member respectively connected to the third electrode connecting member and positioned on the first package frame cover; a second test main electrode connected to the fourth electrode connection.
17. The package structure of the high-voltage power semiconductor chip as claimed in claim 1, wherein the material of the first package bezel comprises polyimide or ceramic.
18. The package structure of the high-voltage power semiconductor chip as claimed in claim 1, wherein the substrate comprises a ceramic main substrate and a conductive adhesion layer on a surface of the ceramic main substrate; the high-voltage power semiconductor chip is electrically connected with the conductive adhesion layer.
19. The package structure of a high voltage power semiconductor chip according to claim 18, wherein the ceramic primary substrate has a thickness of 2mm to 3 mm.
20. The package structure of a high voltage power semiconductor chip according to claim 1, further comprising: the packaging outer frame is positioned on the side part of the substrate, the high-voltage power semiconductor chip and the first packaging frame cover; and the silicone gel layer is positioned between the packaging outer frame and the first packaging frame cover and between the packaging outer frame and the substrate.
21. A packaging method for preparing the packaging structure of the high-voltage power semiconductor chip according to any one of claims 1 to 20, comprising:
providing a substrate, a high-voltage power semiconductor chip, a first packaging frame cover and a grid lead-out part, wherein one surface of the high-voltage power semiconductor chip is provided with a grid, the first packaging frame cover is provided with a first top plate, and a grid reserved opening is formed in the first top plate;
fixedly connecting the high-voltage power semiconductor chip to the substrate, wherein the grid electrode is opposite to the substrate;
placing the first packaging frame cover and the grid electrode leading-out part on the high-voltage power semiconductor chip, wherein the grid electrode reserved opening faces to the grid electrode, and one end of the grid electrode leading-out part is positioned in the grid electrode reserved opening;
and after the first packaging frame cover and the grid electrode lead-out part are arranged on the high-voltage power semiconductor chip, one end of the grid electrode lead-out part and the grid electrode are sintered together.
22. The packaging method according to claim 21, wherein a top surface area of the gate lead-out portion is larger than a top surface area of the gate; the grid electrode reserved opening penetrates through the first top plate; the first top plate is also provided with an additional groove which is positioned in the thickness of the first top plate part, and the additional groove is positioned on the side part of the grid reserved opening and is communicated with the grid reserved opening;
placing the first package frame cover and the gate lead-out portion on the high voltage power semiconductor chip, including: placing the first package frame cover on the high-voltage power semiconductor chip, wherein an opening of the additional groove faces away from the high-voltage power semiconductor chip; and placing the grid lead-out part in the grid reserved opening and the additional groove.
23. The packaging method of claim 22, further comprising providing a first test electrode assembly comprising a first electrode connector and a first main test electrode connected to the first electrode connector; after sintering one end of the grid electrode lead-out part and the grid electrode together, placing the first electrode connecting piece on the first packaging frame cover and covering the grid electrode lead-out part; and sintering or welding the first electrode connecting piece and the grid electrode leading-out part together.
24. The packaging method according to claim 21, wherein a top surface area of the gate lead-out portion is larger than a top surface area of the gate; the grid electrode reserved opening is positioned in the first top plate with partial thickness, the grid electrode leading-out part comprises a spring probe and a conducting strip connected with the spring probe, the spring probe is positioned in the grid electrode reserved opening, the conducting strip is embedded in the first top plate, and a grid connecting groove positioned on a partial area of the conducting strip is further formed in the first top plate;
placing the first package frame cover and the gate lead-out portion on the high voltage power semiconductor chip, including: covering a first packaging frame embedded with a grid electrode lead-out part on the high-voltage power semiconductor chip, wherein the grid connecting groove faces away from the high-voltage power semiconductor chip;
sintering one end of the gate lead-out part together with the gate, including: sintering the spring probe and the grid together.
25. The packaging method according to claim 24, further comprising providing a first test electrode assembly comprising a first electrode connector, a plurality of second electrode connectors, and a first main test electrode, the first electrode connectors being connected to the second electrode connectors, respectively, the first main test electrode being connected to the first electrode connectors; after sintering one end of the grid electrode leading-out part and the grid electrode together, placing the second electrode connecting piece in the grid connecting groove, wherein the first electrode connecting piece is positioned on the first packaging frame cover; and after the second electrode connecting piece is arranged in the grid connecting groove, sintering or welding the second electrode connecting piece and the conducting strip at the bottom of the grid connecting groove together.
26. A packaging method for preparing the packaging structure of the high-voltage power semiconductor chip according to any one of claims 1 to 9 and 14 to 20, comprising:
providing a substrate, a high-voltage power semiconductor chip and a first packaging frame cover, wherein a grid is arranged on one surface of the high-voltage power semiconductor chip, the first packaging frame cover is provided with a first top plate, a grid reserved opening is formed in the first top plate, the grid reserved opening penetrates through the first top plate, an additional groove located in the thickness of part of the first top plate is further formed in the first top plate, and the additional groove is located on the side portion of the grid reserved opening and is communicated with the grid reserved opening;
fixedly connecting the high-voltage power semiconductor chip to the substrate, wherein the grid electrode is opposite to the substrate;
placing the first packaging frame cover on the high-voltage power semiconductor chip, wherein the reserved opening of the grid electrode faces towards the grid electrode, and the opening of the additional groove faces away from the high-voltage power semiconductor chip;
and after the first packaging frame cover is arranged on the high-voltage power semiconductor chip, a grid leading-out part is formed in the grid reserved opening and the additional groove by adopting a deposition process or an electroplating process, and the grid leading-out part is contacted with the grid.
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| CN112216670A (en) * | 2020-11-05 | 2021-01-12 | 全球能源互联网研究院有限公司 | Packaging structure and packaging method of high-voltage power semiconductor chip |
| CN112928090A (en) * | 2021-01-28 | 2021-06-08 | 全球能源互联网研究院有限公司 | Power semiconductor chip packaging structure, packaging method and packaging module |
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| CN212517200U (en) * | 2020-08-03 | 2021-02-09 | 全球能源互联网研究院有限公司 | Packaging structure of high-voltage power semiconductor chip |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112216670A (en) * | 2020-11-05 | 2021-01-12 | 全球能源互联网研究院有限公司 | Packaging structure and packaging method of high-voltage power semiconductor chip |
| CN112928090A (en) * | 2021-01-28 | 2021-06-08 | 全球能源互联网研究院有限公司 | Power semiconductor chip packaging structure, packaging method and packaging module |
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