CN111709162B - Thermal resistance distribution calculation method and device in power semiconductor module and storage medium - Google Patents
Thermal resistance distribution calculation method and device in power semiconductor module and storage medium Download PDFInfo
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Abstract
The invention discloses a method and a device for calculating thermal resistance distribution in a power semiconductor module, a storage medium and electronic equipment, wherein the method comprises the following steps: establishing a simulation model of the power semiconductor module; obtaining a first total thermal resistance simulation value corresponding to a simulation model of the power semiconductor module; the following steps are respectively executed for each material layer in the simulation model: introducing an adjustment coefficient k of a heat transfer coefficient to an i-th material layer of a power semiconductor module in a simulation model i Obtaining an adjustment coefficient k introduced into an ith material layer i An ith thermal resistance simulation value of the rear power semiconductor module; and calculating the thermal resistance ratio of the ith layer material layer in the power semiconductor module according to a formula, thereby obtaining the thermal resistance distribution in the power semiconductor module. The invention solves the problem of complex calculation process of the thermal resistance distribution of the power semiconductor module in the prior art, and the calculation error is reduced and the calculation efficiency is improved by establishing a finite element model and calculating the thermal resistance distribution by using a single variable method.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a method and a device for calculating thermal resistance distribution in a power semiconductor module, a storage medium and electronic equipment.
Background
The high-power electronic device is widely applied in various fields of national economy, particularly has important roles in the fields of rail transit, smart grids, electric automobiles, wind energy, solar energy and the like, and becomes a hot spot for research in the world academic circles and the industrial fields at present. With the continuous development and innovation of the power electronic technology, the power density, the application temperature, the voltage and the current of the power semiconductor module are higher and higher, and the thermal field inside the module is distributed more densely, so that the heat dissipation requirement on the module is also greatly improved.
Thermal analysis and management are key steps in power semiconductor module package design, and output characteristics, reliability and yield of the power semiconductor module can be accurately predicted only after strict thermodynamic analysis. For the power semiconductor module, the chip inside is a heat source, and after passing through the structural units such as the welding layer, the lining board, the substrate and the like, the heat is radiated out through the radiator. Along with the increasing of the power density, each unit in the module is subjected to accurate and comprehensive thermal analysis and management, so that the thermal cycling capability of the device can be effectively improved, and the reliability of the device is improved.
The extraction method of the thermal resistance and heat capacity distribution in the existing power semiconductor module is mainly completed by utilizing a structural function method, firstly, a transient temperature response curve of the power semiconductor module is obtained, logarithmic processing is carried out on the curve and differentiation is carried out, a local network thermal path model (Foster model, see figure 1) is built through deconvolution and discretization, then the local network thermal path model is converted into a continuous network thermal path model (Caser model, see figure 2), and a structural function curve of the power semiconductor module is obtained, so that the thermal resistance and heat capacity distribution in the module is obtained.
The prior art has the following main defects in the calculation process of the thermal resistance distribution:
1. by the method for obtaining the transient temperature response curve of the power semiconductor module by testing the voltage temperature coefficient of the power semiconductor module under small current and the step change of the internal dissipation power by the module, the actually measured data curve has certain error due to the temperature coefficient and the data acquisition of the test system, and the calculation process is complex by means of a complex test system.
2. In the power semiconductor module, a heat conduction path passes through multiple layers of heat transfer media, a network heat path model is established through a transient temperature response curve, the heat path model is transformed, the heat path model on each layer of material is obtained more complex, and the accuracy of the prior art is lower.
Disclosure of Invention
Therefore, the invention aims to solve the problem of complex calculation process of the thermal resistance distribution of the power semiconductor module in the prior art, thereby providing a thermal resistance distribution calculation method, a thermal resistance distribution calculation device, a storage medium and electronic equipment of the power semiconductor module.
In order to achieve the above object, the present invention provides the following solutions:
in a first aspect, an embodiment of the present invention provides a method for calculating a thermal resistance distribution in a power semiconductor module, including: establishing a simulation model of the power semiconductor module, wherein the power semiconductor module comprises a plurality of material layers; obtaining a first total thermal resistance simulation value corresponding to a simulation model of the power semiconductor module; the following steps are respectively executed on each material layer in the simulation model to obtain the thermal resistance ratio of each material layer in the power semiconductor module, and the thermal resistance distribution of the power semiconductor module is obtained: introducing an adjustment coefficient k of a heat transfer coefficient to an i-th material layer of the power semiconductor module in the simulation model i Obtaining an adjustment coefficient k introduced into an ith material layer i The ith thermal resistance simulation value of the power semiconductor module is introduced into the adjusting system for the ith material layerNumber k i A second total thermal resistance simulation value of the power semiconductor module is obtained, i is 1 to n, and n is the material layer number of the power semiconductor module; according to the adjustment coefficient k i And calculating the ith thermal resistance simulation value and the first total thermal resistance simulation value to obtain the thermal resistance ratio of the ith material layer in the power semiconductor module.
In an embodiment, the obtaining a first total thermal resistance simulation value corresponding to a simulation model of the power semiconductor module includes: acquiring the heat transfer area, thickness and heat transfer coefficient of each material layer in the simulation model; calculating the heat resistance of each material layer based on the heat transfer area, the thickness and the heat transfer coefficient of each material layer; and summing the calculated thermal resistances of all the material layers to obtain the first total thermal resistance simulation value.
In one embodiment, the adjustment coefficient k for introducing the heat transfer coefficient to the ith material layer of the power semiconductor module in the simulation model i Obtaining an adjustment coefficient k introduced into an ith material layer i The ith thermal resistance simulation value of the power semiconductor module is introduced into the ith material layer to adjust the coefficient k i And a second total thermal resistance simulation value of the power semiconductor module, i is 1 to n, n is the material layer number of the power semiconductor module, and the method comprises the following steps: adjustment coefficient k of heat transfer coefficient introduced into ith material layer i The heat transfer coefficient after the reaction is (1+k) i )λ i Wherein lambda is i Representing the heat transfer coefficient of the i-th material layer.
In one embodiment, the adjustment coefficient 0 < k i ≤5％。
In one embodiment, the thermal resistance ratio of the ith material layer in the power semiconductor module is calculated by the following formula:
wherein Z is i Representing the thermal resistance duty ratio, k of the ith material layer in the power semiconductor module i The adjustment coefficient is represented by a value representing the adjustment coefficient,R th (j-c) i represents the ith thermal resistance simulation value, R th (j-c) represents the first total thermal resistance simulation value.
In a second aspect, an embodiment of the present invention provides a thermal resistance distribution calculating apparatus in a power semiconductor module, including a building module, configured to build a simulation model of the power semiconductor module, where the power semiconductor module includes multiple material layers; the acquisition module is used for acquiring a first total thermal resistance simulation value corresponding to the simulation model of the power semiconductor module; the calculation module is used for respectively executing the following steps on each material layer in the simulation model to obtain the thermal resistance ratio of each material layer in the power semiconductor module and obtain the thermal resistance distribution of the power semiconductor module: introducing an adjustment coefficient k of a heat transfer coefficient to an i-th material layer of the power semiconductor module in the simulation model i Obtaining an adjustment coefficient k introduced into an ith material layer i The ith thermal resistance simulation value of the power semiconductor module is introduced into the ith material layer to adjust the coefficient k i A second total thermal resistance simulation value of the power semiconductor module is obtained, i is 1 to n, and n is the material layer number of the power semiconductor module; according to the adjustment coefficient k i And calculating the ith thermal resistance simulation value and the first total thermal resistance simulation value to obtain the thermal resistance ratio of the ith material layer in the power semiconductor module.
In a third aspect, an embodiment of the present invention provides an electronic device, including: the device comprises at least one processor and a memory communicatively connected with the at least one processor, wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the thermal resistance distribution calculation method of the first aspect of the embodiment of the present invention.
In a fourth aspect, embodiments of the present invention provide a computer-readable storage medium storing computer instructions for causing a computer to execute the thermal resistance distribution calculation method of the first aspect of the embodiments of the present invention.
The technical scheme of the invention has the following advantages:
1. by establishing a simulation model of the power semiconductor module, the total thermal resistance (namely, a first total thermal resistance simulation value) of the power semiconductor module can be calculated by the simulation model, then the adjustment coefficients of the heat transfer coefficients are respectively introduced into each material layer in the simulation model to reduce calculation errors, the total thermal resistance (namely, a second total thermal resistance simulation value) of the power semiconductor with the adjustment coefficients introduced is calculated, and then the total thermal resistance of the power semiconductor is calculated according to the adjustment coefficients k i And calculating the ith thermal resistance simulation value and the first total thermal resistance simulation value to obtain the thermal resistance ratio of the ith material layer in the power semiconductor module, thereby obtaining the thermal resistance distribution of the power semiconductor module. The complex test system is not needed, a large number of differential and integral calculation and thermal path model transformation calculation are reduced, the overall thermal resistance distribution condition of the module is obtained through a single variable method, and the calculation process is concise and clear.
2. According to the calculation method and the calculation system for the thermal resistance distribution in the power semiconductor module, provided by the invention, the simulation model of the power semiconductor module is established based on the heat transverse conduction theory by utilizing the material characteristics of the heat transfer medium in the module, so that the transient temperature response curve of the power semiconductor module commonly used in the prior art is abandoned, the use of more complex test equipment is avoided, and no additional test error is required to be introduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art local network hot-path model (Foster model);
FIG. 2 is a schematic diagram of a prior art continuous network hot-path model (Cauer model);
FIG. 3 is a flowchart of a method for calculating thermal resistance distribution of a power semiconductor module according to an embodiment of the present invention;
FIG. 4 is a schematic illustration of actual heat transfer processes in different heat transfer mediums in an embodiment of the invention;
FIG. 5 is a schematic illustration of equivalent heat transfer processes in different heat transfer mediums in an embodiment of the invention;
FIG. 6 is a schematic diagram illustrating a heat transfer process of heat generated when various heat transfer mediums dissipate heat according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a heat conduction process at multiple heat sources in an embodiment of the invention;
FIG. 8 is a flow chart of a method for obtaining a first total thermal resistance simulation value in an embodiment of the invention;
FIG. 9 is a schematic diagram of a thermal resistance distribution calculating device of a power semiconductor module according to an embodiment of the present invention;
fig. 10 is a composition diagram of a specific example of an electronic device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
Example 1
The embodiment of the invention provides a thermal resistance distribution calculation method for a power semiconductor module, which is used for calculating thermal resistance distribution of the power semiconductor module, and particularly can be used for calculating thermal resistance duty ratio of each material layer in the power semiconductor module. As shown in fig. 3, the method comprises the steps of:
step S101, establishing a simulation model of the power semiconductor module, where the power semiconductor module includes multiple material layers.
The simulation model may be a finite element model, built based on the theory of lateral conduction of heat in the power semiconductor module. The power semiconductor module may be an IGBT device, a thyristor, or the like, and the present invention is not limited thereto. The power semiconductor is generally composed of multiple layers of materials, and the materials of different layers can be the same or different; the heat transfer coefficients of the different layers can be the same or different; the size and thickness of the different layers may be the same or different.
The heat conduction process in the power semiconductor module can be described by the theory of lateral heat conduction, and during the heat transfer process of the power semiconductor module, there is a process of conducting the heat flow of the heat source from one limited surface to another heat conductor with a larger area, as shown in fig. 4, at this time, the heat energy is transmitted in a three-dimensional cross manner in the heat conductor, that is, the heat can be conducted not only vertically but also laterally, and when the heat is diffused, the section of the heat path is increased continuously. Since the diffusion process of heat is relatively complicated, the complicated process of heat diffusion is simplified to a simple section by introducing the heat diffusion angle α, as shown in fig. 5.
Step S102, a first total thermal resistance simulation value corresponding to a simulation model of the power semiconductor module is obtained.
In the embodiment of the invention, after the simulation model of the power semiconductor module is established, the heat transfer area, thickness and heat transfer coefficient of each material layer can be obtained through simulation data, so that the thermal resistance of each layer can be obtained through calculation by utilizing a thermal resistance formula, and the total thermal resistance simulation value of the power semiconductor module of the simulation model is obtained. Specifically, the obtained heat transfer area, thickness and heat transfer coefficient can be used to calculate the thermal resistance of each material layer, and then the first total thermal resistance simulation value R corresponding to the simulation model is calculated th (j-c). In general, when the heat transfer areas are the same, the formula can be directly used
Obtaining the thermal resistance of the material layer, wherein lambda is the heat transfer coefficient, d is the thickness of the current material layer, and A is the heat transfer area; when the heat transfer areas are different, the thermal diffusion angle of the current material layer is obtained through a simulation model, the increased heat transfer area of the current material layer relative to the previous material layer of the current material layer is calculated by utilizing the diffusion angle and the thickness of the current material layer, the heat transfer area of the current material layer is calculated by utilizing the heat transfer area of the previous material layer and the increased heat transfer area, and then the heat transfer area of the current material layer is calculated according to the formula->
And obtaining the thermal resistance of the current material layer, and summing the calculated thermal resistances of all the material layers to obtain a first total thermal resistance simulation value.
It should be noted that, when the heat transfer areas are different in practical application, the heat transfer area of the current material layer may be calculated by summing the area of the previous material layer and the area of the current material layer increased relative to the previous material layer, or by adding the length and width of the previous material layer to the length increased after heat diffusion, then calculating the heat transfer area of the current material layer, and calculating the thermal resistance of each layer by using the calculated heat transfer area and the formula, thereby obtaining a total thermal resistance simulation value, and in practical application, the present invention may be set according to the practical requirements of the system, but the present invention is not limited thereto.
Step S103, introducing an adjustment coefficient k of heat transfer coefficient to the ith material layer of the power semiconductor module in a simulation model i 。
Embodiments of the present invention adjust the coefficient k i As a single variable, the adjustment coefficient is used to adjust the heat transfer coefficient during the heat transfer process to reduce errors during the calculation process. The adjustment coefficient k introduced by each layer i The specific values of the two can be the same or different, and can be adjusted or set according to the needs or according to statistical results or experience.
As an alternative implementation manner, in the embodiment of the present invention, the adjustment coefficient k of the ith layer i The number value range of (2) is 0 < k i ≤5％，k i The value of which is small enough to introduce the k i The value of (2) can reduce the error in calculation of the thermal resistance while having a negligible effect on the thermal diffusion angle α. According to the embodiment of the invention, the error in the equivalent calculation process is fully reduced by setting the extremely small adjustment coefficient.
As a further alternative embodiment, in the embodiment of the present invention, the introduced single variable, i.e. the adjustment coefficient, is the adjustment of the heat transfer coefficient, e.g. the i-th material layer introduces the adjustment coefficient k of the heat transfer coefficient i The heat transfer coefficient after the reaction is (1+k) i )λ i Wherein lambda is i Representing the heat transfer coefficient of the i-th material layer.
Of course, in the embodiment of the present invention, the coefficient k is adjusted i May also be the overall coefficient of heat transfer coefficient, e.g. incorporating the adjustment coefficient k of heat transfer coefficient i The heat transfer coefficient after the reaction is k i λ i Wherein k is i The value of (2) is slightly greater than 1.
Step S104, obtaining an adjustment coefficient k introduced into the ith material layer i Ith thermal resistance simulation value, ith thermal resistance simulation value of rear power semiconductor moduleIntroducing an adjustment coefficient k for the ith material layer i And a second total thermal resistance simulation value of the rear power semiconductor module, i is 1 to n, and n is the material layer number of the power semiconductor module.
The main difference between the second total thermal resistance simulation value and the first total thermal resistance simulation value is that a single variable (adjustment coefficient k i ) The resulting differences then represent themselves also the total thermal resistance of the power semiconductor module in the simulation model. In the embodiment of the invention, corresponding adjustment coefficients are respectively introduced into each material layer, and the total thermal resistance after introduction is obtained and is used for subsequent thermal resistance duty ratio calculation.
Step S105, according to the adjustment coefficient k i And calculating the ith thermal resistance simulation value and the first total thermal resistance simulation value to obtain the thermal resistance duty ratio of the ith material layer in the power semiconductor module. The thermal resistance duty ratio of the current material layer can be calculated by using a preset calculation formula or a calculation formula which is obtained by deduction in advance. The calculation formula is used for expressing the mathematical relationship between the thermal resistance ratio and the adjustment coefficient of each layer and the total thermal resistance before and after the adjustment coefficient is correspondingly introduced.
After the thermal resistance duty ratio of the ith material layer in the power semiconductor module is calculated, judging whether i is equal to n, if so, executing step S106; otherwise, the value of i is increased by 1, and steps S103 to S105 are re-executed.
Step S106, obtaining a thermal resistance distribution in the power semiconductor module.
In the embodiment of the invention, the steps S103-S105 are respectively executed for each material layer in the simulation model to obtain the thermal resistance ratio of each material layer in the power semiconductor module, and finally the thermal resistance distribution of the power semiconductor module is obtained.
According to the embodiment of the invention, by establishing the simulation model of the power semiconductor module, the total thermal resistance (namely, the first total thermal resistance simulation value) of the power semiconductor module can be calculated by the simulation model because the simulation data in the simulation model can be obtained, then the adjustment coefficients of the heat transfer coefficients are respectively introduced into each material layer in the simulation model to reduce the calculation errors, and the power semiconductor with the introduced adjustment coefficients is calculatedTotal thermal resistance (i.e. second total thermal resistance simulation value), and according to the adjustment coefficient k i And calculating the ith thermal resistance simulation value and the first total thermal resistance simulation value to obtain the thermal resistance ratio of the ith material layer in the power semiconductor module, thereby obtaining the thermal resistance distribution of the power semiconductor module. The complex test system is not needed, a large number of differential and integral calculation and thermal path model transformation calculation are reduced, the overall thermal resistance distribution condition of the module is obtained through a single variable method, and the calculation process is concise and clear.
In the embodiment of the invention, by establishing the finite element model, the calculation is performed by utilizing the material characteristics of the heat transfer medium in the module without introducing additional test errors by means of complex test equipment, the transient temperature response curve of the power semiconductor module required in the traditional calculation process is set aside, and the error of the calculation result is greatly reduced.
As an alternative implementation manner, in the embodiment of the present invention, the thermal resistance ratio of the ith layer of material layer may be calculated by using the following formula:
wherein k is i For the adjustment coefficient of the ith layer, R th (j-c) i Introducing an adjustment coefficient k for an ith material layer i A second total thermal resistance simulation value, R, of the power semiconductor module th (j-c) represents the first total thermal resistance simulation value.
In the embodiment of the present invention, the above formula (1) may be derived by introducing an adjustment coefficient into a certain material layer in the power semiconductor module, deriving by taking the adjusted heat transfer coefficient (1+k) λ as an example, and introducing the adjustment coefficient to obtain the thermal resistance R of the layer t ' h Can be expressed as
The method can obtain:
wherein R is th Representing the thermal resistance of the layer prior to introduction. When no adjustment coefficient is introduced, the total thermal resistance R of the power semiconductor module (n layers in total) th (j-c), i.e. the sum of the thermal resistances of the layers of material, i.e.:
R th (j-c)＝R th1 +R th2 +…R thn (4)
taking the introduction of adjustment coefficients in the first layer as example k 1 By introducing the variable k into the target material 1 Lambda is substituted into the formula to obtain the total thermal resistance R of the first layer after the adjustment coefficient is introduced th (j-c) 1 ：
After the difference between the formula (4) and the formula (5), it can be obtained that:
that is, the thermal resistance of the first layer is:
and so on to obtain the above formula (1).
As an optional implementation manner, in the embodiment of the present invention, in step S102, the obtaining a first total thermal resistance simulation value corresponding to the simulation model of the power semiconductor module may include:
s1021, obtaining the heat transfer area, thickness and heat transfer coefficient of each material layer in the simulation model.
And S1022, calculating the thermal resistance of each material layer based on the heat transfer area, the thickness and the heat transfer coefficient of each material layer.
As an alternative embodiment, the thermal resistance of each material layer may be calculated using the following formula:
wherein lambda is the heat transfer coefficient, d is the current material layer thickness, A is the heat transfer area, R th Representing the thermal resistance of each layer of material. The heat transfer coefficient lambda is only material dependent under stable heat transfer conditions.
S1023, summing the calculated thermal resistances of all the material layers to obtain the first total thermal resistance simulation value.
In the embodiment of the present invention, when the sizes of the two layers are the same, that is, the contact surface is the same as the heat transfer area, the heat transfer area a may be calculated by using the contact area, and when the heat transfer area of each layer is different, the obtaining the heat transfer area of each material layer in the simulation model includes: acquiring the thermal diffusion angle and the thickness of the current material layer; calculating the increased heat transfer area of the current material layer relative to the previous material layer of the current material layer by using the thermal diffusion angle and the thickness of the current material layer; and calculating the heat transfer area of the current material layer by using the heat transfer area of the previous material layer plus the increased heat transfer area.
Specifically, according to the theory of heat conduction, the calculation formula of thermal resistance can be expressed as: considering the heat dissipation of the multi-layer materials, the thermal diffusion angle α of each layer is different, and the thermal conduction model is shown in FIG. 6, the thermal resistance R of the first layer th1 And a thermal resistance R of the second layer th2 Can be expressed as:
where l is the length of the heat transfer area, w is the width of the heat transfer area, and α is the thermal diffusion angle. Wherein, (l+2d) 1 ×tanα 1 )×(w+2d 1 ×tanα 1 ) Represents the heat transfer area between the first layer and the second layer, (l+2d) 1 ×tanα 1 +2d 2 ×tanα 2 )×(w+2d 1 ×tanα 1 +2d 2 ×tanα 2 ) Representing the heat transfer area between the second layer and the third layer. In the actual power semiconductor module, there is a further process of conducting and dissipating heat from a plurality of heat sources in a plurality of heat-conducting media, as shown in fig. 7, in which an equivalent heat-transfer area a is used 2 And (5) performing calculation.
Example 2
The embodiment of the present invention also provides a device for calculating a thermal resistance distribution in a power semiconductor module, which may be used to perform the method for calculating a thermal resistance distribution in a power semiconductor module described in the above embodiment 1, as shown in fig. 9, and includes:
a building module 901, configured to build a simulation model of the power semiconductor module, where the power semiconductor module includes multiple material layers;
the obtaining module 902 is configured to obtain a first total thermal resistance simulation value corresponding to a simulation model of the power semiconductor module;
the calculating module 903 is configured to perform the following steps on each material layer in the simulation model, so as to obtain a thermal resistance ratio of each material layer in the power semiconductor module, and obtain a thermal resistance distribution of the power semiconductor module:
introducing an adjustment coefficient k of a heat transfer coefficient to an i-th material layer of the power semiconductor module in the simulation model i Obtaining an adjustment coefficient k introduced into an ith material layer i The ith thermal resistance simulation value of the power semiconductor module is introduced into the ith material layer to adjust the coefficient k i A second total thermal resistance simulation value of the power semiconductor module is obtained, i is 1 to n, and n is the material layer number of the power semiconductor module;
according to the heat transfer coefficient lambda i The saidAnd calculating the ith thermal resistance simulation value and the first total thermal resistance simulation value to obtain the thermal resistance ratio of the ith material layer in the power semiconductor module.
According to the embodiment of the invention, by establishing the simulation model of the power semiconductor module, the total thermal resistance (namely, the first total thermal resistance simulation value) of the power semiconductor module can be calculated by the simulation model because the simulation data in the simulation model can be obtained, then the adjustment coefficients of the heat transfer coefficients are respectively introduced into each material layer in the simulation model to reduce calculation errors, the total thermal resistance (namely, the second total thermal resistance simulation value) of the power semiconductor with the adjustment coefficients introduced is calculated, and then the total thermal resistance of the power semiconductor with the adjustment coefficients introduced is calculated according to the adjustment coefficient k i And calculating the ith thermal resistance simulation value and the first total thermal resistance simulation value to obtain the thermal resistance ratio of the ith material layer in the power semiconductor module, thereby obtaining the thermal resistance distribution of the power semiconductor module. The complex test system is not needed, a large number of differential, integral and thermal path model transformation calculations are reduced, the overall thermal resistance distribution condition of the power semiconductor module is obtained through a single variable method, and the calculation process is brief and clear.
For a specific description of the device portion, reference may be made to the above method embodiments, which are not repeated here.
Example 3
An embodiment of the present invention provides an electronic device, as shown in fig. 10, including: at least one processor 401, such as a CPU (central processing unit), at least one communication interface 403, a memory 404, at least one communication bus 402. Wherein communication bus 402 is used to enable connected communications between these components. The communication interface 403 may include a Display screen (Display) and a Keyboard (Keyboard), and the optional communication interface 403 may further include a standard wired interface and a wireless interface. The memory 404 may be a high-speed RAM memory (Ram dom Access Memory, volatile random access memory) or a non-volatile memory (non-volatile memory), such as at least one disk memory. The memory 404 may also optionally be at least one storage device located remotely from the aforementioned processor 401. Wherein the processor 401 may perform the thermal resistance distribution calculating method in the power semiconductor module of embodiment 1. A set of program codes is stored in the memory 404, and the processor 401 calls the program codes stored in the memory 404 for executing the thermal resistance distribution calculation method in the power semiconductor module of embodiment 1.
The communication bus 402 may be a peripheral component interconnect standard (peripheral component interconnect, PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus, among others. Communication bus 402 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one line is shown in fig. 10, but not only one bus or one type of bus.
Wherein the memory 404 may include volatile memory (English) such as random-access memory (RAM); the memory may also include a nonvolatile memory (english: non-volatile memory), such as a flash memory (english: flash memory), a hard disk (english: hard disk drive, abbreviated as HDD) or a solid-state drive (english: SSD); memory 404 may also include a combination of the above types of memory.
The processor 401 may be a central processor (English: central processing unit, abbreviated: CPU), a network processor (English: network processor, abbreviated: NP) or a combination of CPU and NP.
Wherein the processor 401 may further comprise a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof (English: programmable logic device). The PLD may be a complex programmable logic device (English: complex programmable logic device, abbreviated: CPLD), a field programmable gate array (English: field-programmable gate array, abbreviated: FPGA), a general-purpose array logic (English: generic array logic, abbreviated: GAL), or any combination thereof.
Optionally, the memory 404 is also used for storing program instructions. The processor 401 may call program instructions to implement the thermal resistance distribution calculation method in the power semiconductor module as in embodiment 1 to be executed in the present application.
The embodiment of the invention also provides a computer readable storage medium, and the computer readable storage medium stores computer executable instructions thereon, wherein the computer executable instructions can execute the thermal resistance distribution calculation method in the power semiconductor module of the embodiment 1. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a Flash Memory (Flash Memory), a Hard Disk (HDD), or a Solid-State Drive (SSD); the storage medium may also comprise a combination of memories of the kind described above.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present invention.
Claims (10)
1. The method for calculating the thermal resistance distribution in the power semiconductor module is characterized by comprising the following steps of:
establishing a simulation model of the power semiconductor module, wherein the power semiconductor module comprises a plurality of material layers;
obtaining a first total thermal resistance simulation value corresponding to a simulation model of the power semiconductor module;
the following steps are respectively executed on each material layer in the simulation model to obtain the thermal resistance ratio of each material layer in the power semiconductor module, and the thermal resistance distribution of the power semiconductor module is obtained:
introducing an adjustment coefficient k of a heat transfer coefficient to an i-th material layer of the power semiconductor module in the simulation model i Obtaining an adjustment coefficient k introduced into an ith material layer i Ith thermal resistance simulation value of the power semiconductor moduleThe ith thermal resistance simulation value introduces an adjustment coefficient k for the ith material layer i A second total thermal resistance simulation value of the power semiconductor module is obtained, i is 1 to n, and n is the material layer number of the power semiconductor module;
according to the adjustment coefficient k i And calculating the ith thermal resistance simulation value and the first total thermal resistance simulation value to obtain the thermal resistance ratio of the ith material layer in the power semiconductor module.
2. The method of claim 1, wherein the thermal resistance duty cycle is calculated by the formula:
wherein Z is i Representing the thermal resistance duty ratio, k of the ith material layer in the power semiconductor module i Representing the adjustment coefficient, R th (j-c) i Represents the ith thermal resistance simulation value, R th (j-c) represents the first total thermal resistance simulation value.
3. The method according to claim 1, wherein 0 < k i ≤5％。
4. The method of claim 1, wherein the layer of the ith material introduces a coefficient of adjustment k for the heat transfer coefficient i The heat transfer coefficient after the reaction is (1+k) i )λ i Wherein lambda is i Representing the heat transfer coefficient of the i-th material layer.
5. The method of claim 1, wherein the obtaining a first total thermal resistance simulation value corresponding to a simulation model of the power semiconductor module comprises:
acquiring the heat transfer area, thickness and heat transfer coefficient of each material layer in the simulation model;
calculating the heat resistance of each material layer based on the heat transfer area, the thickness and the heat transfer coefficient of each material layer;
and summing the calculated thermal resistances of all the material layers to obtain the first total thermal resistance simulation value.
6. The method of claim 5, wherein the thermal resistance of each material layer is calculated by the formula:
wherein R is th Representing the thermal resistance of each material layer, d representing the thickness of the material layer, lambda representing the heat transfer coefficient of the material layer, and A representing the heat transfer area of the material layer.
7. The method of claim 5, wherein when the heat transfer area of each layer is different, the obtaining the heat transfer area of each material layer in the simulation model comprises:
acquiring the thermal diffusion angle and the thickness of the current material layer;
calculating the increased heat transfer area of the current material layer relative to the previous material layer of the current material layer by using the thermal diffusion angle and the thickness of the current material layer;
and calculating the heat transfer area of the current material layer by using the heat transfer area of the previous material layer plus the increased heat transfer area.
8. A thermal resistance distribution calculating apparatus in a power semiconductor module, comprising:
the power semiconductor module comprises a building module and a power semiconductor module, wherein the building module is used for building a simulation model of the power semiconductor module, and the power semiconductor module comprises a plurality of material layers;
the acquisition module is used for acquiring a first total thermal resistance simulation value corresponding to the simulation model of the power semiconductor module;
the calculation module is used for respectively executing the following steps on each material layer in the simulation model to obtain the thermal resistance ratio of each material layer in the power semiconductor module and obtain the thermal resistance distribution of the power semiconductor module:
introducing an adjustment coefficient k of a heat transfer coefficient to an i-th material layer of the power semiconductor module in the simulation model i Obtaining an adjustment coefficient k introduced into an ith material layer i The ith thermal resistance simulation value of the power semiconductor module is introduced into the ith material layer to adjust the coefficient k i A second total thermal resistance simulation value of the power semiconductor module is obtained, i is 1 to n, and n is the material layer number of the power semiconductor module;
according to the heat transfer coefficient lambda i And calculating the ith thermal resistance simulation value and the first total thermal resistance simulation value to obtain the thermal resistance ratio of the ith material layer in the power semiconductor module.
9. A computer readable storage medium storing computer instructions which, when executed by a processor, implement the thermal resistance distribution calculation method in a power semiconductor module according to any one of claims 1 to 7.
10. An electronic device, comprising:
a memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the thermal resistance distribution calculation method in the power semiconductor module according to any one of claims 1-7.
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