CN115186556A

CN115186556A - Thermal impedance model modeling and junction temperature estimation method, computer device and storage medium

Info

Publication number: CN115186556A
Application number: CN202210845325.4A
Authority: CN
Inventors: 杨鑫; 衡可; 武新龙; 欧阳晓平
Original assignee: Changsha Semiconductor Technology And Application Innovation Research Institute; Hunan University
Current assignee: Changsha Semiconductor Technology And Application Innovation Research Institute; Hunan University
Priority date: 2022-07-19
Filing date: 2022-07-19
Publication date: 2022-10-14

Abstract

The invention provides a thermal impedance model modeling and junction temperature estimation method, computer equipment and a storage medium. The power module thermal impedance model modeling method comprises the following steps: establishing a finite element thermal simulation model of the power module; obtaining HA multiplied by PA first summation values according to a simulation result of the finite element thermal simulation model; obtaining HA multiplied by PA coordinate points in an oxyz coordinate system, thereby obtaining a three-dimensional curved surface; mapping the three-dimensional curved surface to an o1x1y1 coordinate system to obtain a first mapping result and form an NA connecting line; taking an nth characteristic coordinate point on an nth sub-line segment obtained by dividing the first virtual line segment; a thermal impedance model of the power module is established.

Description

Thermal impedance model modeling and junction temperature estimation method, computer device and storage medium

Technical Field

The invention belongs to the field of power electronic devices, and particularly relates to a rapid robust power module thermal impedance model modeling method considering material temperature characteristics.

Background

The power module is widely applied to the fields of rail transit, new energy power generation, locomotive traction systems and the like. In the prior art, a power module package structure located in a power module housing sequentially includes, from top to bottom (in a height direction of a power module), a 1 st layer structure, a 2 nd layer structure, \8230 \ 8230 \ 7 th layer structure, and the 1 st layer structure, the 2 nd layer structure, \\ 8230 \ 7 \ 7 th layer structure and the 7 th layer structure respectively correspond to a layer L1 where a chip is located, a chip solder layer L2, an upper copper layer L3, a ceramic layer L4, a lower copper layer L5, a substrate solder layer L6 and a substrate layer L7. Heat is generated by the power module chip active area (i.e., chip layer, e.g., 7.5mm long by 7.5mm high by 0.15mm in size), propagates through the solder layer, the DBC layer (Direct Bond coater), and the heat dissipating substrate layer L7, and finally reaches the external cooling system (heat sink). The DBC includes an upper copper layer L3, a ceramic layer L4, and a lower copper layer L5. Substrate solder layer L6 is also referred to as a lower solder layer, DBC solder layer. The substrate layer 7 serves to fix the power module to the heat sink, and serves a heat conduction function. I.e. the cooling device in direct contact with the substrate layer L7. The radiator can be an air-cooled radiator or a water-cooled radiator. The bottom end, four sidewalls of the substrate layer L7 are all disposed towards the outside of the power module (i.e. directly towards the environment outside the power module).

Power density levels of power modules are increasing due to cost considerations. However, due to the additional increased power, the module is subject to greater temperature fluctuations and the risk of failure becomes more severe. Therefore, it is important to accurately monitor junction temperature information of the device for thermal management and reliability evaluation of the power module.

The traditional invasive junction temperature measurement means such as an infrared camera, a thermocouple, optical fiber temperature measurement and the like need to open module packaging, are complex to operate and are easy to damage a power module.

And the thermal impedance network model (or called thermal impedance model) is widely applied to the field of power module junction temperature monitoring due to the remarkable characteristics of concise expression and high calculation speed. The research of the thermal impedance network model is characterized in that a heat transfer path of a power module is equivalent to a one-dimensional heat transfer path, a heat circuit is similar to a circuit, R represents a thermal resistance (similar to a resistance in the circuit), C represents a thermal capacitance (similar to a capacitance in the circuit), and finally an RC thermal equivalent circuit model is formed. Each node in the thermal impedance model corresponds to a set measurement position of each layer in the actual 7-layer packaging structure, so that the temperature of the corresponding set measurement position can be obtained according to the temperature of the node in the thermal impedance model.

In the modeling of the thermal impedance model of the power module, the thermal resistance and the thermal capacity need to be calculated according to the effective heat transfer area, while the effective heat transfer area of each layer is generally calculated by adopting a thermal diffusion angle model in the prior art, but the accuracy of the existing thermal diffusion angle model is poor, so that the calculation accuracy of the thermal resistance and the thermal capacity in the calculated thermal impedance model is poor, and the estimation error of the thermal impedance model on the junction temperature is large.

In order to improve the junction temperature estimation precision of the thermal impedance model, a transient finite element simulation result is also researched and combined, namely, the temperature corresponding to each node in the thermal impedance model (namely, the temperature of each layer of set measurement position) is obtained in the finite element thermal simulation model, and after a dynamic temperature curve of each node is obtained, thermal resistance and thermal capacity parameters in the thermal impedance model are correspondingly identified, so that the thermal impedance model is utilized to carry out subsequent junction temperature estimation. However, in the above method, the transient temperature response curve of the node needs to be determined by using transient finite element simulation, so that the thermal resistance and thermal capacity corresponding to each layer of structure are identified, which results in long time consumption and low efficiency, and the junction temperature estimation requirement of the power module cannot be met.

Disclosure of Invention

The invention provides a power module thermal impedance model modeling method aiming at the problems that the precision of an effective heat transfer area which needs to be calculated by a thermal diffusion angle model in the existing thermal impedance model is low, the time consumption of thermal resistance and thermal capacity parameters in the thermal impedance model is long and the efficiency is low by utilizing a transient finite element simulation result.

The technical problem to be solved by the invention is realized by the following technical scheme: a power module thermal impedance model modeling method includes the following steps:

step 1: establishing a finite element thermal simulation model of the power module according to the material and size parameters of a 7-layer packaging structure of the power module, wherein the 1 st layer structure, the 2 nd layer structure, the 8230, the 7 th layer structure of the 7-layer packaging structure are respectively a layer where a chip is located, a chip solder layer, an upper copper layer, a ceramic layer, a lower copper layer, a substrate solder layer and a substrate layer;

step 2: let HA value htc (1), htc (2), \8230;, one value in Htc (HA) and PA value P _Loss (1)、P _Loss (2)、……、P _Loss (PA) one value of which constitutes a set of parameters, thus obtaining a HA x PA set of parameters, said HA value being a predetermined range of convective heat dissipation coefficients from the bottom of the power module [ htc (1), htc (HA) ]]The value of PA is the preset range [ P ] of the power loss of the slave chip _Loss (1),P _Loss (PA)]Sequentially increasing the values selected in the table;

respectively applying the HA multiplied by PA group parameters to the finite element thermal simulation model, taking the set value of the environment temperature as the environment temperature applied to the finite element thermal simulation model, and according to the simulation result of the finite element thermal simulation model and the K _i,TA To obtain HA × PA first summation values R _jc(1) 、R _jc(2) 、……、R _jc(HA×PA) In which

Wherein m =1,2, \ 8230;, HA x PA, K _1,TA 、K _2,TA 、……、K _7,TA Respectively indicate the thermal conductivity of the materials of the 1 st layer structure, the 2 nd layer structure, the 8230, the 7 th layer structure and d ₁ 、d ₂ 、……、d ₇ The thickness of the layer 1 structure, the layer 2 structure, \8230 \8230andthe layer 7 structure respectively; t1 _m 、T2 _m Respectively after applying the mth group of parameters to the thermal simulation model of the finite elementThe obtained temperature of the set measuring positions of the 1 st layer structure and the 2 nd layer structure is on a first straight line parallel to the height direction of the power module, and K (T1) _m ) Is expressed with a temperature T1 _m Corresponding thermal conductivity of the material of the layer 1 structure, A _solder1 Is the surface area of the 2 nd layer structure, P _Loss(m) For the power loss of the chip in the m-th set of parameters, q _m (i, z) is the heat flow density of a position which is obtained by applying the mth group of parameters to the finite element thermal simulation model, has a height direction distance z from the upper end surface of the ith layer structure in the ith layer structure, and is positioned on the first straight line;

and step 3: establishing an oxyz coordinate system, wherein an x axis represents a convection heat dissipation coefficient at the bottom end of the power module, a y axis represents power loss of the chip, a z axis represents a first summation value, and HA multiplied by PA coordinate points are obtained in the oxyz coordinate system according to HA multiplied by PA group parameters and HA multiplied by PA first summation values respectively corresponding to the HA multiplied by PA group parameters;

and 4, step 4: obtaining a three-dimensional curved surface in an oxyz coordinate system according to the HA multiplied by PA coordinate points by using an interpolation method;

and 5: mapping three-dimensional surfaces in an oxyz coordinate system to o ₁ x ₁ y ₁ In the coordinate system, obtaining a first mapping result, wherein the x-axis coordinate, the y-axis coordinate and the x-axis coordinate ₁ The axis coordinate and the y1 axis coordinate correspond to each other, and the z axis coordinate corresponds to o ₁ x ₁ y ₁ The eigenvalues of the coordinate points in the coordinate system (i.e. the x-axis coordinate, the y-axis coordinate, the z-axis coordinate of a point of the oxyz coordinate system are equal to the projection of the point onto o, respectively ₁ x ₁ y ₁ X of points derived from a coordinate system ₁ Axis coordinates, y1 axis coordinates, eigenvalues);

at o ₁ x ₁ y ₁ In the coordinate system, the characteristic value in the first mapping result is equal to R _jc,1 The points are connected to form a 1 st connecting line, and the characteristic value in the first mapping result is equal to R _jc,2 The point of the first mapping result is connected to form a 2 nd connecting line, wherein the characteristic value is equal to R, 8230, 8230 _jc,NA The points are connected to form an NA connecting line, so that the NA connecting line is obtained; NA first set values R _jc,1 、R _jc,2 、……、R _jc,NA Equidistant and numerical values are sequentially increased, and the NA first set values are determined according to the numerical value range of the HA multiplied by PA first summation values;

dividing the first virtual line segment into N sub-line segments according to each connection line in the NA connection lines with the intersection point of the first virtual line segment, wherein N is more than or equal to 2 and less than or equal to 10; the values of the NA first set values and the value of the NA are determined by the value of N, and the sum of the lengths of the N sub-line segments is the length of the first virtual line segment; the first end point (FA) and the second end point (FD) of the first virtual line segment are at x ₁ The axial coordinates are all P _Loss (P1) at y ₁ The coordinates on the axis are htc (1), htc (HA), P _Loss (P1) is the rated power of the chip, P _Loss (P1)≤P _Loss (PA)；

Step 6, establishing a thermal impedance model of the power module; the thermal impedance model is provided with a first node, a first element for representing the actual power loss of the chip, and N heat transfer branches which are identical in structure and are mutually connected in parallel; the temperature value of the first node is the measured temperature of the bottom end of the power module; one end of the first element is connected with the heat sink;

the thermal impedance model has N connection states; when the actual convection heat dissipation coefficient of the bottom end of the power module is within the nth sub-range of the convection heat dissipation coefficient, the thermal impedance model is in the nth connection state, and the other end of the first element and the first node are respectively and correspondingly connected with the two ends of the nth heat transfer branch, so that a Cauer heat transfer network structure is formed;

the temperature of a node, close to the first element, of a thermal resistance element corresponding to the ith layer structure in the nth heat transfer branch is the temperature of a set measuring position of the ith layer structure to be determined; the upper limit and the lower limit of the nth sub-range of the convection heat dissipation coefficient are respectively the distance x of the nth sub-line segment ₁ End of coordinate axis, close to x ₁ Convection heat dissipation coefficients corresponding to the endpoints of the coordinate axes;

wherein, the thermal resistance R of the thermal resistance element corresponding to the ith layer structure in the nth heat transfer branch _i,n And a heat capacity C of the heat mass corresponding to the i-th layer structure _i,n The expression of (c) is as follows:

wherein, d _i Is the thickness of the i-th layer structure, K _i,n Is the thermal conductivity in the nth heat transfer branch corresponding to the material of the ith layer structure, c _i,n Specific heat capacity, q, of the nth heat transfer branch corresponding to the material of the ith layer structure _i,n,z Is prepared by mixing P _Loss,n 、htc _n Applying a second set temperature TB to the heat flow density of the set measuring position of the i-th layer structure obtained after the finite element thermal simulation model established in the step 1, wherein the second set temperature TB is the applied environment temperature, P _Loss,n 、htc _n The convective heat dissipation coefficient and the power loss of the chip corresponding to the nth characteristic coordinate point are respectively _solder1 The surface area of the layer 2 structure is O ₁ x ₁ y ₁ Coordinate points in a coordinate system;

wherein, the nth characteristic coordinate point is located on the nth sub-line segment, and the coordinate value of the nth characteristic coordinate point on the y1 axis is close to the x of the nth sub-line segment ₁ The value range of the difference between the coordinate values of the end points of the axes on the y1 axis is [30% × L ] _n ,70％×L _n ]，L _n The absolute value of the difference value of coordinate values of two end points of the nth sub-line segment on the y1 axis is N =1,2, \8230;, N;

T'(1) _n 、T'(2) _n temperatures T of the set measuring positions of the 1 st layer structure to be determined corresponding to the nth heat transfer branch ₁ Temperature T of a set measurement position of a 2 nd layer structure to be determined ₂ Or T' (1) _n 、T'(2) _n Is prepared by adding P _Loss,n 、htc _n Applying a second set temperature TB to the temperature of the set measuring position of the layer 1 structure and the temperature of the set measuring position of the layer 2 structure obtained after the finite element thermal simulation model established in the step 1 is applied;

(A)K _i,n temperature T for a set measurement position of an ith layer structure to be determined _i A function of c _i,n Temperature T for a set measuring point of an ith layer structure to be determined _i A function of (a); or alternatively

(B) If the thermal resistance of the ith layer structure is temperature sensitive thermal resistance, K _i,n Temperature T for a set measuring point of an ith layer structure to be determined _i Otherwise, K _i,n Is a fixed value calculated from the third set temperature TC; if the heat capacity of the i-th layer structure is a temperature sensitive heat capacity, c _i,n Temperature T for a set measurement position of an ith layer structure to be determined _i Otherwise, c _i,n Is a fixed value calculated from the third set temperature TC.

The applicant finds that, in research, the convective heat dissipation coefficient (i.e. a parameter reflecting the heat dissipation performance of the heat sink disposed at the bottom end of the power module) at the bottom end of the power module and the power loss of the chip have a large influence on the heat flow path of the power module. In the invention, a plurality of points are respectively selected from the preset range of the convective heat dissipation coefficient at the bottom end of the power module and the preset range of the power loss of the chip, thereby forming an HA multiplied by PA group parameter. And calculating each group of parameters by applying the parameters to a finite element thermal simulation model to obtain a first summation value corresponding to the group of parameters, so as to obtain a three-dimensional curved surface in an oxyz coordinate system by an interpolation method. According to the research of the applicant, the first summation value can reflect the influence of the convective heat dissipation coefficient at the bottom end of the power module and the power loss of the chip on the heat flow path. By projecting three-dimensional curved surfaces to o ₁ x ₁ y ₁ Obtaining a first mapping result by a coordinate system, and then taking a plurality of discrete first set values (reflecting the change of a first summation value from small to large), thereby connecting all points with equal characteristic values in the first mapping result to form NA connecting lines, namely connecting o according to the first summation value ₁ x ₁ y ₁ A rectangle formed by a preset range of the convection heat dissipation coefficient at the bottom end of the power module and a preset range of the power loss of the chip in the coordinate system is divided into a plurality of areas. By respectively taking characteristic coordinate points on N sub-line segments divided in the first virtual line segment, the method can be applied toThe convective heat dissipation coefficient of the bottom end of the power module corresponding to the characteristic coordinate point on the nth sub-line segment and the power loss of the chip are used as representatives of the area corresponding to the nth sub-line segment, so that the thermal impedance model of the power module is in a corresponding connection state when the actual convective heat dissipation coefficient of the bottom end of the power module is in a corresponding convective heat dissipation coefficient sub-range, a corresponding thermal impedance model can be established, and in the thermal impedance model, the heat flow density of a set measurement position corresponding to an upper copper layer, a ceramic layer, a lower copper layer, a substrate solder layer and a substrate layer can be obtained through the coordinates of the nth characteristic coordinate point before actual measurement, and the heat flow density does not need to be obtained through recalculation in a finite element thermal simulation model according to the actual convective heat dissipation coefficient of the bottom end of the power module and the actual power loss of the chip, and the simulation time is greatly reduced.

Due to the x of each characteristic coordinate point ₁ The axis coordinates are the rated power P of the chip _Loss (P1), and the power of the chip during operation is generally less than the rated power. Through the setting, the established thermal impedance model considers the condition of the highest chip power loss, namely, after each characteristic coordinate point is selected, the actually obtained thermal impedance model can obtain the temperature of the set measuring position of each layer when the chip power loss is the rated power, the condition that the temperature estimated value obtained by the thermal impedance model established according to the smaller chip power loss is smaller than the actual temperature of the actual chip working at the rated power is avoided as much as possible, and the condition that the estimated temperature is lower due to the higher actual temperature is avoided as much as possible under the condition that the temperature estimation precision is ensured.

In the application, the influence of the convection heat dissipation coefficient at the bottom end of the power module and the power loss of the chip on the power module is considered by calculating the first summation value when the convection heat dissipation coefficient at the bottom end of different power modules and the power loss of different chips are calculated. Compared with a thermal impedance model without considering influence on convection heat dissipation coefficient and influence on power loss in the prior art, the thermal impedance model established by the method has better applicability.

In the parallel technical solution (a) of the present application, the thermal resistance of each thermal resistance elementR _i,n Thermal capacity C _i,n In the calculation formula, K is calculated by using the actually measured ambient temperature _i,n 、c _i,n Less time is spent. And the effective heat transfer area does not need to be calculated by using the actual power loss.

In the parallel technical scheme (B), for the temperature-sensitive thermal resistance and the temperature-sensitive thermal capacity, K is represented by actual temperature (i.e. temperature of corresponding point in the thermal impedance model) respectively _i,n 、c _i,n . For the non-temperature sensitive thermal resistance and the non-temperature sensitive thermal capacity, the third set temperature TC is used for calculating the thermal conductivity and the specific heat capacity, and the difference between the calculation result and the result calculated by using the actual temperature (the temperature of the corresponding point in the thermal impedance model) is smaller, so that the third set temperature can be used for calculation before measurement, and thus, the number of parameters which need to be recalculated by the thermal impedance model according to the actual measurement is smaller, and the time required for subsequently setting the temperature estimation of the measurement position for each layer of the power module can be further reduced. Compared with the existing thermal impedance modeling method without considering the influence of the temperature on the thermal parameters (thermal conductivity and specific heat capacity) of each layer of the 7-layer packaging structure, the modeling efficiency is higher, and the model modeling precision is better due to the consideration of the influence of the temperature on the thermal parameters of each layer.

In the above technical solution, in the step 5:

R _jc,1 ≥R _jc-min and R is _jc,NA ≤R _jc-max Wherein the difference value between two adjacent first set values is a fixed value Δ R _jc ，R _jc-max Is the maximum value, R, of the HA x PA first summation values _jc-min Is the minimum of the HA x PA first summation values,

and is

ε ₁ Is a first predetermined percentage.

NU connecting lines in the NA connecting lines have intersection points with the first virtual line segment;

the method comprises the following steps that (1) the U1 connecting line, the U2 connecting line, the 8230, the first summation value corresponding to the NU connecting line is increased in sequence;

the NU connecting lines and the first virtual line segment are respectively intersected, so that the part of the first virtual line segment between the U1-th connecting line and the NU connecting line is divided to obtain NU-1 sub line segments in the N sub line segments;

if it is

If not, the sub-line segment formed by the part of the first virtual line segment between the U2 connection line and the first end point (FA) and the sub-line segment formed by the part of the first virtual line segment between the U1 connection line and the first end point (FA) and the sub-line segment formed by the part of the first virtual line segment between the U2 connection line and the U1 connection line are two different sub-line segments of the N sub-line segments; wherein the first difference value Δ R _A-jc The difference value is a first summation value corresponding to the intersection point of the U1-th connecting line and the first virtual line segment, and a first summation value corresponding to a first endpoint (FA); epsilon ₂ Is a second preset percentage;

if it is

If not, the sub-line segment formed by the part of the first virtual line segment between the NU-1 connecting line and the second end point (FD) and the sub-line segment formed by the part of the first virtual line segment between the NU-1 connecting line and the NU-1 connecting line are two different sub-line segments of the N sub-line segments; wherein the second difference value DeltaR _B-jc Is the difference between a first summation value corresponding to the intersection of the second endpoint (FD) and the first virtual line segment and a first summation value corresponding to the intersection of the NU line and the first virtual line segment.

In the above technical scheme, if the variation range of the thermal resistance of the ith layer structure in the set environment temperature range is larger than the third preset percentage epsilon ₃ Then judgeBreaking the thermal resistance of the ith layer structure into temperature sensitive thermal resistance;

if the variation range of the heat capacity of the ith layer structure in the set environment temperature range is more than a fourth preset percentage epsilon ₄ And judging that the heat capacity of the ith layer structure is temperature sensitive heat capacity.

In a preferred embodiment. The method for judging whether the thermal resistance of the ith layer structure is the temperature-sensitive thermal resistance and whether the heat capacity of the ith layer structure is the temperature-sensitive heat capacity is as follows:

htc1, P _Loss1 Applying the heat resistance to the finite element thermal simulation model established in the step 1, changing the applied environment temperature in the finite element thermal simulation model within a set environment temperature range, calculating the heat resistance and heat capacity of each layer structure, and calculating the heat resistance of each layer structure and the heat capacity of each layer structure at each applied environment temperature, thereby determining whether the heat resistance of each layer structure is temperature sensitive heat resistance and determining whether the heat capacity of each layer structure is temperature sensitive heat capacity;

htc1 is a preset value of the convective heat dissipation coefficient at the bottom end of the power module, and P is _Loss1 Is a preset value of the power loss of the chip.

In the above technical solution, the value of htc (1) is such that: when the power loss of the chip is P _Loss (PA), the convection heat dissipation coefficient of the bottom end of the power module is not less than htc (1), and the ambient temperature is normal temperature, the temperature of the set measuring position of the 1 st layer structure is not more than the upper limit of the working temperature of the chip.

The applicant finds in research that if the htc (1) value (lower limit value of convective heat dissipation coefficient) is set too small, when power loss of a chip is applied, the temperature of a set measurement position of a chip layer easily exceeds the upper limit of the operating temperature of the chip, and the thermal impedance model established at this time is of little significance, because even if the temperature of each node can be obtained according to the thermal impedance model, the htc (1) value exceeding the upper limit of the operating temperature of the chip cannot be adopted at all in practice in order to avoid chip damage. Through the arrangement, the convection coefficient value that the set measuring position of the chip layer is larger than the upper limit of the working temperature of the chip can be obtained when the analysis power loss is the upper limit value and the ambient temperature is the normal temperature.

In a preferred technical scheme, the selection method of htc (1) is as follows: will P _Loss (PA) and ambient temperature are applied to the finite element thermal simulation model in the step 1 at normal temperature, the convective heat dissipation coefficient of the bottom end of the power module applied to the finite element thermal simulation model is adjusted until the temperature of the set measuring position of the layer 1 structure obtained according to the finite element thermal simulation model is not more than the upper limit of the working temperature of the chip, and the convective heat dissipation coefficient of the bottom end of the power module obtained after adjustment is used as the value of htc (1).

In the above technical solution, the coordinate value of the nth feature coordinate point on the y1 axis and the x approaching the nth sub-line segment ₁ The end point of the shaft is at y ₁ The value range of the difference between the coordinate values on the axis is [45% × L ] _n ,55％×L _n ]；

Preferably, the nth feature coordinate point is at y ₁ Coordinate value on axis and x of approach of nth sub-line segment ₁ The end point of the shaft is at y ₁ The difference between the coordinate values on the axis is 50% × L _n 。

By the arrangement, the nth characteristic coordinate point selected in the nth sub-line segment can better represent the characteristic of the area.

In the above technical solution, the position M1 of the upper surface of the 1 st layer structure, the position M2 of the upper surface of the 2 nd layer structure, the position M3 of the upper surface of the 3 rd layer structure, the position M5 of the upper surface of the 5 th layer structure, the position M6 of the upper surface of the 6 th layer structure, and the position M7 of the upper surface of the 7 th layer structure correspond to the set measurement positions of the 1 st layer structure, the 2 nd layer structure, the 3 rd layer structure, the 5 th layer structure, the 6 th layer structure, and the 7 th layer structure, respectively, M4 is the set measurement position of the 4 th layer structure, and the value range of the height difference between the position of M4 and the lower surface of the 4 th layer structure is [30% × d ₄ ,70％×d ₄ ]The positions M1, M2, M3, M4, M5, M6, M7 are all located on the first straight line.

In a preferred embodiment, the first line passes through a central position of the upper surface of the layer 1 structure;

in a preferred embodiment, the difference in height between the position of M4 and the lower surface of the layer 4 structure is 50% x d ₄ 。

The applicant finds that the temperature difference between the upper surface and the lower surface of the chip layer, the chip solder layer, the upper copper layer, the lower copper layer, the substrate solder layer and the substrate layer is small, so that the upper surface position can be used as a set measuring position, the temperature difference between the upper surface and the lower surface of the ceramic layer is large (the upper surface temperature is high, the lower surface temperature is low), and if the upper surface or the lower surface is used as the set measuring position, the estimation precision can be poor when the established thermal impedance model is used for temperature estimation of each set measuring position. In this application, through setting for the value range of the difference in height of M4 position and layer 4 structure lower surface for the temperature of ceramic layer (getting the temperature between ceramic layer temperature upper limit value, the temperature lower limit value promptly) can be represented as far as possible to M4 position, and can not cause the temperature estimation effect of thermal impedance model poor because of adopting the ceramic layer the highest temperature or the minimum temperature to represent the ceramic layer temperature.

In a more preferred embodiment, M1 is the center position of the upper surface of the layer 1 structure.

In a more preferred embodiment, the difference in height between the location of M4 and the lower surface of the layer 4 structure is 50% x d ₄ 。

In the technical scheme, N is more than or equal to 2 and less than or equal to 10; preferably, 3. Ltoreq. N.ltoreq.5.

In the above technical solution, the value of htc (1) is such that: when the power loss of the chip is a first preset value P _Loss (P1) and when the convection heat dissipation coefficient of the bottom end of the power module is not less than htc (1), the temperature of the set measuring position of the 1 st layer structure is not more than the upper limit of the working temperature of the chip.

In a preferred embodiment, htc (1) is selected by: will P _Loss (PA) and an upper limit value of the environmental temperature are applied to the finite element thermal simulation model in the step 1, the bottom end convection heat dissipation coefficient of the power module applied to the finite element thermal simulation model is adjusted until the temperature of the set measuring position of the layer 1 structure obtained according to the finite element thermal simulation model is not larger than the upper limit of the working temperature of the chip, and the adjusted bottom end convection heat dissipation coefficient of the power module is used as the value of htc (1).

In the above technical solution, the power module may be one of a diode module, a MOSFET module, an IGBT module, and a thyristor module.

The invention also provides a junction temperature estimation method, wherein a radiator is arranged at the bottom end of the power module in the actual space, and the output power of the radiator is fixed;

the chip junction temperature estimation method comprises the following steps:

in the finite element thermal simulation model established in step 1 of the power module thermal impedance model modeling method described in any one of the above, applying a power loss of an actual chip, and adjusting a value of a convective heat dissipation coefficient of the bottom end of the power module applied in the finite element thermal simulation model until a difference between a temperature of the bottom end of the power module obtained in the finite element thermal simulation model and a temperature of the bottom end of the actually measured power module is not greater than a preset temperature error value;

and taking the value of the convection heat dissipation coefficient at the bottom end of the power module obtained after adjustment as the actual convection heat dissipation coefficient at the bottom end of the power module, so that the thermal impedance model is in a connection state corresponding to the convection heat dissipation coefficient sub-range according to the convection heat dissipation coefficient sub-range to which the actual convection heat dissipation coefficient at the bottom end of the power module belongs, and taking the temperature at the other end of the first element obtained according to the thermal impedance model as the junction temperature of the chip.

The applicant finds that due to the complexity of air flow analysis, it is difficult to obtain the value of the convective heat dissipation coefficient at the bottom end of the power module according to the parameters of an actual radiator (such as a water cooling module and an air cooling module), so that the invention adjusts the value of the convective heat dissipation coefficient at the bottom end of the power module applied in a finite element thermal simulation model during the estimation of the junction temperature, and compares the temperature at the bottom end of the power module obtained in the finite element thermal simulation model with the temperature at the bottom end of the actually measured power module in real time, thereby obtaining the convective heat dissipation coefficient at the bottom end of the power module which is consistent with or close to the effect of the radiator actually applied at the bottom end of the power module, so that the thermal impedance model is in a corresponding connection state, thereby obtaining the estimation value of the junction temperature of the chip more quickly under the condition of less influence on the estimation accuracy, and greatly improving the temperature estimation efficiency.

The present invention also provides a computer apparatus comprising: a memory for storing a computer program; a processor for implementing the steps of the power module thermal impedance model modelling method as described in any one of the above and/or the steps of the junction temperature estimation method as described above when executing the computer program.

The invention also provides a storage medium having stored thereon a computer program which, when executed by a processor, carries out the steps of the power module thermal impedance model modelling method as defined in any one of the preceding claims and/or the steps of the junction temperature estimation method as defined above.

Based on the technical scheme, the rapid robust power module thermal impedance model modeling method considering the temperature characteristics of the material has the following beneficial effects:

1) The invention calculates the effective heat transfer area by using the finite element steady-state thermal simulation result which can be quickly solved, solves the problem of low calculation precision of the effective heat transfer area of the current power module due to the adoption of the thermal diffusion angle with lower precision, and greatly improves the junction temperature monitoring accuracy of the thermal impedance model of the power module.

2) Compared with the traditional thermal impedance model, the thermal impedance model disclosed by the invention does not need to determine the transient temperature response curve of the node in the thermal impedance model, does not need to identify a large number of thermal resistance and thermal capacitance parameters, can effectively reduce the extraction time of the thermal resistance and thermal capacitance parameters, and improves the parameter extraction efficiency.

3) The thermal impedance network model takes the temperature effect of the power module packaging material into consideration, so that the junction temperature monitoring precision of the model in a high-temperature area can be ensured.

4) The thermal impedance network model considers the influence of boundary conditions (namely convection heat dissipation coefficient and chip power loss) on a heat flow path, and greatly improves the applicability of the thermal impedance model under different boundary conditions.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.

FIG. 1 is a schematic diagram of a set measurement position of each layer structure in a conventional power module package structure according to an embodiment of the present invention;

FIG. 2 is a diagram of a finite element steady state finite element thermal simulation model obtained in accordance with an embodiment of the present invention;

FIG. 3 is a graph illustrating a heat flow density curve and an effective heat transfer area curve of a power module according to an embodiment of the present invention;

FIG. 4 is a diagram of a power module heat flow density curve at different ambient temperatures according to a finite element of an embodiment of the present invention;

FIG. 5 is a graphical representation of material thermal conductivity, specific heat capacity as a function of temperature for various layer structures of an embodiment of the present invention;

FIGS. 6 and 7 are schematic diagrams showing the variation of thermal resistance and thermal capacity with temperature of the respective layer structures according to the embodiment of the present invention;

FIG. 8 is a comparison of heat flow profiles for the substrate layer L7 under different cooling conditions obtained in accordance with an embodiment of the present invention;

FIG. 9 is a schematic diagram of a three-dimensional surface created by an embodiment of the present invention;

FIG. 10 is a mapping of a three-dimensional surface in an xyz coordinate system to o according to an embodiment of the present invention ₁ x ₁ y ₁ A schematic diagram of a first mapping result obtained by a coordinate system;

FIG. 11 is a schematic diagram of a thermal impedance model established in an embodiment of the present invention that takes into account temperature effects;

FIG. 12 is a flow chart of a method for modeling a thermal impedance model of a power module according to an embodiment of the invention;

fig. 13 (a), 13 (b), and 13 (c) are graphs comparing results obtained by experimental measurement and estimated by the method of the present invention under different power conditions, respectively.

Fig. 14 (a), 14 (b), and 14 (c) are graphs comparing results obtained by experimental measurement under different cooling conditions and results estimated by the method of the present invention, respectively.

FIG. 15 (a), FIG. 15 (b), FIG. 15 (c) and FIG. 15 (d) are respectively the environmental temperature T of the embodiment of the present invention _a =40 ℃ and ambient temperature T _a =60 ℃ and ambient temperature T _a =80 ℃ ambient temperature T _a =100 ℃ junction temperature estimation result obtained by the method of the invention and junction temperature estimation result obtained by finite element simulation method, wherein P is a graph _Loss ＝100W，htc＝5000W·m ^-2 ·℃ ^-1 ；

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Example 1

To explain the present invention in more detail, the present invention will be further explained in detail by taking the inflight power semiconductor module FF150R12ME3G as an example, with reference to the accompanying drawings. The encapsulation structure of the IGBT power module with the Yingfei model number of FF150R12ME3G is the structure shown in FIG. 2.

The invention provides a power module thermal impedance model modeling method, wherein a 7-layer packaging structure of a power module comprises a 1 st layer structure, a 2 nd layer structure, a 8230, a 7 th layer structure and a 7 th layer structure, wherein the 1 st layer structure, the 2 nd layer structure, the 8230and the 7 th layer structure are sequentially arranged from top to bottom in the height direction, and are respectively a layer L1 where a chip is located, a chip solder layer L2, an upper copper layer L3, a ceramic layer L4, a lower copper layer L5, a substrate solder layer L6 and a substrate layer L7.

The power module thermal impedance model modeling method comprises the following steps:

step 1: and establishing a finite element thermal simulation model of the power module according to the material and dimension parameters of the 7-layer packaging structure.

As shown in fig. 1, in a 7-layer package structure in the prior art, positions M1, M2, 8230, M7 are respectively set measurement positions of a 1 st layer structure, a 2 nd layer structure, 8230, 7 th layer structure, and positions M1, M2, M3, M4, M5 and M6 are all located on a first straight line, and the first straight line is parallel to a height direction of a power module.

Preferably, M1, M2, M3, M5, M6, and M7 are the position of the upper surface of the 1 st layer structure, the position of the upper surface of the 2 nd layer structure, the position of the upper surface of the 3 rd layer structure, the position of the upper surface of the 5 th layer structure, the position of the upper surface of the 6 th layer structure, and the position of the upper surface of the 7 th layer structure, respectively, and the height difference between the position of M4 and the lower surface of the 4 th layer structure has a value in the range of [30% × d × ₄ ,70％×d ₄ ]。

More preferably, M1 is the central position of the upper surface of the layer 1 structure.

More preferably, the height difference between the position of M4 and the lower surface of the layer 4 structure is 50% multiplied by d ₄ 。

In fig. 1, the temperature at position M1 is taken as the junction temperature T of the power module _j (i.e., the temperature of the chip layer L1). The temperature of the position M2 is taken as the temperature T of the solder layer L2 of the chip _solder1 . The temperature at position M3 is taken as the temperature T of the upper copper layer L3 _copper1 . The temperature at the position M4 is taken as the temperature T of the ceramic layer L4 _ceramic . The temperature at the position M5 is taken as the temperature T of the lower copper layer L5 _copper2 . The temperature of the position M6 is set as the temperature T of the substrate solder layer L6 _baseplate . The temperature at the position M7 is taken as the temperature T of the lower surface of the heat dissipation substrate layer L7 _c 。

The applicant finds that the temperature difference between the upper end and the lower end of the ceramic layer is large, and if the temperature of the upper end is selected, according to the thermal impedance model, because the thermal resistance and the thermal capacity of the ceramic layer are temperature sensitive parameters, when a large temperature value is obtained, the result of the established thermal impedance model is inaccurate, and the measurement of the junction temperature Tj is inaccurate. Therefore, the position of half of the thickness is selected to be equivalent to the average value of the temperatures of the upper surface and the lower surface, the actual situation is better met, and the simulation effect on the thermal resistance and the thermal capacity of the ceramic layer is better.

According to the material parameters, the size parameters and the chip coordinate position, a finite element steady-state finite element thermal simulation model which can be rapidly solved, namely a finite element thermal simulation model with a three-dimensional structure, is established. In the invention, a steady-state finite element thermal simulation model as shown in fig. 2 is established in an ANSYS Workbench according to the material parameters and the size parameters of the power module.

The power module may be a diode power module, or a MOSFET power module, or an IGBT power module, or a thyristor power module.

In the invention, the established finite element thermal simulation model can be established without considering the material, the size and the like of the diode, namely, the model of the 7-layer packaging structure comprising the layer where the chip is positioned is only established. The applicant has found that the diode generates heat during operation, and the heat also mainly affects the shell temperature (i.e. the temperature of the lower surface of the substrate layer). In the scheme, the influence on the thermal impedance model is that the temperature of the first node TU is mainly influenced by the shell temperature, and even if the diode is not modeled, the junction temperature can still change according to the shell temperature when the temperature of the diode is raised, so that the influence on the junction temperature measurement precision is small.

Step 2A: and judging whether the thermal resistance of the ith layer structure is temperature sensitive thermal resistance or not and judging whether the heat capacity of the ith layer structure is temperature sensitive heat capacity or not.

Step 2A may be performed between step 1 and step 2, or may be performed in any of steps 2-6.

In this application, the power loss P of the chip _Loss (W) at a heat generation rate H _G (W·mm ^-3 ) Is loaded to the active region (i.e. chip layer) of the finite element thermal simulation model, and the specific formula is as follows:

where V represents the active area volume (i.e., chip volume). The convective heat dissipation coefficient (htc) is used as a simplified thermal boundary condition to represent the heat dissipation capability of a heat sink disposed at the bottom end of the power module.

For power devices, power losses include both switching losses and conduction losses. Those skilled in the art will understand how to set the power dissipation of a chip based on the performance of the chip when in operation.

In the present application, the method for calculating the effective heat transfer area of each layer is as follows: and acquiring junction temperature information and temperature information of the chip solder layer L2 based on the established finite element steady-state thermal simulation result capable of being solved quickly so as to correct the heat transfer area of the chip layer L1. The chip solder layer L2 still sees its upper surface area as the effective heat transfer area of the layer. According to the coordinate position of the chip, a heat flow density curve in the direction from the upper surface of the upper copper layer L3 to the lower surface of the substrate layer L7 in the vertical downward direction of the center position of the chip is obtained so as to correct the effective heat transfer area of the rest layers.

Determining the effective heat transfer area A of the chip layer L1 _chip The calculation formula of (2) is as follows:

wherein, T (1) ₍₁₎ And T (2) ₍₁₎ Respectively obtaining the module junction temperature and the chip solder layer L2 temperature (the finite element steady-state thermal simulation temperature measuring point is shown in figure 1) obtained by applying the 1 st group of parameters, and K _Tj For this purpose, the thermal conductivity, d, of the chip layer L1 corresponds _chip Is the chip layer L1 thickness. T (1) ₍₁₎ I.e. the temperature at point M1 of fig. 1.

For the layers below the chip solder layer L2, including the upper copper layer L3, the ceramic layer L4, the lower copper layer L5, the substrate solder layer L6 and the substrate layer L7, the effective heat transfer area can be calculated by using the heat flow density qz curve along the vertically downward direction of the chip center position as shown in fig. 3, and the position of the vertical path distance zero point in fig. 3 represents the height position of the top end of the upper copper layer L3. The closer to the bottom end of the power module, the greater the vertical path distance. The solid curve of fig. 3 can be read directly and the dashed curve is the power loss P according to the chip applied _Loss And calculating a ratio with the heat flux density corresponding to the set measurement position of each layer in the solid curve. Fig. 3 is a heat flux density curve obtained with an ambient temperature of 25 ℃.

The applicant found in the study that the influence of the ambient temperature on the heat flow density is negligible and can be ignored, as shown in fig. 4. Therefore, the heat flow density curve can be extracted by using a fixed ambient temperature of 25 ℃.

The thermal conductivity and specific heat capacity of the different materials as a function of temperature are shown in FIG. 5. Thermal conductivity K of the i-th layer structure _T(i) Is a function of the temperature T (i) of the set measurement location of the ith layer structure, the specific heat capacity c of the ith layer structure _T(i) Is a function of the temperature T (i) of the set measuring position of the i-th layer structure.

In step 2A, the temperature T (i) of the set measurement position of the ith layer structure can be obtained through a finite element thermal simulation model, so that the thermal conductivity and the specific heat capacity of the corresponding layer structure can be obtained through calculation according to T (i).

The MATLAB/cftool box can be utilized to fit the relationship between the heat conductivity, the specific heat capacity and the temperature, and the specific fitting formula can be as follows:

the formula I is as follows:

the second formula is as follows:

the calculation formula of the thermal conductivity and the specific heat capacity of a certain material is not limited to the formula I and the formula II, and can be determined by a person skilled in the art according to the actual material and the existing knowledge in the field. Calculating the thermal resistance R of the i-th layer structure using the following equation _i Heat capacity C of i-th layer structure _i

The convective heat dissipation factor is applied to the bottom of the power module and the power loss of the chip is applied to the layer 1 structure through the heat generation rate parameter, as will be understood by those skilled in the art.

If the variation amplitude of the thermal resistance of the ith layer structure in the set environment temperature range is more than a third preset percentage epsilon ₃ And judging that the thermal resistance of the ith layer structure is temperature sensitive thermal resistance. I.e. in the setting ringAnd in the ambient temperature range, obtaining the maximum value and the minimum value of the thermal resistance of the ith layer structure, wherein the variation amplitude is the ratio of the difference value of the maximum value and the minimum value of the thermal resistance of the ith layer structure to the minimum value of the thermal resistance of the ith layer structure.

If the variation range of the heat capacity of the ith layer structure in the set environment temperature range is more than a fourth preset percentage epsilon ₄ And judging that the heat capacity of the ith layer structure is temperature sensitive heat capacity. In other words, within a set ambient temperature range, the maximum value and the minimum value of the heat capacity of the ith layer structure are obtained, and the variation range is the ratio between the difference value of the maximum value and the minimum value of the heat capacity of the ith layer structure.

Third predetermined percentage epsilon ₃ Fourth predetermined percentage of ₄ The value can be 20%, or other values can be taken according to actual needs.

The method for judging whether the thermal resistance of the ith layer structure is the temperature-sensitive thermal resistance and whether the heat capacity of the ith layer structure is the temperature-sensitive heat capacity is as follows:

htc1, P _Loss1 And (2) applying the heat resistance to the finite element thermal simulation model established in the step (1), changing the applied environment temperature in the finite element thermal simulation model within a set environment temperature range, calculating the heat resistance and heat capacity of each layer of structure, and calculating the heat resistance of each layer of structure and the heat capacity of each layer of structure at each applied environment temperature, thereby determining whether the heat resistance of each layer of structure is temperature-sensitive heat resistance and determining whether the heat capacity of each layer of structure is temperature-sensitive heat capacity. Htc1 is a preset value of the convective heat dissipation coefficient at the bottom end of the power module, and P is _Loss1 Is a preset value of the power loss of the chip.

In the established finite element steady-state finite element thermal simulation model, the environmental temperature T is changed _a Acquiring steady-state temperature information of different physical layers at different environmental temperatures, combining a relational expression of thermal conductivity of different materials changing along with the temperature and a relational expression of specific heat capacity changing along with the temperature, which are fitted in an MATLAB/cftool box, calculating corresponding thermal resistance and thermal capacity parameters by using the formulas, analyzing the temperature sensitivity of the thermal resistance and the thermal capacity parameters, and determining the thermal resistance R and the thermal capacity C which need real-time temperature iteration according to standards.

To analyze the temperature sensitivity of the thermal parameters of different material layers, the results of finite element steady-state thermal simulation are first utilized. In this case, a constant power loss P is applied to the chip active region _Loss =100W; the bottom plate (namely the lower surface of the substrate layer) applies constant convection heat dissipation coefficient htc1=5000W.m ^-2 .℃ ^-1 Constant convection heat dissipation coefficient htc2=10w.m is applied to four sides of the bottom plate (namely four sides of the substrate layer) ^-2 .℃ ^-1 To simulate external heat dissipation conditions; ambient temperature T _a Respectively taking 30 ℃, 60 ℃, 90 ℃, 120 ℃ and 150 ℃. Therefore, the steady-state temperature information of each layer under different environmental temperature conditions can be obtained, and the thermal resistance and the thermal capacity of each layer corresponding to different environmental temperatures can be obtained by using a formula.

The temperature sensitivity of the thermal parameters of each layer is shown in fig. 6 and 7. In the present invention, for the convenience of implementation, only the thermal parameters with the variation range larger than 20% for the ambient temperature from 30 ℃ to 150 ℃ need to consider the temperature influence. As can be seen, only the chip layer L1 has the thermal resistance R _chip Thermal resistance R with ceramic layer L4 _ceramic And ceramic layer L4 heat capacity C _ceramic Changes with temperature exceed 20%, so temperature sensitivity needs to be taken into account when modeling the thermal impedance model.

And 2, step: the predetermined range of convective heat dissipation factor at the bottom of the power module [ htc (1), htc (HA)]HA values htc (1), htc (2), 8230, htc (HA) with sequentially increased values are selected in the chip, and the power loss of the chip is within a preset range [ P _Loss (1),P _Loss (PA)]The internally selected numerical values are sequentially increased by PA value P _Loss (1)、P _Loss (2)、……、P _Loss (PA) forming a set of parameters by one of the HA values and one of the PA values to obtain a HA x PA set of parameters, wherein the 1 st set of parameters is htc (1), P _Loss (1) The component (8230) \\ 8230 `, the parameter of the HA x PA group is Htc (HA), P _Loss (PA).

HA. PA is a preset value. HA. The value of PA is preferably not less than 5. And the values of HA and PA can be determined according to actual needs.

Applying the HA multiplied by PA group parameters to a finite element thermal simulation model respectively, and enabling the environment temperatureThe degree set value is used as the applied environment temperature in the finite element thermal simulation model according to the simulation result of the finite element thermal simulation model and K _i,TA To obtain HA × PA first summation values R _jc(1) 、R _jc(2) 、……、R _jc(HA×PA) Wherein

Wherein A is _i (m) effective heat transfer area corresponding to the ith layer structure after applying the mth set of parameters to the finite element thermal simulation model, A _i,z (m) an effective heat transfer area of the ith layer structure at a position in the height direction at a distance z from the upper end face of the ith layer structure after the mth group of parameters is applied to the finite element thermal simulation model, wherein m =1,2, \8230; k is _i,TA The thermal conductivity of the material of the i-th layer structure corresponding to the first set temperature TA (i.e. the thermal conductivity obtained by substituting the first set temperature TA into the calculation formula of the thermal conductivity of the i-th layer structure), d _i Is the thickness of the ith layer structure; t1 _m 、T2 _m The temperatures of the set measuring positions of the 1 st layer structure and the 2 nd layer structure obtained after the mth group of parameters are applied to the finite element thermal simulation model are respectively K (T1) _m ) Is expressed with a temperature T1 _m Corresponding thermal conductivity of the material of the layer 1 structure, A _solder1 Is the surface area of the 2 nd layer structure, P _Loss(m) For the power loss of the chip in the m-th set of parameters, q _m (i, z) is the heat flow density of the position, which is obtained by applying the mth group of parameters to the finite element thermal simulation model, of the ith layer structure, wherein the position is located on the first straight line and the height direction of the ith layer structure is away from the upper end surface of the ith layer structure by z. For example, the i-th layer structure is arranged in the height direction with the upper end face of the i-th layer structureA distance d _i And the position on the first straight line is the position of the lower end face of the ith layer structure.

The ambient temperature set point may be an ambient temperature ambient value, such as 25 ℃. When the HA multiplied by PA group parameters are applied respectively, the environmental temperature applied in the finite element thermal simulation model is not changed (namely the environmental temperature set value).

Wherein the 1 st group of parameters are applied to the finite element thermal simulation model to obtain the effective heat transfer area A of the ith layer structure _i (1) To thereby obtain a 1 st first summation value R _jc(1)

Wherein, A _i (1) To apply set 1 parameters to the effective heat transfer area corresponding to the ith layer structure after the finite element thermal simulation model, A _i,z (1) T1 is the effective heat transfer area of the ith layer structure at the height direction distance z from the upper end surface of the ith layer structure after the 1 st group of parameters are applied to the finite element thermal simulation model ₁ 、T2 ₁ The temperature P of the set measuring positions of the 1 st layer structure and the 2 nd layer structure obtained after the 1 st group of parameters are applied to the finite element thermal simulation model _Loss(1) For the power loss of the chip in set 1 parameters (i.e., the power loss of the chip applied in the finite element thermal simulation model), A _solder1 Is the area of the upper surface of the solder layer L2 of the chip, q ₁ (i, z) is the heat flow density of the position, which is obtained by applying the 1 st group of parameters to the finite element thermal simulation model, of the ith layer structure, wherein the position is at the height direction distance z from the upper end surface of the ith layer structure and is positioned on the first straight line.

In the present invention, the applied ambient temperature was taken as a fixed value of 25 ℃, and the power loss and cooling conditions were carefully analyzed, such as the heat flow profile of the substrate layer L7 under different boundary conditions as shown in fig. 8. As can be seen from fig. 8, as the htc value increases, the heat transfer area of the substrate layer decreases, i.e., one boundary condition corresponds to one heat flow path, and different boundary conditions cause a large change in the effective heat transfer area, which directly affects the value of the thermal impedance model parameter according to the calculation formula of the thermal parameter (i.e., thermal resistance and thermal capacity). This means that in practical application, the model parameters need to be corrected according to the boundary conditions, that is, the power loss of the chip and the convective heat dissipation coefficient at the bottom end of the power module are applied to the finite element thermal simulation model to obtain the simulation result, for example, the heat flow density, the thermal resistance and the thermal capacity of each layer according to the temperatures of different measurement points, and the like are obtained.

However, in practice, the temperature estimation accuracy can meet a certain index, and it is not necessary to spend a lot of time and cost to repeat the simulation and data processing in order to slightly improve the accuracy of the junction temperature monitoring.

Although the influence of the boundary conditions on the heat flow path can be intuitively reflected by using the heat flow density distribution in the finite element, it is necessary to use an index which can quantify the degree of influence of the boundary conditions on the heat flow path. The invention provides a quantitative index (namely a first summation value) for representing the influence degree of the boundary condition on the thermal parameter. The first summation value is a parameter index for representing the influence of the boundary condition on the heat transfer path, and refers to the thermal resistance of the crust at a certain temperature.

The heat transfer area is calculated by changing the setting of the boundary conditions in the finite element steady-state thermal simulation, and then the first summation value under different boundary conditions can be calculated, which is shown in table 2. In Table 2, line 1 is the values corresponding to htc (1), htc (2), and \8230, and htc (8), and column 1 is P _Loss (1)、P _Loss (2)、……、P _Loss (PA) corresponding values.

Because the temperature of the power module in specific application is limited within 150 ℃, the index is calculated by selecting the thermal conductivity of each layer of material at 150 ℃. The first set temperature TA can be set to 150 ℃.

TABLE 1 first summation values under different boundary conditions

And 3, step 3: and establishing an oxyz coordinate system, wherein the x axis represents the convection heat dissipation coefficient at the bottom end of the power module, the y axis represents the power loss of the chip, and the z axis represents a first summation value, so that HA multiplied by PA coordinate points are obtained in the oxyz coordinate system according to the HA multiplied by PA group parameters and HA multiplied by PA first summation values respectively corresponding to the HA multiplied by PA group parameters.

And 4, step 4: by using an interpolation method (i.e., fitting known three-dimensional coordinate points to obtain a three-dimensional curved surface), a three-dimensional curved surface is obtained in an oxyz coordinate system according to the HA × PA coordinate points, as shown in fig. 9.

And 5: mapping three-dimensional surfaces in an oxyz coordinate system to o ₁ x ₁ y ₁ In the coordinate system, a first mapping result is obtained, as shown in fig. 10. Wherein the numerical size can be characterized by color (or grayscale).

From the mapping result, the degree of influence of the boundary condition on the heat flow path can be known.

Wherein, the x-axis coordinate, the y-axis coordinate and o of the oxyz coordinate system ₁ x ₁ y ₁ X of the coordinate system ₁ The axis coordinate and the y1 axis coordinate correspond to each other, and the z axis coordinate of the oxyz coordinate system corresponds to o ₁ x ₁ y ₁ Characteristic values of coordinate points in a coordinate system.

According to the numerical range of the HA multiplied by PA first summation values, setting NA first set values R with sequentially increased numerical values _jc,1 、R _jc,2 、……、R _jc,NA So that R is _jc,1 ≥R _jc-min And make R _jc,NA ≤R _jc-max Wherein, the difference value of two adjacent first set values is a fixed value Δ R _jc ，R _jc-max Is the maximum value, R, of the HA x PA first summation values _jc-min Is the minimum of the HA x PA first summation values,

and is

ε ₁ Is a first predetermined percentage. Epsilon ₁ Less than or equal to 100 percent. The person skilled in the art can also set the value of the first preset percentage, for example 0.2, 0.5 or 0.8, depending on the actual situation. Fixed value deltar _jc The determination can be made according to the value of NA and the numerical range of the HA × PA first summation values.

For example, in FIG. 10, R is assigned to 0.33, 0.34, 0.35, and 0.36 _jc,1 、R _jc,2 、R _jc,3 、R _jc,4 。

At o ₁ x ₁ y ₁ In the coordinate system, the characteristic value in the first mapping result is equal to R _jc,1 The points are connected to form a 1 st connecting line, and the characteristic value in the first mapping result is equal to R _jc,2 The point of the first mapping result is connected to form a 2 nd connecting line, wherein the characteristic value is equal to R, 8230, 8230 _jc,4 Are connected to form the 4 th connecting line.

In fig. 10, the connecting lines of 0.335, 0.345, and 0.355 are auxiliary lines, not R _jc,1 、R _jc,2 、……、R _jc,NA A value of (1).

A first virtual line segment is defined.

Two end points of the first virtual line segment are respectively a first end point FA and a second end point FD;

the first end point FA and the second end point FD are at x ₁ The axial coordinates are all P _Loss (P1)，P _Loss (P1) is the rated power of the chip, P _Loss (P1)≤P _Loss (PA)；

The first end point FA and the second end point FD are arranged at y ₁ Coordinates on the axis are htc (1) and Htc (HA) respectively;

dividing the first virtual line segment into N sub line segments, wherein the sum of the lengths of the N sub line segments is the length of the first virtual line segment;

and the value of the NA first set values and the value of the NA are determined by the value of the N.

Namely, the value of N is selected first, so that the number of sub-line segments into which the first virtual line segment needs to be divided is determined, and the value of NA first set values (equidistant setting) can be selected.

the method comprises the following steps that (1) the line U1, the line U2, \8230, and the line 8230are formed in the line NU, and first summation values corresponding to the line U2 are sequentially increased;

the NU connecting lines and the first virtual line segment are respectively intersected, so that the part of the first virtual line segment between the U1-th connecting line and the NU connecting line is divided into NU-1 sub-line segments in the N sub-line segments.

In fig. 10, the 2 nd link (the U1 st link), the 3 rd link (the U2 nd link), and the 4 th link (the U3 rd link) intersect with the first virtual line segment (the line segment between FA and FD), so NU =3, and two sub-line segments between 0.34-0.35 and 0.35-0.36 are obtained by division.

If it is

If not, the sub-line segment formed by the part of the first virtual line segment between the U2-th connecting line and the first end point FA and the sub-line segment formed by the part of the first virtual line segment between the U1-th connecting line and the first end point FA and the part of the first virtual line segment between the U2-th connecting line and the U1-th connecting line are two different sub-line segments of the N sub-line segments; wherein the first difference value DeltaR _A-jc The difference value is a difference value between a first summation value corresponding to the intersection point of the U1-th connecting line and the first virtual line segment and a first summation value corresponding to the first endpoint FA; epsilon ₂ Is a second predetermined percentage. Epsilon ₂ Less than or equal to 100 percent. The person skilled in the art can also set the value of the second preset percentage, for example 0.2, 0.5 or 0.8, depending on the actual situation.

For example, in fig. 10, the area of the portion of the first virtual line segment where the first summation value is greater than 0.36 is smaller, the portion greater than 0.36 may be merged with the area of 0.35-0.36, that is, the area of point FC-point FD in the figure is the same sub-line segment.

If it is

If not, the sub-line segment formed by the part of the first virtual line segment between the NU-1 connecting line and the second end point FD and the sub-line segment formed by the part of the first virtual line segment between the NU-1 connecting line and the NU-1 connecting line are two different sub-line segments of the N sub-line segments; wherein the second difference value DeltaR _B-jc The difference value is a first summation value corresponding to the intersection of the second endpoint FD and the first virtual line segment, and a first summation value corresponding to the intersection of the NU connecting line and the first virtual line segment.

For example, in fig. 10, if the area of the portion of the first virtual line segment where the first sum value is less than 0.34 is large, the portion of the first virtual line segment less than 0.34 can be regarded as a sub-line segment different from the sub-line segment formed by 0.34 to 0.35, that is, in fig. 10, the first virtual line segment is divided into 3 sub-line segments (the sub-line segment between the point FA and the point FB, the sub-line segment between the point FB and the point FC, and the sub-line segment between the point FC and the point FD).

The point F1, the point F2, and the point F3 are feature coordinate points obtained from 3 sub-line segments, respectively.

The lookup table can be divided into several regions according to the error allowance parameter epsilon of the first summation value, the table is correspondingly divided into 3 regions if epsilon value is 0.01 ℃/W, and a typical heat flow path in each region is selected to represent the whole heat flow path in the region, specifically:

(1) x corresponding to point F1 ₁ Axial coordinate, y ₁ Axis coordinates are respectively P _loss ＝140W,htc＝200W.m ^-2 .℃ ^-1 ；

(2) X corresponding to point F2 ₁ Axial coordinate, y ₁ Axis coordinates are respectively P _loss ＝140W,htc＝5000W.m ^-2 .℃ ^-1 ；

(3) X corresponding to point F3 ₁ Axial coordinate, y ₁ Axis coordinates are respectively P _loss ＝140W,htc＝50000W.m ^-2 .℃ ^-1 。

The values of the thermal parameters under different boundary conditions are shown in table 2.

TABLE 2 thermal parameter values under typical boundary conditions

Step 6, establishing a thermal impedance model of the power module; the thermal impedance model is provided with a first node TU, a first element PU for representing the actual power loss of the chip, and N heat transfer branches which have the same structure and are mutually connected in parallel;

the temperature value of the first node TU is the measured temperature T of the bottom end of the power module _c (i.e., the position M on the first straight line at the bottom of the power module) _c Measured temperature of); one end of the first element PU is connected with the heat sink;

the thermal impedance model has N connection states; when the thermal impedance model is in the nth connection state, the other end of the first element PU and the first node TU are respectively and correspondingly connected with the two ends of the nth heat transfer branch so as to form a Cauer heat transfer network structure, N =1,2, \ 8230 \ 8230;, N.

The heat sink is connected with the heat sink, and a heat capacity element corresponding to the ith layer structure is connected between a node of the heat resistance element corresponding to the ith layer structure in the nth heat transfer branch, which is close to the first element PU, and the heat sink. And the temperature of a node, close to the first element PU, of the heat resistance element corresponding to the ith layer structure in the nth heat transfer branch is the temperature of a set measurement position of the ith layer structure to be determined.

In this embodiment, a thermal impedance network model considering the temperature influence may be finally obtained based on the circuit simulation software LTspice as shown in fig. 11.

As shown in fig. 11, the 3 dashed boxes are 3 heat transfer branches, respectively. In each heat transfer branch, R _chip 、R _solder1 、R _copper1 、R _ceramic 、R _copper2 、R _solder2 、R _baseplate Respectively corresponding to the 1 st, 2 nd, 82308230, 7 th layer structures, and C _chip 、C _solder1 、C _copper1 、C _ceramic 、C _copper2 、C _solder2 、C _baseplate The heat capacity elements respectively correspond to the layer 1 structure, the layer 2 structure, the layer 8230, and the layer 7 structure.

In FIG. 11, T ₁ 、T ₂ 、……T ₇ The temperatures of the set measurement positions corresponding to the 1 st layer structure, the 2 nd layer structure, \8230;, and the 7 th layer structure, respectively.

Although the same symbol is used in different heat transfer branches to represent the same layer structure, the thermal resistance R of the thermal resistance element corresponding to the ith layer structure in the nth heat transfer branch _i,n And a heat capacity C of the heat capacity element corresponding to the i-th layer structure _i,n It is calculated using the following expression.

When the actual convection heat dissipation coefficient at the bottom end of the power module is in the nth convection heat dissipation coefficient sub-range, the thermal impedance model is in the nth connection state;

wherein, the upper limit and the lower limit of the nth sub-range of the convection heat dissipation coefficient are respectively the distance x of the nth sub-line segment ₁ Convection heat dissipation coefficient corresponding to endpoint of coordinate axis, and approach x of nth sub-line segment ₁ Convection heat dissipation coefficients corresponding to the endpoints of the coordinate axes;

wherein, the thermal resistance R of the thermal resistance element corresponding to the ith layer structure in the nth heat transfer branch _i,n And a heat capacity C of the heat capacity element corresponding to the i-th layer structure _i,n The expression of (a) is as follows:

wherein d is _i Is the thickness of the i-th layer structure, K _i,n Is the thermal conductivity in the nth heat transfer branch corresponding to the material of the ith layer structure, c _i,n Specific heat capacity, A, corresponding to the material of the ith layer structure in the nth heat transfer branch _i,n Is the effective heat transfer area corresponding to the ith layer structure in the nth heat transfer branch, A _i,n,z Is prepared by mixing P _Loss,n 、htc _n The effective heat transfer area of the position, which is obtained after the second set temperature TB is applied to the finite element thermal simulation model established in the step 1 and has the distance z from the upper end surface of the ith layer structure in the height direction, is obtained;

wherein, K _i Indicating that the ith layer of material is at a temperature T' (i) _n The thermal conductivity, q, of the following _z(n) Is prepared by mixing P _Loss,n 、htc _n And a heat flow density P, which is obtained after the second set temperature TB is applied to the finite element thermal simulation model established in the step 1, is obtained at a position on the first straight line, wherein the distance between the ith layer structure and the upper end surface of the ith layer structure in the height direction is z, and the position is _Loss,n 、htc _n The convective heat dissipation coefficient and the power loss of the chip corresponding to the nth characteristic coordinate point are respectively _solder1 Is the upper surface area of the layer 2 structure.

In the application, when i is more than or equal to 3, the integral is utilized to solve the thermal resistance R _i,n And heat capacity C _i,n 。

The first set temperature TA is preferably an upper limit value of the chip operating temperature range. The second set temperature TB is preferably equal to the first set temperature TA or is preferably ambient temperature (e.g., 25 degrees), and may have other values within the chip operating temperature range.

T'(1) _n 、T'(2) _n Temperatures T of the set measuring positions of the 1 st layer structure to be determined corresponding to the nth heat transfer branch ₁ Temperature T of set measuring position of 2 nd layer structure to be determined ₂ Or T' (1) _n 、T'(2) _n Is prepared by mixing P _Loss,n 、htc _n And the second set temperature TB is obtained after the second set temperature TB is applied to the finite element thermal simulation model established in the step 1The temperature of the set measuring position of the 1 st layer structure, the temperature of the set measuring position of the 2 nd layer structure, wherein the second set temperature TB is the applied ambient temperature.

If the thermal resistance of the ith layer structure is temperature sensitive thermal resistance, K _i,n Temperature T for a set measurement position of an ith layer structure to be determined _i Otherwise, K _i,n Is a fixed value calculated from the third set temperature TC;

if the heat capacity of the i-th layer structure is a temperature sensitive heat capacity, c _i,n Temperature T for a set measuring point of an ith layer structure to be determined _i Otherwise, c _i,n Is a fixed value calculated from the third set temperature TC.

The third set temperature TC is preferably an ambient temperature constant value (e.g., 25 degrees).

The applicant finds in research that if all the layer thermal resistances and thermal capacitances are recalculated according to the actual temperature of the layer, the thermal impedance network will be iterated for a longer time, i.e. the simulation takes longer, but the accuracy is improved a little. In the application, for the temperature sensitive thermal resistance and the temperature sensitive heat capacity, the expression is obtained according to the actual temperature, namely, the formula I and the formula II can be adopted.

For example, in the embodiment, the thermal resistance of the chip layer is temperature sensitive thermal resistance, and in the thermal impedance model, the thermal resistance of the thermal resistance element corresponding to the layer 1 structure is represented as K _T(1) ＝438056.(T(1)+273.15) ^-1.4 And T (1) is the junction temperature to be solved, and is obtained by subsequent calculation in a thermal impedance model. Because the heat capacity of the heat capacity element corresponding to the layer 1 structure is a non-temperature-sensitive heat capacity, the third set temperature is substituted for T (1) into the specific heat capacity calculation formula of the formula II, so that a heat capacity value is obtained, and recalculation in a thermal impedance model is not needed.

Since the thermal resistance and the thermal capacity corresponding to the ceramic layer are both temperature-sensitive, the thermal resistance of the thermal resistance element and the thermal capacity of the thermal capacity element in the thermal impedance model can both adopt a formula I and a formula II as functions of the temperature T (4) of the set measuring position of the ceramic layer, and the value of the T (4) is obtained by calculation in the subsequent thermal impedance model.

And the non-temperature sensitive thermal resistance and the non-temperature sensitive thermal capacity are calculated according to a fixed third preset temperature (for example, 25 ℃) instead of the temperature T (i) of the set measuring position of the corresponding layer in the formula I and the formula II, namely the non-temperature sensitive thermal resistance and the non-temperature sensitive thermal capacity in the thermal impedance model can be calculated through the formula I and the formula II to obtain known values without subsequent iteration, so that the iterative operation time is greatly reduced, and the efficiency is improved.

3 thermal parameters R taking into account the temperature influence _chip 、R _ceramic And C _ceramic (the chip layer 1 thermal resistance, the ceramic layer 4 thermal resistance and the ceramic layer 4 thermal capacity are respectively shown) are iterated in real time in the thermal impedance model.

It is to be noted that, for thermal parameters that do not require consideration of the temperature influence, their thermal conductivity and specific heat capacity both take values at a temperature of 25 ℃.

The rated power of the chip can be determined according to practical conditions, for example, 100W is taken in the application.

Taking the nth characteristic coordinate point on the nth sub-line segment to ensure that the coordinate value of the nth characteristic coordinate point on the y1 axis is close to the x of the nth sub-line segment ₁ The value range of the difference between the coordinate values of the end points of the axes on the y1 axis is [30% × L ] _n ,70％×L _n ]，L _n The absolute value of the difference value of the coordinate values of the two end points of the nth sub-line segment on the y1 axis is N =1,2, \8230 \ 8230;, N.

The applicant finds that the value range of the difference value is [30% multiplied by L ] in research _n ,70％×L _n ]In time, the junction temperature estimation error is only 0.2 ℃ theoretically, and the actual requirement can be met.

Preferably, a value range of a difference between a coordinate value of the nth feature coordinate point on the y1 axis and a coordinate value of an end point of the nth sub-line segment close to the x1 axis on the y1 axis is [45% × L% _n ,55％×L _n ]。

More preferably, the coordinate value of the nth feature coordinate point on the y1 axis is close to the nth sub-line segment by x ₁ The difference between the coordinate values of the end points of the axes on the y1 axis is 50% xL _n 。

For example, in fig. 10, the 1 st sub-line segment is a line segment between the points FA and FB, the 1 st characteristic coordinate point is F1, and the 1 st sub-line segment is closer to and farther from x ₁ The end points of the axis are FA and FB, respectively.

In the invention, based on finite element steady-state thermal simulation which can be solved quickly, the corresponding relation between the boundary condition and the heat flow path (namely the path for transferring heat from the chip layer L1 to the substrate layer L7) is analyzed, thereby improving the applicability of the thermal impedance model.

In the invention, the method for improving the applicability of the thermal impedance model comprises the following steps: the method comprises the steps of providing an index (namely a first summation value) corresponding to a boundary condition and an influence heat flow path, establishing a lookup table corresponding to the boundary condition and the heat flow path by means of a finite element steady-state finite element thermal simulation model capable of being rapidly solved, and selecting typical heat flow paths from the lookup table to establish a thermal impedance network model with strong applicability under different boundary conditions.

In the invention, the influence of different boundary conditions on the heat flow path is analyzed. The boundary conditions include power loss P of the chip _Loss The convection heat dissipation coefficient htc at the bottom end of the power module and the ambient temperature T _a 。

It is believed that the ambient temperature does not affect the thermal behavior of the power module. Therefore, in the present application, the power loss P of the chip is mainly analyzed _Loss The influence of the bottom end of the power module on the convection heat dissipation coefficient htc on the heat transfer path, and when the first summation value is calculated, the applied environment temperature is set to be a fixed value (namely, the ambient temperature can be set to be a normal temperature value of the environment temperature).

N is more than or equal to 2 and less than or equal to 10. In a preferred embodiment, 3N 5.

The power module is one of a diode module, a MOSFET module, an IGBT module and a thyristor module.

The invention provides a junction temperature estimation method, which comprises the following steps:

applying actual power loss of a chip in the finite element thermal simulation model established in the step 1 of the power module thermal impedance model modeling method, and adjusting the value of the convective heat dissipation coefficient of the bottom end of the power module applied in the finite element thermal simulation model until the difference between the temperature of the bottom end of the power module obtained in the finite element thermal simulation model and the temperature of the bottom end of the actually measured power module is not larger than a preset temperature error value;

taking the value of the convection heat dissipation coefficient at the bottom end of the power module obtained after adjustment as the actual convection heat dissipation coefficient at the bottom end of the power module, enabling the thermal impedance model to be in a connection state corresponding to the convection heat dissipation coefficient sub-range according to the convection heat dissipation coefficient sub-range to which the actual convection heat dissipation coefficient at the bottom end of the power module belongs, taking the temperature at the other end of the first element PU obtained according to the thermal impedance model as the junction temperature of the chip, wherein the junction temperature of the chip is the temperature T of the set measurement position of the layer 1 structure to be determined ₁ (ii) a And in the actual space, the bottom end of the power module is provided with a radiator with fixed output power.

The preset temperature error value may be determined according to the requirement of the accuracy of the estimation of the junction temperature of the chip, for example, if the requirement of the accuracy of the estimation of the junction temperature of the chip is 1 ℃, the preset temperature error value may be set to be 0.1 ℃, 0.2 ℃ or the like.

The present invention also provides a computer apparatus comprising: a memory for storing a computer program; a processor for implementing the steps of the power module thermal impedance model modeling method as described above and/or the steps of the junction temperature estimation method as claimed in claim 8 when executing the computer program.

The invention also provides a storage medium having stored thereon a computer program which, when executed by a processor, carries out the steps of the power module thermal impedance model modeling method as described above and/or the steps of the junction temperature estimation method as claimed in claim 8.

In the invention, the whole area is divided into a plurality of parts (the first virtual line segment is respectively N sub-line segments), each part takes a typical value (namely a characteristic coordinate point), namely, the boundary condition corresponding to the characteristic coordinate point is used for representing the boundary condition covered by the sub-line segment, so that the problems of low processing speed and low efficiency caused by repeated finite element simulation when the boundary condition is replaced in practice can be avoided. In the present application, when N =3, the branches of the thermal impedance network under 3 typical operating conditions can be established in advance, so that the whole boundary condition can be applied, and the junction temperature estimation error is also within an allowable range.

In the prior art, a finite element thermal simulation model is established according to the size and coordinates of a packaging structure in a power module, and a dynamic temperature curve of each node (namely, each layer of set measurement position) can be obtained in the finite element transient thermal simulation model, so that thermal resistance and thermal capacity parameters are extracted, a thermal network model is established, and the temperature (namely, junction temperature) of the layer 1 set measurement position is obtained. However, if the operating conditions of the power module (e.g., external cooling conditions, power of the power module during operation) are changed, the boundary conditions (e.g., external cooling conditions, power of the power module during operation) applied in the finite element simulation need to be adjusted accordingly, resulting in long simulation time and inefficient junction temperature estimation.

Different from the traditional method for establishing a heat network considering boundary conditions by utilizing finite element transient thermal simulation, the method provided by the invention does not need to calculate a large number of values of the heat capacity element and the heat resistance element corresponding to each layer structure under different boundary conditions, only needs finite element steady state simulation information, greatly reduces the simulation time cost and simplifies the modeling process. Specific time cost comparisons are shown in table 3. Compared with the traditional method, the method provided by the invention reduces the simulation time by about 60%.

TABLE 3 comparison of finite element simulation time consumption between the conventional method and the method of the present invention

A flow chart of a fast robust power module thermal impedance model modeling method considering material temperature characteristics is shown in fig. 12.

In order to prove the effectiveness of the method, experimental verification is carried out. The power module FF150R12ME3G is installed on an air-cooled radiator, the equivalent convective heat dissipation coefficient htc at the bottom end of the power module can be changed by adjusting the rotating speed of a fan (namely the radiator), and the equivalent convective heat dissipation coefficient htc is subjected to comparative calibration with finite element simulation (namely the equivalent convective heat dissipation coefficient htc is obtained by applying a chip which is the same as the actual chip in a finite element thermal simulation model)Power loss value, and adjusting the convective heat dissipation coefficient at the bottom end of the power module until the bottom end temperature of the power module in the finite element thermal simulation model is the same as the actually measured bottom end temperature), and natural heat dissipation, that is, the convective heat dissipation coefficient htc =400W · m at the bottom end of the power module when the fan is 0 ^-2 ·℃ ^-1 Htc =3600W · m in forced air cooling ^-2 ·℃ ^-1 Wherein the experimental ambient temperature measured is 25 ℃. Adopting a FORTIC326Pro thermal imager to carry out infrared temperature measurement on the power module subjected to black paint treatment, wherein the maximum error is +/-1 ℃, and simultaneously measuring the shell temperature T of the power module by using a thermocouple _c 。

Fig. 13 (a), fig. 13 (b), and fig. 13 (c) are graphs comparing the junction temperature measured by the infrared camera and the estimation method of the present invention when the load current I =30A, I =40A, I =50A according to the embodiment of the present invention, respectively; fig. 14 (a), 14 (b), and 14 (c) show cooling capacities htc =3600w.m, respectively, in the example of the present invention ^-2 .℃ ^-1 、htc＝860W.m ^-2 .℃ ^-1 、htc＝400W.m ^-2 .℃ ^-1 Comparing the junction temperature measured by the infrared camera with the junction temperature measured by the estimation method of the invention;

the results of fig. 13 and 14 show that the peak errors of the thermal impedance model and the experiment proposed by the present invention are within 1.3 ℃ no matter under different power (current) conditions, different cooling conditions, or in a higher junction temperature region, and since the measurement error of the thermal imager is 1 ℃, it can be known that the junction temperature estimation accuracy of the junction temperature estimation method proposed by the present invention is not more than 2.3 ℃ in the higher junction temperature region. The reason for the error in the valley value is that the infrared measurement result is affected by the reflection temperature, and the obtained measurement value is smaller than the true value, so the error is larger. Overall, the proposed thermal impedance model is able to accurately estimate the junction temperature of the module at different boundary conditions. Meanwhile, as can be seen from fig. 13, the proposed model can accurately simulate the thermal response of the high-temperature region of the power module, which shows that the model can effectively solve the problem of temperature dependence of the packaging material.

FIG. 15 (a), FIG. 15 (b), FIG. 15 (c) and FIG. 15 (d) are the environmental temperatures T of the embodiment of the present invention _a =40 ℃ ambient temperatureT _a =60 ℃ and ambient temperature T _a =80 ℃ and ambient temperature T _a =100 ℃ the junction temperature estimation method of the invention and the junction temperature estimation result obtained by finite element simulation method are shown schematically, wherein, P _Loss ＝100，htc＝5000。

The finite element simulation method is to apply the ambient temperature to a finite element thermal simulation model and directly obtain a junction temperature estimation result by utilizing finite element simulation.

In the application, the thermal conductivity of each layer structure is obtained by adopting a fixed first set temperature, and the structures obtained by applying each group of parameters to the finite element thermal simulation model are combined to calculate a first summation value, although the three-dimensional curved surfaces have differences when the environmental temperatures are different, so that the first virtual line segment and the divided sub-line segments are different, as seen from the results of fig. 15 (a), 15 (b), 15 (c) and 15 (d), the junction temperature estimation result of the method is smaller than the junction temperature estimation result of the finite element thermal simulation model at different environmental temperatures. Specifically, under different ambient temperatures, the maximum error between the junction temperature estimated by the method and the finite element result is not more than 0.8 ℃, which shows that the method can accurately represent the thermal behavior of the power device under different ambient temperatures, and simultaneously verifies that the ambient temperature has little influence on the thermal behavior of the power device, and the influence of the ambient temperature can be ignored when the influence of the boundary conditions on the heat flow path is analyzed.

The invention provides a rapid robust power module thermal impedance model modeling method considering material temperature characteristics. Aiming at the disadvantages that the traditional thermal impedance model has longer time consumption for parameter extraction and the calculation accuracy of the effective heat transfer area is low due to the adoption of a thermal diffusion angle with lower accuracy, the invention corrects the effective heat transfer area of each layer based on the finite element steady-state thermal simulation result which can be quickly solved; meanwhile, the temperature characteristic of the packaging material is considered, and a thermal impedance model considering the temperature influence is constructed; on the basis, the influence of boundary conditions (including power loss and cooling conditions) on an effective heat transfer path is considered, and the applicability of model parameters under different boundary conditions is further improved. The method provided by the invention considers the influence of temperature and boundary conditions on thermal parameters on the basis of correcting the effective heat transfer area, is beneficial to improving the accuracy and reliability of junction temperature monitoring of the power module, and can be suitable for the power module to operate in a high-temperature area and different boundary conditions for a long time.

The method is actually an improved thermal impedance modeling model, and model parameters are rapidly and accurately obtained; the applicability of the model under different conditions is improved; the junction temperature can be accurately estimated when the high-temperature region works by taking the influence of the temperature into consideration.

Example 2

The present embodiment 2 differs from embodiment 1 in that:

K _i,n temperature T for a set measurement position of an ith layer structure to be determined _i A function of c _i,n Temperature T for a set measuring point of an ith layer structure to be determined _i . Namely, the thermal resistance and the thermal capacity of each layer of structure are represented by the expressions of the first formula and the second formula in the first embodiment, and the temperature to be estimated is obtained in the actual thermal impedance model through iteration.

Example 3

The present example 3 differs from the example 1 in that: the values of htc (1) are such that: when the power loss of the chip is P _Loss (PA), the convection heat dissipation coefficient of the bottom end of the power module is not less than htc (1), and the ambient temperature is normal temperature, the temperature of the set measuring position of the 1 st layer structure is not more than the upper limit of the working temperature of the chip.

The htc (1) can be selected by the following method: will P _Loss (PA) and ambient temperature are applied to the finite element thermal simulation model in the step 1 at normal temperature, the convective heat dissipation coefficient of the bottom end of the power module applied to the finite element thermal simulation model is adjusted until the temperature of the set measuring position of the layer 1 structure obtained according to the finite element thermal simulation model is not more than the upper limit of the working temperature of the chip, and the convective heat dissipation coefficient of the bottom end of the power module obtained after adjustment is used as the value of htc (1).

A person skilled in the art may set a preset range of the convective heat dissipation coefficient at the bottom end of the power module, which reflects the heat dissipation condition of the heat sink, according to the upper limit of the working temperature of the actual chip, for example, the preset range may be selected to be 1000-10000, so as to ensure that the working temperature is not greater than the maximum bearing temperature (e.g., 150 degrees) of the chip during working.

It should be noted that, in this specification, each embodiment is described in a progressive manner, and each embodiment focuses on differences from other embodiments, and portions that are the same as and similar to each other in each embodiment may be referred to.

The embodiments of the present invention have been described in detail, but the description is only for the preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. All equivalent changes and modifications made within the scope of the present invention should be covered by this patent. Various equivalent modifications of the invention, which fall within the scope of the appended claims of this application, will be suggested to those skilled in the art after reading this disclosure. The embodiments and features of the embodiments of the present invention may be combined with each other without conflict.

Claims

1. A power module thermal impedance model modeling method is characterized in that: the power module thermal impedance model modeling method comprises the following steps:

and 2, step: let HA value htc (1), htc (2), \8230;, one of Htc (HA) and PA value P _Loss (1)、P _Loss (2)、……、P _Loss (PA) one value of which constitutes a set of parameters, thus obtaining a HA x PA set of parameters, said HA value being a predetermined range of convective heat dissipation coefficients from the bottom of the power module [ htc (1), htc (HA) ]]Values of successively increasing values selected in the range, PA, of a predetermined range [ P ] of power loss from the chip _Loss (1),P _Loss (PA)]The values selected in the system are sequentially increased, and HA and PA are preset values;

respectively applying the HA multiplied by PA group parameters to the finite element thermal simulation model, taking the set value of the environment temperature as the environment temperature applied to the finite element thermal simulation model, and according to the simulation result of the finite element thermal simulation model and the K _i,TA To obtain HA × PA first summation values R _jc(1) 、R _jc(2) 、……、R _jc(HA×PA) Wherein

Wherein m =1,2, \8230;, HA × PA, K _1,TA 、K _2,TA 、……、K _7,TA The first set temperature TA indicates the thermal conductivity of the materials of the 1 st, 2 nd, 8230, 7 th layer structures, d ₁ 、d ₂ 、……、d ₇ The thickness of the layer 1 structure, the layer 2 structure, \8230 \8230andthe layer 7 structure respectively; t1 _m 、T2 _m The set measurement positions of the layer 1 structure and the layer 2 structure obtained by applying the mth group of parameters to the finite element thermal simulation model are respectively the temperature, the set measurement positions of each layer of structure are all positioned on a first straight line parallel to the height direction of the power module, and K (T1) _m ) Is expressed with a temperature T1 _m Corresponding thermal conductivity of the material of the layer 1 structure, A _solder1 Is the surface area of the 2 nd layer structure, P _Loss(m) For the power loss of the chip in the m-th set of parameters, q _m (i, z) is the heat flow density of a position, which is obtained by applying the mth group of parameters to the finite element thermal simulation model, is in the ith layer structure, has a height direction distance z from the upper end face of the ith layer structure, and is positioned on the first straight line;

and 5: mapping three-dimensional surfaces in an oxyz coordinate system to o ₁ x ₁ y ₁ In the coordinate system, obtaining a first mapping result, wherein the x-axis coordinate, the y-axis coordinate and the x-axis coordinate ₁ Axial coordinate, y ₁ The axis coordinates correspond to o, and the z-axis coordinate corresponds to ₁ x ₁ y ₁ Characteristic values of coordinate points in a coordinate system;

at o ₁ x ₁ y ₁ In the coordinate system, the characteristic value in the first mapping result is equal to R _jc,1 The points are connected to form a 1 st connecting line, and the characteristic value in the first mapping result is equal to R _jc,2 The points are connected to form a 2 nd connecting line, \8230, the characteristic value in the first mapping result is equal to R _jc,NA Forming a NA connecting line by connecting the points to obtain the NA connecting line; NA first setting values R _jc,1 、R _jc,2 、……、R _jc,NA Equidistant and numerical values are increased in sequence;

dividing the first virtual line segment into N sub-line segments according to each connection line in the NA connection lines with the intersection point of the first virtual line segment, wherein N is more than or equal to 2 and less than or equal to 10; n is a preset value, the value of NA is determined by the value of N, and the values of the NA first set values are determined according to the value of NA and the numerical range of the HA multiplied by PA first summation values; the sum of the lengths of the N sub line segments is the length of the first virtual line segment; the first end point (FA) and the second end point (FD) of the first virtual line segment are at x ₁ The axial coordinates are all P _Loss (P1) at y ₁ Coordinates on the axis are htc (1) and Htc (HA) respectively; p _Loss (P1) is the rated power of the chip, P _Loss (P1)≤P _Loss (PA)；

Step 6: establishing a thermal impedance model of the power module; the thermal impedance model is provided with a first node (TU), a first element (PU) for representing the actual power loss of the chip, and N heat transfer branches which are identical in structure and are mutually connected in parallel; the temperature value of the first node (TU) is the measured temperature at the bottom end of the power module; one end of the first element (PU) is connected with the heat sink;

the thermal impedance model has N connection states; when the actual convection heat dissipation coefficient of the bottom end of the power module is in the nth convection heat dissipation coefficient sub-range, the thermal impedance model is in an nth connection state, and the other end of the first element (PU) and the first node (TU) are correspondingly connected with the two ends of the nth heat transfer branch respectively, so that a Cauer heat transfer network structure is formed;

the temperature of a node, close to a first element (PU), of a thermal resistance element corresponding to the ith layer structure in the nth heat transfer branch is the temperature of a set measurement position of the ith layer structure to be determined; the upper limit and the lower limit of the nth sub-range of the convective heat dissipation coefficient are respectively the distance x of the nth sub-line segment ₁ End of coordinate axis, close to x ₁ Convection heat dissipation coefficients corresponding to the endpoints of the coordinate axes;

wherein, the thermal resistance R of the thermal resistance element corresponding to the ith layer structure in the nth heat transfer branch _i,n And a heat capacity C of the heat mass corresponding to the i-th layer structure _i,n The expression of (a) is as follows:

wherein d is _i Is the thickness of the i-th layer structure, K _i,n Is the thermal conductivity in the nth heat transfer branch corresponding to the material of the ith layer structure, c _i,n The specific heat capacity of the nth heat transfer branch corresponding to the material of the ith layer structure; q. q.s _i,n,z Is prepared by adding P _Loss,n 、htc _n Applying a second set temperature TB to the heat flow density of the set measuring position of the i-th layer structure obtained after the finite element thermal simulation model established in the step 1, wherein the second set temperature TB is the applied environment temperature, P _Loss,n 、htc _n The convective heat dissipation coefficient and the power loss of the chip corresponding to the nth characteristic coordinate point are respectively _solder1 The surface area of the layer 2 structure is O ₁ x ₁ y ₁ Coordinate points in a coordinate system;

wherein the nth characteristicThe coordinate point is located on the nth sub-line segment, and the coordinate value of the nth characteristic coordinate point on the y1 axis is close to the x of the nth sub-line segment ₁ The value range of the difference between the coordinate values of the end points of the axes on the y1 axis is [30% × L ] _n ,70％×L _n ]，L _n The absolute value of the difference value of coordinate values of two endpoints of the nth sub-line segment on the y1 axis is N =1,2, \8230;, N;

T'(1) _n 、T'(2) _n temperatures T of the set measuring positions of the 1 st layer structure to be determined corresponding to the nth heat transfer branch ₁ Temperature T of a set measurement position of a 2 nd layer structure to be determined ₂ Or T' (1) _n 、T'(2) _n Is prepared by mixing P _Loss,n 、htc _n Applying a second set temperature TB to the temperature of the set measuring position of the layer 1 structure and the temperature of the set measuring position of the layer 2 structure obtained after the finite element thermal simulation model established in the step 1 is applied;

(A)K _i,n temperature T for a set measuring point of an ith layer structure to be determined _i A function of c _i,n Temperature T for a set measurement position of an ith layer structure to be determined _i A function of (a); or alternatively

(B) If the thermal resistance of the ith layer structure is temperature sensitive thermal resistance, K _i,n Temperature T for a set measurement position of an ith layer structure to be determined _i Otherwise, K _i,n Is a fixed value calculated from the third set temperature TC; if the heat capacity of the i-th layer structure is a temperature sensitive heat capacity, c _i,n Temperature T for a set measurement position of an ith layer structure to be determined _i Otherwise, c _i,n Is a fixed value calculated from the third set temperature TC.

2. The power module thermal impedance model modeling method of claim 1, wherein: the first set temperature TA is a value selected from the range of the working temperature of the chip;

preferably, the first set temperature TA is an upper limit value of the chip operating temperature range.

3. The power module thermal impedance model modeling method of claim 1, wherein: in the step 5:

R _jc,1 ≥R _jc-min and R is _jc,NA ≤R _jc-max Wherein, the difference value of two adjacent first set values is a fixed value Δ R _jc ，R _jc-max Is the maximum value, R, of the HA × PA first summation values _jc-min Is the minimum of the HA x PA first summation values,

and is provided with

ε ₁ Is a first preset percentage;

if it is

If not, the sub-line segment formed by the part of the first virtual line segment between the U2-th connecting line and the first end point (FA) and the sub-line segment formed by the part of the first virtual line segment between the U1-th connecting line and the first end point (FA) and the sub-line segment formed by the part of the first virtual line segment between the U2-th connecting line and the U1-th connecting line are two different sub-line segments of the N sub-line segments; wherein the first difference value DeltaR _A-jc A difference value between a first summation value corresponding to an intersection point of the U1-th connecting line and the first virtual line segment and a first summation value corresponding to a first endpoint (FA); epsilon ₂ Is a second preset percentage;

if it is

If not, the sub-line segment formed by the part of the first virtual line segment between the NU-1 connecting line and the second end point (FD) and the sub-line segment formed by the part of the first virtual line segment between the NU-1 connecting line and the NU-1 connecting line are two different sub-line segments of the N sub-line segments; wherein the second difference value Δ R _B-jc Is the difference between a first summation value corresponding to the intersection of the second endpoint (FD) and the first virtual line segment and a first summation value corresponding to the intersection of the NU line and the first virtual line segment.

4. The power module thermal impedance model modeling method of any of claims 1-3, wherein:

if the variation amplitude of the thermal resistance of the ith layer structure in the set environment temperature range is more than a third preset percentage epsilon ₃ Judging that the thermal resistance of the ith layer structure is temperature sensitive thermal resistance;

if the variation range of the heat capacity of the ith layer structure in the set environment temperature range is more than a fourth preset percentage epsilon ₄ Judging that the heat capacity of the ith layer structure is temperature sensitive heat capacity;

preferably, the method for determining whether the thermal resistance of the ith layer structure is the temperature-sensitive thermal resistance and the heat capacity of the ith layer structure is the temperature-sensitive heat capacity comprises the following steps:

let htc1, P _Loss1 Applying the heat resistance to the finite element thermal simulation model established in the step 1, changing the applied environment temperature in the finite element thermal simulation model within a set environment temperature range, calculating the heat resistance and heat capacity of each layer structure, and calculating the heat resistance of each layer structure and the heat capacity of each layer structure at each applied environment temperature, thereby determining whether the heat resistance of each layer structure is temperature sensitive heat resistance and determining whether the heat capacity of each layer structure is temperature sensitive heat capacity;

wherein htc1 is the bottom end pair of the power modulePredetermined value of heat dissipation coefficient of flow, P _Loss1 Is a preset value of the power loss of the chip.

5. The power module thermal impedance model modeling method of any of claims 1-3, wherein: the value of htc (1) is such that: when the power loss of the chip is P _Loss (PA), when the convection heat dissipation coefficient of the bottom end of the power module is not less than htc (1) and the ambient temperature is normal temperature, the temperature of the set measuring position of the layer 1 structure is not more than the upper limit of the working temperature of the chip;

preferably, the htc (1) is selected by the following method: will P _Loss (PA) and ambient temperature are applied to the finite element thermal simulation model in the step 1 at normal temperature, the bottom end convection heat dissipation coefficient of the power module applied to the finite element thermal simulation model is adjusted until the temperature of the set measuring position of the layer 1 structure obtained according to the finite element thermal simulation model is not more than the upper limit of the working temperature of the chip, and the adjusted bottom end convection heat dissipation coefficient of the power module is used as the value of htc (1).

6. The power module thermal impedance model modeling method of any of claims 1-3, wherein: coordinate value of nth feature coordinate point on y1 axis and approaching x of nth sub-line segment ₁ The end point of the shaft is at y ₁ The value range of the difference between the coordinate values on the axis is [45% × L ] _n ,55％×L _n ]；

Preferably, the coordinate value of the nth feature coordinate point on the y1 axis is close to the nth sub-line segment by x ₁ The difference between the coordinate values of the end points of the axes on the y1 axis is 50% xL _n 。

7. The power module thermal impedance model modeling method of any of claims 1-3, wherein: the position M1 of the upper surface of the 1 st layer structure, the position M2 of the upper surface of the 2 nd layer structure, the position M3 of the upper surface of the 3 rd layer structure, the position M5 of the upper surface of the 5 th layer structure, the position M6 of the upper surface of the 6 th layer structure, and the position M7 of the upper surface of the 7 th layer structure correspond to the position M1 of the upper surface of the 1 st layer structure, the position M5 of the upper surface of the 5 th layer structure, the position M6 of the upper surface of the 6 th layer structure, and the position M7 of the upper surface of the 7 th layer structure, respectively,Setting measurement positions of a 5 th layer structure, a 6 th layer structure and a 7 th layer structure, wherein M4 is the setting measurement position of the 4 th layer structure, and the height difference between the position of the M4 and the lower surface of the 4 th layer structure ranges from [30% × d ] ₄ ,70％×d ₄ ]Positions M1, M2, M3, M4, M5, M6 and M7 are all positioned on a first straight line;

preferably, the first straight line passes through the central position of the upper surface of the layer 1 structure;

preferably, the height difference between the position of M4 and the lower surface of the layer 4 structure is 50% multiplied by d ₄ 。

8. A method of estimating junction temperature, the method comprising:

in the finite element thermal simulation model established in step 1 of the power module thermal impedance model modeling method of any of claims 1-7, applying a power loss of an actual chip, and adjusting a value of a convective heat dissipation coefficient at a bottom end of the power module applied in the finite element thermal simulation model until a difference between a temperature at the bottom end of the power module obtained in the finite element thermal simulation model and a temperature at the bottom end of the measured power module is not greater than a preset temperature error value;

taking the value of the convection heat dissipation coefficient at the bottom end of the power module obtained after adjustment as the actual convection heat dissipation coefficient at the bottom end of the power module, so that the thermal impedance model is in a connection state corresponding to the convection heat dissipation coefficient sub-range according to the convection heat dissipation coefficient sub-range to which the actual convection heat dissipation coefficient at the bottom end of the power module belongs, and taking the temperature at the other end of the first element (PU) obtained according to the thermal impedance model as the junction temperature of the chip;

and in the actual space, the bottom end of the power module is provided with a radiator with fixed output power.

9. A computer device, comprising: a memory for storing a computer program; a processor for implementing the steps of the power module thermal impedance model modelling method of any of claims 1 to 7 and/or the steps of the junction temperature estimation method of claim 8 when executing the computer program.

10. A storage medium having stored thereon a computer program which, when executed by a processor, carries out the steps of the power module thermal impedance model modelling method of any of claims 1 to 7 and/or the steps of the junction temperature estimation method of claim 8.