CN116738804B - Power module life prediction method based on failure physics - Google Patents
Power module life prediction method based on failure physics Download PDFInfo
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Abstract
The invention discloses a power module life prediction method based on failure physics, which comprises the steps of establishing a power module three-dimensional finite element model, carrying out temperature field simulation under the condition of uniformly applying chip power loss to obtain the original temperature distribution of a chip at the current stage, introducing the original temperature distribution into a chip cell-level model established in Matlab, introducing the corrected chip power loss distribution into a chip active area in finite element analysis to carry out thermal coupling simulation to obtain the corrected module temperature distribution at the current stage and the plastic strain energy density distribution of a solder layer, and calculating the module thermal resistance at the current stage and the module life at the current stage by combining the corrected chip power loss; when the current stage is not the first stage, if the ratio of the thermal resistance of the module in the current stage to the thermal resistance of the module in the first stage is larger than a preset threshold value, outputting the service life of the module according to the service life of each stage. The ageing process of the solder layer can be more accurately simulated; the service life prediction precision is higher; has good universality.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a power module life prediction method based on failure physics.
Background
The power semiconductor module is widely applied to important fields such as renewable energy inverters, motor driving of electric automobiles, locomotive traction and the like. However, reliability problems are increasingly prominent. The chip solder layer is one of the weakest parts in the power module, and the solder layer can be degraded under the action of long-term thermal stress, so that the thermal resistance of the module is increased, and finally the thermal runaway of the module is caused to fail. Therefore, accurate life prediction of the power module solder layer is of great importance for reducing non-downtime maintenance time and reducing maintenance costs of the power conversion system.
The aging of the solder layer in the power module is a result of the multi-factor mutual coupling of uneven temperature distribution on the surface of the chip, initial defects in the solder layer, uneven stress distribution in the solder layer, and the like. Each solder layer has its own independent aging process. However, in the conventional life prediction method, when finite element simulation is performed on a power module, most of the conventional life prediction method uses the whole chip as a uniform constant heat source, the solder layer is set to be an ideal solder layer without initial defects, and the change of power loss distribution caused by the change of chip surface temperature distribution in the aging process of the solder layer is not considered, so that the difference of the aging process of the solder layer cannot be reflected. The power semiconductor chip is a multi-cell structure, and the loss of each cell is different in the running process of the chip. In addition, the solder layer of the power module contains a large number of tiny holes, the holes can also affect the temperature distribution of the chip surface, and the temperature distribution of the chip surface can also change along with the aging of the solder layer, so that the temperature distribution of the actual chip surface is far more complicated than that of the whole chip serving as a uniform constant heat source. The micro-voids inside the solder layer can also cause severe non-uniformity in the thermal stress distribution of the solder layer. Therefore, providing a life prediction method that considers the influence of uneven chip surface temperature distribution and uneven solder layer stress distribution on the aging process of the solder layer and the variation of chip power loss distribution in the aging process of the solder layer becomes a problem to be solved in the prior art.
Disclosure of Invention
Aiming at the technical problems that the prior life prediction method does not consider the influences of uneven chip surface temperature distribution and uneven solder layer stress distribution on the aging process of a solder layer and the power loss distribution change of the chip in the aging process of the solder layer, the invention provides a power module life prediction method based on failure physics.
The technical scheme adopted for solving the technical problems is as follows:
a power module life prediction method based on failure physics includes the following steps:
s100: establishing a power module three-dimensional finite element model with a solder layer containing a distributed initial cavity through CT scanning;
s200: under the condition of uniformly applying the power loss of the chip, carrying out temperature field simulation to obtain the original temperature distribution of the chip at the current stage;
s300: the original temperature distribution of the chip at the current stage is imported into a chip cell-level model established in Matlab to calculate cell power loss at different positions of the chip;
s400: the corrected chip power loss distribution is led into a chip active region in finite element analysis to carry out thermal coupling simulation, so that the module temperature distribution and the solder layer plastic strain energy density distribution corrected at the current stage are obtained;
s500: calculating the module thermal resistance of the current stage and the module service life of the current stage according to the corrected module temperature distribution of the current stage, the corrected chip power loss and the plastic strain energy density distribution of the solder layer;
s600: when the current stage is not the first stage, judging whether the ratio of the module thermal resistance of the current stage to the module thermal resistance of the first stage is larger than a preset threshold, if not, eliminating the grid with the maximum plastic strain energy density of the current stage, entering the next stage, carrying out temperature field simulation to obtain the original temperature distribution of the next stage, returning to S300 until the ratio of the module thermal resistance of the corresponding stage to the module thermal resistance of the first stage is larger than the preset threshold, and outputting the service life of the module according to the service life of each stage.
Preferably, S100 includes:
and obtaining a three-dimensional microstructure of the solder layer of the power module chip through CT scanning, carrying out statistical analysis on initial voids in the solder layer, and establishing a three-dimensional finite element model of the power module containing distributed initial voids in the solder layer, wherein the modeling of the power module chip is divided into a terminal area, a gate area and an active area.
Preferably, S500 includes:
s510: calculating the module thermal resistance of the current stage according to the corrected module temperature distribution of the current stage and the corrected chip power loss, and deriving the plastic strain energy density of each grid of the solder layer of the current stage according to the plastic strain energy density distribution of the solder layer of the current stage;
s520: and sequencing the plastic strain energy density of each grid of the solder layer at the current stage from large to small to obtain the plastic strain energy density of the grid with the maximum plastic strain energy density at the current stage, and calculating the service life at the current stage according to the crack initiation energy of the solder layer material, the plastic strain energy density of the grid with the maximum plastic strain energy density at the current stage, the plastic strain energy density of each previous stage of the grid with the maximum plastic strain energy density at the current stage and the service life of each previous stage.
Preferably, in S510, calculating the thermal resistance of the module at the current stage according to the corrected temperature distribution of the module at the current stage and the corrected power consumption of the chip includes:
acquiring the chip temperature and the shell temperature right below the chip in the current stage according to the corrected module temperature distribution in the current stage;
the thermal resistance of the module at the current stage is obtained by calculation according to the junction temperature of the chip at the current stage, the temperature of the shell right below the chip and the corrected power loss of the chip, and the thermal resistance of the module at the current stage is specifically:
；
wherein ,is->Stage chip junction temperature, < >>Is->Temperature of shell right below chip stage +.>First->Phase corrected chip power loss, +.>Is->And (5) stage module thermal resistance.
Preferably, when the current stage is the first stage, the plastic strain energy density of the grid with the maximum plastic strain energy density of the current stage in each previous stage and the life of each previous stage are zero, and the current stage life is calculated according to the crack initiation energy of the solder layer material, the plastic strain energy density of the grid with the maximum plastic strain energy density of the current stage in each previous stage and the life of each previous stage in S520, specifically:
；
wherein ,crack initiation energy for solder layer material, +.>For the first phase life, +.>Is the plastic strain energy density on the grid where the plastic strain energy density is the greatest in the first stage solder layer.
Preferably, when the current stage is not the first stage, the current stage lifetime is calculated in S520 according to the crack initiation energy of the solder layer material, the plastic strain energy density of the grid with the maximum plastic strain energy density of the current stage, the plastic strain energy density of each previous stage of the grid with the maximum plastic strain energy density of the current stage, and the lifetime of each previous stage, specifically:
；
wherein ,crack initiation energy for solder layer material, +.>Is->Plastic strain energy density on grid with maximum plastic strain energy density in stage solder layer, +.>Is->The grid with the maximum plastic strain energy density in the solder layer in the stage is at the +.>Plastic strain energy density at stage, +.>Is->Stage module lifetime, wherein->。
Preferably, in S600, the ratio of the thermal resistance of the corresponding stage module to the thermal resistance of the first stage module is greater than a preset threshold, specifically:
；
wherein ,is the first stage module thermal resistance.
Preferably, in S600, the module life is output according to each stage life, specifically:
；
wherein ,for the life of the module->The number of stages experienced at the end of the cycle.
According to the power module service life prediction method based on failure physics, the influences of uneven chip temperature distribution and solder layer stress distribution on the solder layer aging process caused by multi-factor mutual coupling are considered, and the solder layer aging process can be simulated more accurately; the change of the power loss distribution of the chip in the aging process of the solder layer is considered, so that the life prediction precision is higher; the solder material can be applied to modules of different packages of the same solder material, and has good universality.
Drawings
FIG. 1 is a flowchart of a power module life prediction method based on failure physics according to an embodiment of the invention;
FIG. 2 is a three-dimensional scan of a power module chip solder layer obtained by a CT scanner in accordance with an embodiment of the present invention;
FIG. 3 is a three-dimensional finite element model of a power module constructed in an embodiment of the present invention;
FIG. 4 is a diagram of a three-dimensional finite element model of a solder layer in a three-dimensional finite element model of a power module for power creation in accordance with an embodiment of the present invention;
FIG. 5 is a diagram showing a calibration of a chip surface temperature distribution in a finite element according to an embodiment of the present invention;
FIG. 6 is a grid division of a solder layer in a finite element according to an embodiment of the present invention;
FIG. 7 is a graph showing a comparison of a predicted lifetime of a power module and a lifetime obtained by an actual aging test according to an embodiment of the present invention.
Detailed Description
In order to make the technical scheme of the present invention better understood by those skilled in the art, the present invention will be further described in detail with reference to the accompanying drawings.
In one embodiment, as shown in fig. 1, a power module life prediction method based on failure physics, the method includes the following steps:
s100: and establishing a power module three-dimensional finite element model with a solder layer containing a distributed initial cavity through CT scanning.
In one embodiment, S100 comprises:
and obtaining a three-dimensional microstructure of the solder layer of the power module chip through CT scanning, carrying out statistical analysis on initial voids in the solder layer, and establishing a three-dimensional finite element model of the power module containing distributed initial voids in the solder layer, wherein the modeling of the power module chip is divided into a terminal area, a gate area and an active area.
S200: and (3) carrying out temperature field simulation under the condition of uniformly applying the power loss of the chip to obtain the original temperature distribution of the chip at the current stage.
S300: and (3) importing the original temperature distribution of the chip at the current stage into a chip cell-level model established in Matlab to calculate cell power loss at different positions of the chip.
S400: and (3) introducing the corrected chip power loss distribution into a chip active region in finite element analysis to perform thermal coupling simulation, so as to obtain the module temperature distribution corrected at the current stage and the plastic strain energy density distribution of the solder layer.
S500: and calculating the module thermal resistance of the current stage and the module service life of the current stage according to the corrected module temperature distribution of the current stage, the corrected chip power loss and the plastic strain energy density distribution of the solder layer.
In one embodiment, S500 includes:
s510: calculating the module thermal resistance of the current stage according to the corrected module temperature distribution of the current stage and the corrected chip power loss, and deriving the plastic strain energy density of each grid of the solder layer of the current stage according to the plastic strain energy density distribution of the solder layer of the current stage;
s520: and sequencing the plastic strain energy density of each grid of the solder layer at the current stage from large to small to obtain the plastic strain energy density of the grid with the maximum plastic strain energy density at the current stage, and calculating the service life at the current stage according to the crack initiation energy of the solder layer material, the plastic strain energy density of the grid with the maximum plastic strain energy density at the current stage, the plastic strain energy density of each previous stage of the grid with the maximum plastic strain energy density at the current stage and the service life of each previous stage.
In one embodiment, calculating the current stage module thermal resistance according to the current stage corrected module temperature distribution and corrected chip power loss in S510 includes:
acquiring the chip temperature and the shell temperature right below the chip in the current stage according to the corrected module temperature distribution in the current stage;
the thermal resistance of the module at the current stage is obtained by calculation according to the junction temperature of the chip at the current stage, the temperature of the shell right below the chip and the corrected power loss of the chip, and the thermal resistance of the module at the current stage is specifically:
；
wherein ,is->Stage coreSheet junction temperature, cryptophan officinalis>Is->Temperature of shell right below chip stage +.>First->Phase corrected chip power loss, +.>Is->And (5) stage module thermal resistance.
In one embodiment, when the current stage is the first stage, the plastic strain energy density of the grid with the maximum plastic strain energy density of the current stage at each previous stage and the life of each previous stage are all zero, and the current stage life is calculated in S520 according to the crack initiation energy of the solder layer material, the plastic strain energy density of the grid with the maximum plastic strain energy density of the current stage at each previous stage and the life of each previous stage, specifically:
；
wherein ,crack initiation energy for solder layer material, +.>For the first phase life, +.>Is the plastic strain energy density in the first stage solder layerPlastic strain energy density on the grid with the greatest degree.
In particular, the method comprises the steps of,is a known value, and can be calculated from the formula (12) described in section 3.1 of the related document Investigation on fatigue mechanism of solder layers in IGBT modules under high temperature gradients.
In one embodiment, when the current stage is not the first stage, the current stage lifetime is calculated in S520 according to the crack initiation energy of the solder layer material, the plastic strain energy density of the grid with the maximum plastic strain energy density of the current stage, the plastic strain energy density of each previous stage of the grid with the maximum plastic strain energy density of the current stage, and the lifetime of each previous stage, specifically:
；
wherein ,crack initiation energy for solder layer material, +.>Is->Plastic strain energy density on grid with maximum plastic strain energy density in stage solder layer, +.>Is->The grid with the maximum plastic strain energy density in the solder layer in the stage is at the +.>Plastic strain energy density at stage, +.>Is->Stage module lifetime, wherein->。
S600: when the current stage is not the first stage, judging whether the ratio of the module thermal resistance of the current stage to the module thermal resistance of the first stage is larger than a preset threshold, if not, eliminating the grid with the maximum plastic strain energy density of the current stage, entering the next stage, carrying out temperature field simulation to obtain the original temperature distribution of the next stage, returning to S300 until the ratio of the module thermal resistance of the corresponding stage to the module thermal resistance of the first stage is larger than the preset threshold, and outputting the service life of the module according to the service life of each stage.
In one embodiment, the ratio of the thermal resistance of the corresponding stage module to the thermal resistance of the first stage module in S600 is greater than a preset threshold, specifically:
；
wherein ,is the first stage module thermal resistance.
In one embodiment, the module lifetime is output in S600 according to each stage lifetime, specifically:
；
wherein ,for the life of the module->The number of stages experienced at the end of the cycle.
In a detailed embodiment, the detailed steps are as follows:
step 1, performing three-dimensional CT scanning on a power module solder layer, wherein the scanning result is shown in fig. 2, analyzing and measuring initial cavities in the scanning result, and establishing a power module three-dimensional finite element model of the solder layer containing distributed initial cavities is shown in fig. 3, wherein a chip is divided into a terminal area 1, a gate area 2 and an active area 3. The solder layer three-dimensional finite element model is shown in fig. 4. The bonding wires have little effect on the chip and solder layer temperature, and the bonding wires are ignored when constructing the three-dimensional finite element model of the module.
And 2, in finite element analysis, performing temperature field simulation on the power module under the condition that the power density is uniformly applied to the active region, and obtaining the primary temperature distribution in the first stage.
And 3, establishing a chip cell level model in Matlab, dividing a chip active area into 9 parts, scaling each cell model by using a power semiconductor chip physical model in an equal proportion, introducing the first-stage original temperature distribution obtained in the step 2 into the cell level model, and calculating cell loss at different positions of the first-stage chip.
And 4, importing the obtained distributed cell power loss into finite element analysis, performing temperature field simulation, and enabling the chip surface temperature distribution to be as close as possible to the actually measured chip surface temperature distribution by adjusting boundary conditions. The chip surface temperature distribution after calibration and the actual measured chip surface temperature distribution are shown in fig. 5.
Step 5, performing thermal coupling simulation to obtain the temperature distribution of the first-stage module and the plastic strain energy density distribution of the solder layer, and calculating the thermal resistance of the first-stage moduleAnd (3) carrying out normalization treatment, wherein the thermal resistance of the first stage is 1. As shown in fig. 6, the meshing diagram of this embodiment is 114885 meshes and has a large number of meshes, so in this embodiment, 5000 meshes are eliminated at a time, the plastic strain energy density of the mesh with the plastic strain energy density of 5000 th rank is 0.185, and the crack initiation energy of the solder layer material is 6499.05 according to the method described in the above related literature. Calculating stage one Life +.>：
；
And 6, importing 5000 grid numbers with highest energy into finite element analysis, eliminating the 5000 grids, and entering a second stage. And (3) re-carrying out temperature field simulation under the condition that the power loss distribution is unchanged, introducing the obtained temperature distribution into a chip cell level model established by Matlab, calculating the power loss distribution of the chip at the second stage, introducing the corrected power loss of the chip at the second stage into finite element analysis, and carrying out thermal coupling simulation to obtain the module temperature distribution after the second stage correction and the plastic strain energy density distribution of the solder layer. The plastic strain energy densities of 109885 grids are derived from finite elements, the grids are ordered from large to small, the plastic strain energy density of the 5000 th grid is ranked as 0.179 in the second stage plastic strain energy density, and the second stage module life is calculated:
；
step 7, calculating the normalized thermal resistance of the second-stage module1.011, less than->The number of stages is increased by one, and the operation of the step 6 is repeated.
Step 8, when iterating to the sixth stage, the thermal resistance thereof1.22, greater than->Iteration stop, calculate module lifetime +.>：
；
The predicted lifetime versus experimental lifetime pair is shown in fig. 7, for example, with an experimental lifetime of 61600, a predicted lifetime of 63540, and a prediction error of 3.1%.
According to the power module service life prediction method based on failure physics, the influences of uneven chip temperature distribution and solder layer stress distribution on the solder layer aging process caused by multi-factor mutual coupling are considered, and the solder layer aging process can be simulated more accurately; the change of the power loss distribution of the chip in the aging process of the solder layer is considered, so that the life prediction precision is higher; the solder material can be applied to modules of different packages of the same solder material, and has good universality.
The power module life prediction method based on failure physics provided by the invention is described in detail above. The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the core concepts of the invention. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.
Claims (7)
1. A power module life prediction method based on failure physics, the method comprising the steps of:
s100: establishing a power module three-dimensional finite element model with a solder layer containing a distributed initial cavity through CT scanning;
s200: under the condition of uniformly applying the power loss of the chip, carrying out temperature field simulation to obtain the original temperature distribution of the chip at the current stage;
s300: introducing the original temperature distribution of the chip at the current stage into a chip cell-level model established in Matlab to calculate cell power loss at different positions of the chip;
s400: the corrected chip power loss distribution is led into a chip active region in finite element analysis to carry out thermal coupling simulation, so that the module temperature distribution and the solder layer plastic strain energy density distribution corrected at the current stage are obtained;
s500: calculating the module thermal resistance of the current stage and the module service life of the current stage according to the corrected module temperature distribution of the current stage, the corrected chip power loss and the plastic strain energy density distribution of the solder layer;
s500 includes:
s510: calculating the module thermal resistance of the current stage according to the corrected module temperature distribution of the current stage and the corrected chip power loss, and deriving the plastic strain energy density of each grid of the solder layer of the current stage according to the plastic strain energy density distribution of the solder layer of the current stage;
s520: sequencing the plastic strain energy density of each grid of the solder layer at the current stage from large to small to obtain the plastic strain energy density of the grid with the maximum plastic strain energy density at the current stage, and calculating the service life of the current stage according to the crack initiation energy of the solder layer material, the plastic strain energy density of the grid with the maximum plastic strain energy density at the current stage, the plastic strain energy density of each previous stage of the grid with the maximum plastic strain energy density at the current stage and the service life of each previous stage;
s600: when the current stage is not the first stage, judging whether the ratio of the module thermal resistance of the current stage to the module thermal resistance of the first stage is larger than a preset threshold, if not, eliminating the grid with the maximum plastic strain energy density of the current stage, entering the next stage, carrying out temperature field simulation to obtain the original temperature distribution of the next stage, returning to S300 until the ratio of the module thermal resistance of the corresponding stage to the module thermal resistance of the first stage is larger than the preset threshold, and outputting the service life of the module according to the service life of each stage.
2. The method of claim 1, wherein S100 comprises:
and obtaining a three-dimensional microstructure of the solder layer of the power module chip through CT scanning, carrying out statistical analysis on initial voids in the solder layer, and establishing a three-dimensional finite element model of the power module containing distributed initial voids in the solder layer, wherein the modeling of the power module chip is divided into a terminal area, a gate area and an active area.
3. The method of claim 2, wherein calculating a current stage module thermal resistance from the corrected module temperature profile and the corrected chip power loss for the current stage in S510 comprises:
acquiring the chip temperature at the current stage and the shell temperature right below the chip according to the corrected module temperature distribution at the current stage;
calculating to obtain the module thermal resistance of the current stage according to the junction temperature of the chip, the temperature of the shell right below the chip and the corrected power loss of the chip, wherein the module thermal resistance of the current stage is specifically as follows:
；
wherein ,is->Stage chip junction temperature, < >>Is->Temperature of shell right below chip stage +.>First->Phase corrected chip power loss, +.>Is->And (5) stage module thermal resistance.
4. A method according to claim 3, wherein when the current stage is the first stage, the plastic strain energy density of the grid with the maximum plastic strain energy density of the current stage is zero in each previous stage and the life of each previous stage, and the current stage life is calculated in S520 based on the crack initiation energy of the solder layer material, the plastic strain energy density of the grid with the maximum plastic strain energy density of the current stage in each previous stage and the life of each previous stage, specifically:
；
wherein ,crack initiation energy for solder layer material, +.>For the first phase life, +.>Is the plastic strain energy density on the grid where the plastic strain energy density is the greatest in the first stage solder layer.
5. A method according to claim 3, wherein when the current stage is not the first stage, the current stage lifetime is calculated in S520 from the crack initiation energy of the solder layer material, the plastic strain energy density of the grid having the maximum plastic strain energy density of the current stage, the plastic strain energy density of each previous stage of the grid having the maximum plastic strain energy density of the current stage, and the lifetime of each previous stage, in particular:
；
wherein ,crack initiation energy for solder layer material, +.>Is->Plastic strain energy density on grid with maximum plastic strain energy density in stage solder layer, +.>Is->The grid with the maximum plastic strain energy density in the solder layer in the stage is at the +.>Plastic strain energy density at stage, +.>Is->Stage module lifetime, wherein->。
6. The method according to any one of claims 4 or 5, wherein the ratio of the thermal resistance of the corresponding stage module to the thermal resistance of the first stage module in S600 is greater than a predetermined threshold, specifically:
；
wherein ,is the first stage module thermal resistance.
7. The method of claim 6, wherein the outputting module life according to each stage life in S600 is specifically:
；
wherein ,for the life of the module->The number of stages experienced at the end of the cycle.
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