CN113987783A - Power semiconductor device service life prediction method based on multi-fatigue mode coupling - Google Patents
Power semiconductor device service life prediction method based on multi-fatigue mode coupling Download PDFInfo
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Abstract
The invention relates to a power semiconductor device life prediction method based on multi-fatigue mode coupling, which is characterized in that life prediction models are established aiming at different fatigue modes of a power semiconductor device; obtaining fatigue life model parameter data of the power semiconductor device under different fatigue failure modes and bringing the data into a life prediction model; establishing an electric-thermal coupling model of the power semiconductor device to obtain electric heating circulation working condition parameters; substituting the obtained electric heating cycle working condition parameters into a middle service life prediction model, and calculating fatigue service lives corresponding to different fatigue failure modes; and performing degradation correction on the electrothermal coupling model crusting thermal resistance and the on-resistance according to the fatigue life. The fatigue mode which causes the final failure of the device can be judged, the corresponding fatigue life is output, the dynamic degradation process of parameters such as thermal resistance/on resistance in the service process of the device can be simulated and extracted, and effective guidance is provided for the long-term operation reliability evaluation of the power semiconductor device.
Description
Technical Field
The invention belongs to the technical field of reliability of power electronic devices and devices, and particularly relates to a power semiconductor device service life prediction method based on multi-fatigue mode coupling.
Background
The electric energy conversion module is used by combining power components, and realizes electric energy digital storage and conversion based on various regulation strategies, wherein a power semiconductor device represented by an IGBT is a key device part for controlling the on-off of electric energy, and the power semiconductor device is a key factor influencing the overall performance and safe and reliable operation of the device. Statistics show that about 40% of converter failures in the various components of a power converter are due to power semiconductors, and the time spent to repair these failures accounts for more than 60% of the total failure time. Power semiconductor devices are typically heterogeneous composite structures whose normal electrical function is achieved depending on the package structural integrity. Due to the difference of thermal expansion coefficients of the packaging materials of the device, when the internal temperature field of the device fluctuates repeatedly, disturbed thermal stress is generated among different packaging structures. Under the long-term action of disturbance thermal stress, the defects of the microstructure in the packaging material continuously grow and gather, and the electrical, heat conduction, insulating mechanical and other properties of the material are degraded, so that the internal electric heating environment of the device is deteriorated, and the electric heating boundary for ensuring the safe operation of the device is dynamically degenerated. At the initial stage of operation of the power electronic device, the power semiconductor device can meet the requirement of safe operation through safe design, but as the service time of the power semiconductor device increases, the probability of transient electric heating breakdown failure of the device is greatly increased due to dynamic degradation of an electric heating safety boundary of the device, so that great threat is caused to the safe and reliable operation of the electric energy conversion module, and the performance improvement and the long-term operation reliability of the power electronic device are seriously restricted. Therefore, the service life of the power semiconductor device in the long-term service process is accurately predicted, and the method has important significance for guaranteeing safe and reliable operation of electric power equipment.
Under actual operating conditions, the fatigue behavior of a power semiconductor device package is very complex, multiple fatigue modes generally occur simultaneously, and different fatigue modes are coupled with each other. The physical differences exist among different fatigue modes, the fatigue life of the power semiconductor device is determined by the fatigue mode which fails firstly (main fatigue mode), the rest fatigue modes can also exert influence on the fatigue life of the device, and the main fatigue mode type can change along with the change of specific application conditions. The package fatigue is a slow and long-term evolution process, under the continuous action of various fatigue modes, the electric heating characteristics of the device are continuously and gradually degraded, the internal electric-thermal-stress environment is gradually deteriorated, and the fatigue process of each single fatigue mode is accelerated in turn. Therefore, dynamic coupling is realized by changing the electric heating characteristics of the power semiconductor device under the combined action of different fatigue modes.
Disclosure of Invention
The invention aims to provide a power semiconductor device life prediction method based on multi-fatigue mode coupling, which can provide effective guidance for evaluating the long-term operation reliability of a power semiconductor device, aiming at the defects of the technology.
In order to achieve the purpose, the invention is designed as follows: the method for predicting the service life of the power semiconductor device based on multi-fatigue mode coupling comprises the following steps:
1) establishing a life prediction model aiming at different fatigue modes of the power semiconductor device by combining a material fatigue theory and a working principle of the power semiconductor device;
2) establishing an accelerated life test platform according to the model of the power semiconductor device, and performing accelerated life assessment aiming at different fatigue modes of the power semiconductor device under different working conditions to obtain fatigue life model parameter data of the power semiconductor device under different fatigue failure modes and bring the data into the life prediction model in the step 1);
meanwhile, establishing an electric-thermal coupling model of the power semiconductor device to obtain electric heating circulation working condition parameters;
3) substituting the electric heating cycle working condition parameters obtained in the step 2) into the service life prediction model in the step 2), and calculating the fatigue life corresponding to different fatigue failure modes; and performing degradation correction on the electrothermal coupling model crusting thermal resistance and the on-resistance according to the fatigue life.
Further, in the step 1), the service life prediction model comprises a solder fatigue life model:
Nf_solder＝Af_solder·(ΔTj)^(αf_solder)·exp(-(Ef_solder)/Tjm)·(ton)^(βf_solder) (5)
Ni_solder＝Ai_solder·(ΔTj)^(αi_solder)·exp(-(Ei_solder)/Tjm)·(ton)^(βi_solder) (5a)
Np_solder＝Nf_solder-Ni_solder (5b)
in the formula, Ni_solder、Np_solderAnd Nf_solderRespectively solder fatigue initiation life, solder fatigue extension life and solder total fatigue life, Delta Tj、TjmAnd tonRespectively junction temperature fluctuation amplitude, average junction temperature and loading time, Af_solder、αf_solder、Ef_solderAnd betaf_solderAre all solder total fatigue life model parameters, Ai_solder、αi_solder、Ei_solderAnd betai_solderAll are parameters of a solder fatigue initiation life model;
bond wire fatigue life model:
Nf_wire＝Af_wire·{a·Ic 2/[1+d·exp(-ton)]+b·ΔTj}^(αf_wire) (6)
Ni_wire＝Ai_wire·{a·Ic 2/[1+d·exp(-ton)]+b·ΔTj}^(αi_wire) (6a)
Np_wire＝Nf_wire-Ni_wire (6b)
in the formula, Nf_wire、Ni_wireAnd Np_wireRespectively the total fatigue life, fatigue initiation life and fatigue extension life of the key wire, Ic 2/[1+d·exp(-ton)]Is key wire resistance heat, d is the time-dependent coefficient of the key wire resistance heat, a is the key wire resistance heat weight coefficient, b is the junction temperature weight coefficient, Af_wireAnd alphaf_wireAre all key wire fatigue total life model parameters, Ai_wireAnd alphai_wireAre all key fatigue initiation life model parameters, ICTo conduct current, Δ TjAnd tonThe junction temperature fluctuation amplitude and the loading time of the IGBT are respectively.
Further, in the step 2), the obtained life prediction model parameter data of the power semiconductor device in different fatigue failure modes includes a solder total fatigue life model parameter, a solder fatigue initiation life model parameter, a key wire fatigue total life model parameter and a key wire fatigue initiation life model parameter.
Further, in the step 2), an electrical thermal coupling model of the power semiconductor device is established according to the junction-to-shell thermal resistance R of the initial devicethjc_0And an on-resistance Ron_0Acquiring electric heating circulation working condition parameters including junction temperature fluctuation amplitude Delta TjHighest junction temperature TjmLoading time tonAnd conduction current Ic。
Further, the specific process of step 3) is as follows:
at thermal cycling intervals Δ nkNamely, setting that the parameters of the crusting thermal resistance and the on-resistance of the power semiconductor device are kept unchanged in the kth iteration step, and respectively calculating the fatigue initiation life N of the solder in the kth iteration step by substituting the parameters of the electric heating circulation working condition into formula (5) and formula (6)i_solder_kTotal fatigue life N of solderf_solder_kFatigue life of bond wire Ni_wire_kTotal fatigue life N of and key wiref_wire_k(ii) a According to material fatigueTheoretically, calculating the increment Delta D of the fatigue initiation damage of the solder in the kth iteration stepi_solder_kIncrease of fatigue extension damage Delta D of solderp_solder_kDelta D of fatigue initiation damage of bond wirei_wolder_kAnd bond wire fatigue extension damage increment Δ Dp_wolder_k：
ΔDi_solder_k＝(Δnk)/Ni_solder_k (7a)
ΔDp_solder_k＝(Δnk)/(Nf_solder_k-Ni_solder_k) (7b)
ΔDi_wolder_k＝(Δnk)/Ni_wire_k (7c)
ΔDp_wolder_k＝(Δnk)/(Nf_wire_k-Ni_wire_k) (7d)
Based on Miner fatigue damage accumulation rule, the fatigue damage accumulated after the kth iteration step is respectively:
Di_solder_k＝Di_solder_(k-1)+ΔDi_solder_k (8a)
Di_wire_k＝Di_wire_(k-1)+ΔDi_wire_k (8c)
Dp_solder_k＝Dp_solder_(k-1)+ΔDp_solder_k (8b)
Dp_wire_k＝Dp_wire_(k-1)+ΔDp_wire_k (8d)
wherein D isi_solder_kAccumulating the fatigue initiation damage D of the solder after the kth iterationp_solder_kAccumulating the fatigue extension damage of the solder after the kth iteration step, Di_wire_kAccumulating fatigue initiation damage of bond wire after kth iteration step, Dp_wire_kAccumulating fatigue extension damage of the key wire after the kth iteration step; di_solder_(k-1)Accumulating fatigue initiation damage D of solder after the k-1 iterationp_solder_kAccumulating the fatigue extension damage of the solder after the k-1 iteration step, Di_wire_kAccumulating fatigue initiation damage of bond wire after the k-1 iterationp_wire_kAccumulating fatigue expansion damage of the bond wire after the k-1 iteration step;
when the accumulated fatigue initiation damage is less than 1, the fatigue initiation stage is carried out; when the accumulated fatigue initiation damage is equal to 1, the material enters a fatigue extension stage, and the degradation relation of the junction thermal resistance and the on-resistance of the power semiconductor device is as follows:
Rthjc_k＝Rthjc_0，Dp_solder_k＝0(Di_solder_k<1)
Rthjc_k＝(1+μsolderDp_solder_k)×Rthjc_0(Di_solder_k＝1) (9a)
and
Dp_wire_k＝0，Ron_k＝Ron_0(Di_wire_k<1)
Ron_k＝(1+μwireDp_wire_k)×Ron_0(Di_wire_k＝1) (9b)
wherein R isthjc_kJunction-to-case thermal resistance, R, corrected for degradation of power semiconductor devices after the kth iteration stepon_kOn-resistance parameter, mu, for degradation correction of power semiconductor device after kth iteration stepsolderFor a given coefficient of degradation correction of the junction thermal resistance, muwireFor a given on-resistance degradation correction factor, Rthjc_0Is the initial incrustation thermal resistance, Ron_0Is the initial on-resistance;
the k-th iteration step is retreated and corrected to Rthjc_kAnd Ron_kRespectively feeding back the signals to the electrical thermal coupling model of the power semiconductor device in the step 2), and repeating the step 2) and the step 3), and ending the iterative cycle when the total fatigue extension damage corresponding to any one fatigue mode in the power semiconductor device reaches 1; outputting and storing the total cycle number N of the power semiconductor device after each iteration stepk(iterative Interval summation of the already-experienced first k iteration steps) and the thermal encrustation resistance Rthjc_kAnd on-resistance parameter Ron_kAnd outputting R representing dynamic degradation of electrothermal characteristics of power semiconductor devicethjc_k-NkAnd Ron_k-NkA curve; wherein, the failure mode that the total fatigue extension damage reaches 1 firstly is the main mode causing the failure of the power semiconductor device, and the final fatigue life of the power semiconductor deviceNfAnd the iteration intervals of all iteration steps after the device fails are added.
The invention has the following technical effects: the method for predicting the service life of the power semiconductor device based on multi-fatigue-mode coupling can predict the fatigue life of the power semiconductor device in the long-term service process under specific conditions, and can judge the fatigue mode causing the final failure of the device and output the corresponding fatigue life through the power semiconductor device electric-thermal coupling simulation-fatigue damage calculation iterative cycle, and can also simulate and extract the dynamic degradation process of parameters such as thermal resistance/on resistance and the like in the service process of the device, thereby providing effective guidance for the long-term operation reliability evaluation of the power semiconductor device.
Drawings
FIG. 1 is a comparison of simulation and experimental data of thermal resistance/on-resistance degradation of an IGBT device along with cycle cycles in a power cycle assessment process;
FIG. 2 shows the data of the total fatigue life of the welding and key wire of the IGBT module under different working condition circulation examination conditions: o-total solder fatigue life, □ -total bond wire fatigue life;
FIG. 3 is a simulation model of an IGBT module power cycle test circuit;
fig. 4 and 5 show cycle parameters obtained by the electric-thermal coupling simulation of the IGBT device under a certain specific condition in the power cycle test circuit: the on current is-65A, the on time is-1.00 s, and the off time is-2.00 s;
fig. 6 shows the life prediction simulation result of the IGBT module based on the iterative consideration of the electrical-thermal coupling simulation-fatigue damage calculation loop under different working conditions.
Detailed Description
The following further description is made with reference to the accompanying drawings and detailed description.
The fatigue of the solder layer and the fatigue of the key wire are the most main packaging failure modes of the power semiconductor device, and the solder layer is used as an important packaging structure in the power semiconductor module, plays roles of current conduction, heat dissipation, mechanical fixing support and the like, and is essential for realizing complete electrical functions of the device. In the long-term service process of the power semiconductor device, the action of disturbance thermal stress enables the solder alloy to generate visco-plastic deformation, deformation energy is continuously accumulated in the material, micro defects in the solder are gathered to form fatigue cracks and continuously expand, the cracks damage the structural integrity of the solder layer, the electric heating conduction capacity of the solder is reduced, the internal temperature of the device is continuously increased, the loss of the device is further increased due to the increase of junction temperature, the electric heating stress in the device is increased, the fatigue process of the solder layer is accelerated, and self-acceleration failure cycle is formed. The metal wire is connected with the upper surface of the chip and the DBC copper layer/power terminal through an ultrasonic bonding method, and is an essential packaging structure participating in power semiconductor electric energy conduction. The metal wire is directly bonded with the metal layer on the upper surface of the chip, when the switch of the power semiconductor device is switched on, the temperature change of the chip generates circulating fluctuating thermal stress on a bonding interface, a micro-crack is initiated and expanded along the bonding interface, the interface conductivity is reduced, the on-resistance of the power semiconductor device is increased, the chip loss is increased, the junction temperature and the fluctuation amplitude of the device are further improved, the initiation and expansion of the crack of the bonding interface are intensified in turn, and finally the bond wire can be stripped from the surface of the chip to cause the open circuit failure of the device.
The invention discloses a multi-fatigue-mode-based coupling power semiconductor device life prediction method based on electric-thermal coupling simulation-fatigue damage calculation loop iteration. The method will be described in detail below by taking the example of solder and bond wire fatigue failure under power cycle conditions of an Insulated Gate Bipolar Transistor (IGBT) module.
1, respectively establishing fatigue life models aiming at different fatigue modes of the power semiconductor device by combining a material fatigue theory and a power semiconductor device working principle
The fatigue of IGBT solder layer and bond wire are that the microcrack and the continuation expansion are initiated to specific material structure under the effect of the disturbance thermal stress that the fluctuation of device internal temperature caused, and the material viscoplasticity that thermal stress caused warp is out of shape, and inside accumulation viscoplasticity strain energy of material, strain energy accumulation to certain extent back, material atomic bond fracture formation crystal structure defect further assembles into the microcrack, and it is tired fundamental power of drive power semiconductor device packaging structure to see the material viscoplasticity strain energy from this. According to the material fatigue theory, the material fatigue life and the viscoplastic strain energy have the following relationship:
Nf＝Ni+Np＝k1(Δwpl)^(k2)+k3(Δwpl)^(k4) (1)
Ni＝k1(Δwpl)^(k2) (1a)
Np＝k3(Δwpl)^(k4) (1b)
in the formula, Nf、NiAnd NpRespectively total fatigue life, fatigue initiation life and fatigue extension life, and represents an exponential operation sign, Δ wplIncrease of viscoplastic strain energy density of the material every cycle1～k4Is a material parameter.
According to the theory of plastic mechanics, the viscoplastic strain energy of a material is defined by the following formula:
wpl＝∫σ·dεp (2)
in the formula, epsilonpLet viscoplastic strain, σ be stress, and ^ represents integral operation sign, and d represents differential operation sign.
The strain epsilon of the material under the action of thermal stress comprises elastic strain epsilonelasticPlastic strain epsilonplasticAnd creep strain epsiloncreepThe separation type constitutive model describes the relationship of stress-strain of the material as follows:
ε＝εelastic+εplastic+εcreep (3)
εelastic＝σ/E (3a)
εplastic＝(σ/Cplastic)^(1/n1) (3b)
e is the modulus of elasticity, cplasticIs the coefficient of ductility, n1Is ductility index, A, alpha, n2And Q are creep constitutive model parameters, R is the universal gas constant, t0As creep onset time, tFor stress loading time, T is temperature. The elastic strain belongs to a recoverable part, does not influence the viscoplastic strain energy of the material, and the plastic strain and the creep strain are viscoplastic deformation parts of the material. Therefore, the viscoplastic strain of the material is mainly influenced by stress, temperature and loading time, and according to the thermal stress theory, the thermal stress of the material is linearly related to the temperature fluctuation:
σ＝αT·ΔT (4)
wherein alpha isTRegarding the thermal expansion coefficient, Δ T is the temperature fluctuation amplitude, and the fatigue life model is further simplified to be based on the following equations (1) to (4) under the assumption of small strain:
Nf＝Af(ΔT)^(af·)exp(-E/T)·(t)^β
wherein A isf、E、αfAnd β are all model parameters to be determined.
According to the operating principle of the IGBT device, the solder fatigue is mainly affected by junction temperature fluctuation, so that the solder fatigue life model is shown as the following formula:
Nf_solder＝Af_solder·(ΔTj)^(αf_solder)·exp(-(Ef_solder)/Tjm)·(ton)^(βf_solder) (5)
Ni_solder＝Ai_solder·(ΔTj)^(αi_solder)·exp(-(Ei_solder)/Tjm)·(ton)^(βi_solder) (5a)
Np_solder＝Nf_solder-Ni_solder (5b)
in the formula Ni_solder、Np_solderAnd Nf_solderRespectively solder fatigue initiation life, solder fatigue extension life and solder total fatigue life, Delta Tj、TjmAnd tonRespectively junction temperature fluctuation amplitude, average junction temperature and loading time, Af_solder、αf_solder、Ef_solderAnd betaf_solderAre all solder total fatigue life model parameters, Ai_solder、αi_solder、Ei_solderAnd betai_solderAll are parameters of a solder fatigue initiation life model;
according to the working principle of an IGBT device, the fatigue of the bonding wire is mainly influenced by the temperature fluctuation of a bonding pad, the temperature fluctuation of the bonding pad is caused by junction temperature fluctuation and resistance heat of the bonding wire, and in addition, as the Al metal of the bonding wire composition material has high melting point and high strength, the creep strain can be ignored within the normal working temperature range of the IGBT, the fatigue life model of the bonding wire is shown as the following formula:
Nf_wire＝Af_wire·{a·Ic 2/[1+d·exp(-ton)]+b·ΔTj}^(αf_wire) (6)
Ni_wire＝Ai_wire·{a·Ic 2/[1+d·exp(-ton)]+b·ΔTj}^(αi_wire) (6a)
Np_wire＝Nf_wire-Ni_wire (6b)
in the formula, Nf_wire、Ni_wireAnd Np_wireRespectively the total fatigue life, fatigue initiation life and fatigue extension life of the key wire, Ic 2/[1+d·exp(-ton)]Is key wire resistance heat, d is the time-dependent coefficient of the key wire resistance heat, a is the key wire resistance heat weight coefficient, b is the junction temperature weight coefficient, Af_wireAnd alphaf_wireAre all key wire fatigue total life model parameters, Ai_wireAnd alphai_wireAre all key fatigue initiation life model parameters, ICTo conduct current, Δ TjAnd tonThe junction temperature fluctuation amplitude and the loading time of the IGBT are respectively.
2. Establishing an accelerated life test platform, and respectively carrying out accelerated life examination on different fatigue modes of the power semiconductor device under different working conditions to obtain life prediction model parameter data of the power semiconductor device under different fatigue failure modes
Determining specification and model of a power semiconductor device, taking an Insulated Gate Bipolar Transistor (IGBT) as an example, adopting a power cycle check platform, setting the voltage of a gate emitter to be +10V, and adopting the power cycle check platform to control the IGBT at different junction temperature waves in a constant junction temperature fluctuation modePerforming solder fatigue examination under the conditions of dynamic and average temperature and turn-on time, and monitoring and extracting the thermal resistance R of the crust of the IGBT module in the solder fatigue processthjcAnd an on-resistance RonData is degraded over the power cycle. Setting the gate emitter voltage to +20V, checking the fatigue of the IGBT key wire by the same method, monitoring and extracting the junction-crust thermal resistance R of the IGBT module in the solder fatigue processthjcAnd an on-resistance RonData is degraded over the power cycle. In the power cycle process, IGBT module thermal resistance/on-resistance degradation data are segmented according to fatigue initiation (thermal resistance/on-resistance is not obviously increased) and fatigue extension (thermal resistance/on-resistance is obviously increased), 20% of crusting thermal resistance increase and 5% of on-resistance increase are set as fatigue failure thresholds of IGBT module solder and key wire respectively, and IGBT module fatigue initiation life N under different working conditions and fatigue failure modes is extractedi_solder/Ni_wireAnd total fatigue life data Nf_solder/Nf_wireAs shown in fig. 1. And (3) extracting a solder total fatigue life model parameter, a solder fatigue initiation life model parameter, a key fatigue total life model parameter and a key fatigue initiation life model parameter respectively by combining the circulation working condition and the solder and key fatigue life data of the IGBT module by adopting a data fitting method, as shown in a figure 2, a formula (5 ') and a formula (6').
Nf_solder＝1.853×1013·(ΔTj)-4.3552·exp(-1378/Tjm)·(ton)0.2526 (5’)
Ni_solder＝5.2×1012·(ΔTj)-4.3552·exp(-1378/Tjm)·(ton)0.2526 (5a’)
Nf_wire＝1.142×1013{0.01Ic 2/[1+0.291·exp(-ton)]+0.57·ΔTj-20}-4.2114 (6’)
Ni_wire＝8.3×1012{0.01Ic 2/[1+0.291·exp(-ton)]+0.57·ΔTj-20}-4.2114 (6a’)
3. Establishing an electrothermal coupling model of a power semiconductor device to obtain electrothermal circulation working condition parameters
The method comprises the steps of determining parameters such as circuit topology, control parameters and load conditions of the power semiconductor device, and building an electrothermal coupling simulation circuit of the power semiconductor device based on simulation platforms such as MATLAB/SIMULINK and PLCES. Setting variable thermal resistance and on-resistance circuit element in power semiconductor device electric thermal coupling model, firstly inputting initial device crusting thermal resistance Rthjc_0And an on-resistance Ron_0And simulating and extracting junction temperature fluctuation amplitude delta T of the power semiconductor device under given conditionsjHighest junction temperature TjmLoading time tonAnd conduction current IcAnd (4) working condition parameters of electric heating circulation.
V-I, E given in MATLAB/SIMULINK platform based on IGBT data manual, using IGBT module bond wire and solder fatigue as examplesonAnd EoffEstablishing an IGBT module table look-up method loss calculation module according to data, establishing an IGBT module power cycle test simulation circuit, and setting on-resistance and crusting thermal resistance in an IGBT loss calculation and heat network module as variable circuit parameters, as shown in figure 3. Setting the on-current IC65A, the on-time is 1s, the off-time is 2s, the input initial crusting thermal resistance is 0.192K/W, the on-resistance is 0.005 omega, the simulation time length is set to 3000s (corresponding to 1000 power cycles), the IGBT module is subjected to electrothermal coupling simulation, and the junction temperature fluctuation amplitude Delta T of the IGBT module is extractedjHighest junction temperature TjmOn-state current ICAnd on-time tonThe working condition parameters of the electric heating cycle are shown in figures 4 and 5.
4. Performing degradation correction on electrothermal coupling model crusting thermal resistance and on-resistance according to fatigue damage
Assume that at thermal cycling intervals Δ nk(set as the kth iteration step), the thermal resistance/on-resistance parameter of the power semiconductor device is kept unchanged, and the electric heating circulation working condition parameters extracted by the electric heating coupling model are substituted into the formula (5) and the formula (6) to respectively calculate the fatigue initiation life N of the solder in the kth iteration stepi_solder_kTotal fatigue life N of solderf_solder_kFatigue life of bond wire Ni_wire_kTotal fatigue life N of and key wiref_wire_k. According to the definition of the fatigue damage of the material,calculating the solder fatigue initiation damage increment Delta D of the kth iteration stepi_solder_kIncrease of fatigue extension damage Delta D of solderp_solder_kDelta D of fatigue initiation damage of bond wirei_wolder_kAnd bond wire fatigue extension damage increment Δ Dp_wolder_k：
ΔDi_solder_k＝(Δnk)/Ni_solder_k (7a)
ΔDp_solder_k＝(Δnk)/(Nf_solder_k-Ni_solder_k) (7b)
ΔDi_wolder_k＝(Δnk)/Ni_wire_k (7c)
ΔDp_wolder_k＝(Δnk)/(Nf_wire_k-Ni_wire_k) (7d)
Based on Miner fatigue damage accumulation rule, the fatigue damage accumulated after the kth iteration step is respectively:
Di_solder_k＝Di_solder_(k-1)+ΔDi_solder_k (8a)
Di_wire_k＝Di_wire_(k-1)+ΔDi_wire_k (8c)
Dp_solder_k＝Dp_solder_(k-1)+ΔDp_solder_k (8b)
Dp_wire_k＝Dp_wire_(k-1)+ΔDp_wire_k (8d)
wherein D isi_solder_kAccumulating the fatigue initiation damage D of the solder after the kth iterationp_solder_kAccumulating the fatigue extension damage of the solder after the kth iteration step, Di_wire_kAccumulating fatigue initiation damage of bond wire after kth iteration step, Dp_wire_kAccumulating fatigue extension damage of the key wire after the kth iteration step; di_solder_(k-1)Accumulating fatigue initiation damage D of solder after the k-1 iterationp_solder_kAccumulating the fatigue extension damage of the solder after the k-1 iteration step, Di_wire_kAccumulating fatigue initiation damage of bond wire after the k-1 iterationp_wire_kAccumulating fatigue expansion damage of the bond wire after the k-1 iteration step;
according to the material fatigue theory, the material fatigue is generally divided into two sequential stages of fatigue initiation and fatigue extension, and when the accumulated fatigue initiation damage is less than 1, the material fatigue is in a fatigue initiation stage; strain energy is continuously accumulated in the material at a fatigue initiation stage, no micro-cracks are formed in the material, and fatigue initiation damage has no influence on the electric heating conduction capability of the material, so that the thermal resistance/on resistance parameter of the power semiconductor device at the stage is kept unchanged; when the accumulated fatigue initiation damage is equal to 1, the material enters a fatigue expansion stage, the internal micro-cracks of the material are already formed at the stage and continuously expand under the action of thermal stress, so that the parameters of the thermal resistance and the on-resistance of the power semiconductor device are continuously degraded along with the increase of the fatigue expansion damage, and the specific degradation relation is as follows:
Rthjc_k＝Rthjc_0，Dp_solder_k＝0(Di_solder_k<1, fatigue sprout stage)
Rthjc_k＝(1+μsolderDp_solder_k)×Rthjc_0(Di_solder_kFatigue extension stage (9a) ═ 1
And
Dp_wire_k＝0，Ron_k＝Ron_0(Di_wire_k<1, fatigue sprout stage)
Ron_k＝(1+μwireDp_wire_k)×Ron_0(Di_wire_kFatigue extension stage (9b) ═ 1
Wherein R isthjc_kJunction-to-case thermal resistance, R, corrected for degradation of power semiconductor devices after the kth iteration stepon_kOn-resistance parameter, mu, for degradation correction of power semiconductor device after kth iteration stepsolderFor a given coefficient of degradation correction of the junction thermal resistance, muwireFor a given on-resistance degradation correction factor, Rthjc_0Is the initial incrustation thermal resistance, Ron_0Is the initial on-resistance;
the k-th iteration step is retreated and corrected to Rthjc_kAnd Ron_kRespectively feeding back the signals to the electrical thermal coupling model of the power semiconductor device in the step 2), repeating the step 2) to the step 4), and when the total fatigue expansion corresponding to any one fatigue mode in the power semiconductor device is achievedEnding the iterative loop when the unfolding damage reaches 1; outputting and storing the total cycle number N of the power semiconductor device after each iteration stepk(iterative Interval summation of the already-experienced first k iteration steps) and the thermal encrustation resistance Rthjc_kAnd on-resistance parameter Ron_kAnd outputting R representing dynamic degradation of electrothermal characteristics of power semiconductor devicethjc_k-NkAnd Ron_k-NkA curve; wherein, the failure mode that the total fatigue extension damage reaches 1 firstly is the main mode causing the failure of the power semiconductor device, and the final fatigue life N of the power semiconductor devicefAnd the iteration intervals of all iteration steps after the device fails are added.
For example, the IGBT electrothermal cycle working condition parameters shown in fig. 4 and 5 are substituted into formula (5 ') and formula (6') to respectively calculate the fatigue initiation life and the total fatigue life of the solder and the bond wire of the IGBT module under the working condition, 1000 times of power cycle is taken as an iteration interval, and the fatigue damage is calculated and accumulated according to formula (7) and formula (8); according to the formula (9) and the fatigue expansion damage of the solder and the bonding wire accumulated by the IGBT module after the iteration step to the junction thermal resistance R of the IGBT modulethjcAnd an on-resistance RonPerforming degradation correction to correct Rthjc_kAnd Ron_kRespectively fed back to the power semiconductor device electric thermal coupling model.
The k-th iteration step is retreated and corrected to Rthjc_kAnd Ron_kRespectively feeding back the parameters to the electrothermal coupling model of the power semiconductor device in the step 3), carrying out electrothermal coupling simulation again after updating the incrustation thermal resistance/on-resistance parameters, repeating the step 3) and the step 4), extracting the working condition parameters of the electrothermal circulation of the device, carrying out fatigue damage calculation, and correcting the degeneration of the incrustation thermal resistance and the on-resistance to form an electrothermal coupling simulation-fatigue damage calculation iterative cycle of the power semiconductor device.
After each iteration cycle, the solder fatigue extension damage D is preservedp_solderFatigue extension damage of bond wire Dp_wireDevice junction thermal resistance RthjcAnd an on-resistance RonAs shown in fig. 6. And ending the iteration cycle when the total fatigue extension damage corresponding to any failure mode of the power semiconductor device reaches 1.
Outputting the thermal resistance R of the crust of the power semiconductor device after each iteration cycle after the simulation is finishedthjcAnd an on-resistance RonDisplaying the dynamic degradation process of the electric heating parameters of the power semiconductor device; and judging the fatigue loss mode and the corresponding fatigue life of the power semiconductor device according to the given thermal resistance and the conduction voltage drop threshold.
Automatically calling a SIMULINK program to perform electrothermal coupling simulation of the IGBT module, extraction of parameters of circulating conditions of the IGBT module, accumulated calculation of fatigue damage of the IGBT module, degradation correction and feedback of electrothermal parameters of the IGBT module and the like based on MATLAB compiling script files, performing IGBT electrothermal coupling simulation-fatigue damage calculation loop iteration, setting a loop iteration termination condition, and extracting and storing incrustation thermal resistance and on-resistance of the IGBT module after each iteration loop when the termination condition is met, wherein the control program is automatically stopped; setting 20% of crusting thermal resistance and 5% of on-resistance as fatigue failure threshold values of solder and key wires of the IGBT module respectively, if the crusting thermal resistance firstly reaches the failure threshold value, judging that the solder of the IGBT module is in fatigue failure under the condition, and the corresponding thermal cycle frequency is the fatigue life of the IGBT module, if the on-resistance firstly reaches the failure threshold value, judging that the key wires of the IGBT module are in fatigue failure under the condition, and the corresponding thermal cycle frequency is the fatigue life of the IGBT module.
Claims (5)
1. A power semiconductor device life prediction method based on multi-fatigue mode coupling is characterized in that: the method comprises the following steps:
1) establishing a life prediction model aiming at different fatigue modes of the power semiconductor device by combining a material fatigue theory and a working principle of the power semiconductor device;
2) establishing an accelerated life test platform according to the model of the power semiconductor device, and performing accelerated life assessment aiming at different fatigue modes of the power semiconductor device under different working conditions to obtain fatigue life model parameter data of the power semiconductor device under different fatigue failure modes and bring the data into the life prediction model in the step 1);
meanwhile, establishing an electric-thermal coupling model of the power semiconductor device to obtain electric heating circulation working condition parameters;
3) substituting the electric heating cycle working condition parameters obtained in the step 2) into the service life prediction model in the step 2), and calculating the fatigue life corresponding to different fatigue failure modes; and performing degradation correction on the electrothermal coupling model crusting thermal resistance and the on-resistance according to the fatigue life.
2. The method of claim 1, wherein the method comprises: in the step 1), the service life prediction model comprises a solder fatigue life model and a bond wire fatigue life model;
solder fatigue life model:
Nf_solder＝Af_solder·(ΔTj)^(αf_solder)·exp(-(Ef_solder)/Tjm)·(ton)^(βf_solder) (5)
Ni_solder＝Ai_solder·(ΔTj)^(αi_solder)·exp(-(Ei_solder)/Tjm)·(ton)^(βi_solder) (5a)
Np_solder＝Nf_solder-Ni_solder (5b)
in the formula, Ni_solder、Np_solderAnd Nf_solderRespectively solder fatigue initiation life, solder fatigue extension life and solder total fatigue life, Delta Tj、TjmAnd tonRespectively junction temperature fluctuation amplitude, average junction temperature and loading time, Af_solder、αf_solder、Ef_solderAnd betaf_solderAre all solder total fatigue life model parameters, Ai_solder、αi_solder、Ei_solderAnd betai_solderAll are parameters of a solder fatigue initiation life model;
bond wire fatigue life model:
Nf_wire＝Af_wire·{a·Ic 2/[1+d·exp(-ton)]+b·ΔTj}^(αf_wire) (6)
Ni_wire＝Ai_wire·{a·Ic 2/[1+d·exp(-ton)]+b·ΔTj}^(αi_wire) (6a)
Np_wire＝Nf_wire-Ni_wire (6b)
in the formula, Nf_wire、Ni_wireAnd Np_wireRespectively the total fatigue life, fatigue initiation life and fatigue extension life of the key wire, Ic 2/[1+d·exp(-ton)]Is key wire resistance heat, d is the time-dependent coefficient of the key wire resistance heat, a is the key wire resistance heat weight coefficient, b is the junction temperature weight coefficient, Af_wireAnd alphaf_wireAre all key wire fatigue total life model parameters, Ai_wireAnd alphai_wireAre all key fatigue initiation life model parameters, ICTo conduct current, Δ TjAnd tonThe junction temperature fluctuation amplitude and the loading time of the IGBT are respectively.
3. The method for predicting the life of a power semiconductor device based on multi-fatigue-mode coupling according to claim 2, wherein: in the step 2), the obtained life prediction model parameter data of the power semiconductor device under different fatigue failure modes comprises a solder total fatigue life model parameter, a solder fatigue initiation life model parameter, a key wire fatigue total life model parameter and a key wire fatigue initiation life model parameter.
4. The method for predicting the life of a power semiconductor device based on multi-fatigue-mode coupling according to claim 2, wherein: in the step 2), establishing an electric-thermal coupling model of the power semiconductor device according to the junction-crust thermal resistance R of the initial devicethjc_0And an on-resistance Ron_0Acquiring electric heating circulation working condition parameters including junction temperature fluctuation amplitude Delta TjHighest junction temperature TjmLoading time tonAnd conduction current Ic。
5. The method for predicting the life of a power semiconductor device based on multi-fatigue-mode coupling according to claim 4, wherein: the specific process of the step 3) is as follows:
at thermal cycling intervals Δ nkNamely, setting that the parameters of the crusting thermal resistance and the on-resistance of the power semiconductor device are kept unchanged in the kth iteration step, and respectively calculating the fatigue initiation life N of the solder in the kth iteration step by substituting the parameters of the electric heating circulation working condition into formula (5) and formula (6)i_solder_kTotal fatigue life N of solderf_solder_kFatigue life of bond wire Ni_wire_kTotal fatigue life N of and key wiref_wire_k(ii) a According to the material fatigue theory, calculating the solder fatigue initiation damage increment delta D of the kth iteration stepi_solder_kIncrease of fatigue extension damage Delta D of solderp_solder_kDelta D of fatigue initiation damage of bond wirei_wolder_kAnd bond wire fatigue extension damage increment Δ Dp_wolder_k：
ΔDi_solder_k＝(Δnk)/Ni_solder_k (7a)
ΔDp_solder_k＝(Δnk)/(Nf_solder_k-Ni_solder_k) (7b)
ΔDi_wolder_k＝(Δnk)/Ni_wire_k (7c)
ΔDp_wolder_k＝(Δnk)/(Nf_wire_k-Ni_wire_k) (7d)
Based on Miner fatigue damage accumulation rule, the fatigue damage accumulated after the kth iteration step is respectively:
Di_solder_k＝Di_solder_(k-1)+ΔDi_solder_k (8a)
Di_wire_k＝Di_wire_(k-1)+ΔDi_wire_k (8c)
Dp_solder_k＝Dp_solder_(k-1)+ΔDp_solder_k (8b)
Dp_wire_k＝Dp_wire_(k-1)+ΔDp_wire_k (8d)
wherein D isi_solder_kAccumulating the fatigue initiation damage D of the solder after the kth iterationp_solder_kAccumulating the fatigue extension damage of the solder after the kth iteration step, Di_wire_kAccumulated after the kth iterationFatigue initiation damage of bond wire, Dp_wire_kAccumulating fatigue extension damage of the key wire after the kth iteration step; di_solder_(k-1)Accumulating fatigue initiation damage D of solder after the k-1 iterationp_solder_kAccumulating the fatigue extension damage of the solder after the k-1 iteration step, Di_wire_kAccumulating fatigue initiation damage of bond wire after the k-1 iterationp_wire_kAccumulating fatigue expansion damage of the bond wire after the k-1 iteration step;
when the accumulated fatigue initiation damage is less than 1, the fatigue initiation stage is carried out; when the accumulated fatigue initiation damage is equal to 1, the material enters a fatigue extension stage, and the degradation relation of the junction thermal resistance and the on-resistance of the power semiconductor device is as follows:
Rthjc_k＝Rthjc_0，Dp_solder_k＝0(Di_solder_k<1)
Rthjc_k＝(1+μsolderDp_solder_k)×Rthjc_0(Di_solder_k＝1) (9a)
and
Dp_wire_k＝0，Ron_k＝Ron_0(Di_wire_k<1)
Ron_k＝(1+μwireDp_wire_k)×Ron_0(Di_wire_k＝1) (9b)
wherein R isthjc_kJunction-to-case thermal resistance, R, corrected for degradation of power semiconductor devices after the kth iteration stepon_kOn-resistance parameter, mu, for degradation correction of power semiconductor device after kth iteration stepsolderFor a given coefficient of degradation correction of the junction thermal resistance, muwireFor a given on-resistance degradation correction factor, Rthjc_0Is the initial incrustation thermal resistance, Ron_0Is the initial on-resistance;
the k-th iteration step is retreated and corrected to Rthjc_kAnd Ron_kRespectively feeding back the signals to the electrical thermal coupling model of the power semiconductor device in the step 2), and repeating the step 2) and the step 3), and ending the iterative cycle when the total fatigue extension damage corresponding to any one fatigue mode in the power semiconductor device reaches 1; output storage post-step power semiconductorTotal cycle number N experienced by the devicekAnd incrustation thermal resistance Rthjc_kAnd on-resistance parameter Ron_kAnd outputting R representing dynamic degradation of electrothermal characteristics of power semiconductor devicethjc_k-NkAnd Ron_k-NkA curve; wherein, the failure mode that the total fatigue extension damage reaches 1 firstly is the main mode causing the failure of the power semiconductor device, and the final fatigue life N of the power semiconductor devicefAnd the iteration intervals of all iteration steps after the device fails are added.
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| CN116738804A (en) * | 2023-08-16 | 2023-09-12 | 湖南大学 | Power module life prediction method based on failure physics |
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| CN115166499A (en) * | 2022-06-28 | 2022-10-11 | 上海正泰智能科技有限公司 | Method and device for determining service life of circuit breaker, computer equipment and storage medium |
| CN115166499B (en) * | 2022-06-28 | 2023-12-08 | 上海正泰智能科技有限公司 | Method and device for determining service life of circuit breaker, computer equipment and storage medium |
| CN116738804A (en) * | 2023-08-16 | 2023-09-12 | 湖南大学 | Power module life prediction method based on failure physics |
| CN116738804B (en) * | 2023-08-16 | 2023-11-03 | 湖南大学 | Power module life prediction method based on failure physics |
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