JP2017010441A - Semiconductor integrated circuit simulation method and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of performing circuit simulation of a semiconductor integrated circuit, which overcomes a problem of margin shortage among timing elements in the vicinity of a heat source element which generates heat that causes the problem.SOLUTION: A circuit simulation method includes steps of; producing a circuit diagram (201); simulating circuit operation (202); calculating amounts of heat generated by circuit elements using the simulation of circuit operation (203); making a floor plan of a circuit arrangement (205); calculating thermal resistance based on lead frame information and package information (206), (207); performing thermal simulation based on the calculated thermal resistance (208); calculating a maximum thermal gradient difference based on the thermal simulation (209); calculating worst timing based on the computed maximum thermal gradient difference (210); and performing circuit simulation with the worst timing (211).SELECTED DRAWING: Figure 5

Description

  The present invention relates to a circuit simulation method for a semiconductor integrated circuit and a semiconductor integrated circuit designed and manufactured based on the method.

  For example, heat countermeasures have conventionally been taken in the arrangement of semiconductor integrated circuits incorporating heat source elements through which a large current flows, such as various driver integrated circuits, power integrated circuits, CPUs (central processing units), and IPDs (intelligent power devices). There are many things.

  Patent Document 1 discloses a method of arranging a heat source element and a temperature dependent element so that temperature changes of two or more temperature dependent elements are substantially the same.

  Patent Document 2 discloses an automatic placement method of a semiconductor integrated circuit in which circuit blocks that generate a large amount of power are distributed and placed on a semiconductor substrate to make the temperature distribution on the semiconductor substrate uniform. Therefore, in the method of grouping basic logic circuits by function into circuit blocks and automatically arranging a plurality of circuit blocks on a semiconductor substrate, the simulation output result obtained by simulating circuit operation and the basic logic circuit The power consumption of the circuit block is calculated using the power consumption calculation rule file storing the means for calculating the power consumption. Using this calculation result, circuit connection information, and placement restriction means when placing and wiring the basic logic circuit on the semiconductor substrate, the circuit block is placed on the semiconductor substrate so as to average the power consumption per unit area. To do.

  Patent Document 3 discloses a method for calculating the thermal resistance of a heat dissipation path from a surface-mounted element. It is said that it is possible to design and manufacture a heat-reliable one by designing such a thermal resistance calculation method.

  Patent Document 4 provides a method for designing a semiconductor integrated circuit system with excellent workability by designing the semiconductor integrated circuit with good workability even when the semiconductor integrated circuit is scaled up and highly integrated. Therefore, based on the system specification information, a semiconductor integrated circuit (LSI) including a housing that houses the system, a mounting substrate that is housed in the housing and forms the system, and a package substrate that is mounted on the mounting substrate A first step of designing an apparatus, a step of performing a thermal analysis of at least one of a mounting substrate and a semiconductor integrated circuit in the housing, and a step of performing a thermal analysis based on the design result obtained in the first step A second step of designing a semiconductor integrated circuit system based on the analysis result is included. According to Patent Document 4, by optimizing the element arrangement of the semiconductor integrated circuit based on not only the internal conditions of the semiconductor integrated circuit but also the mounting substrate including the housing and the thermal analysis information of the package substrate, the mounting substrate, The package substrate and the entire semiconductor integrated circuit can be optimized.

  Patent Document 5 considers position information of a heat source when designing the layout of an electronic circuit, and it is said that optimal electrical characteristics can be obtained. To that end, in an electronic circuit arrangement creating apparatus for creating an arrangement of an electronic circuit including a plurality of circuit blocks and at least one heat source, circuit netlist data including a netlist of the first circuit block, and circuit netlist data A circuit simulation is performed based on the above. Based on the simulation result data, the heat source position calculating means for searching the heat source and calculating the heat source position, the calculated heat source position, and the arrangement information of all the circuit blocks based on the floor plan inputted in advance, from each circuit block The heat source relative position calculating means for calculating the relative position of the heat source and the heat source based on the calculated relative position of the heat source when the arrangement of the second circuit block different from the first circuit block is created. The arrangement heat source display control means for controlling to display the symbol at the relative position of the designated second circuit block.

Japanese Patent Laid-Open No. 7-32286 JP-A-9-266254 JP-A 64-13445 JP 2008-102631 A JP2013-161352A

  Patent Document 1 can improve the thermal matching between temperature dependent elements in a semiconductor integrated circuit in which a heat source element and a temperature dependent element coexist. However, the size and thickness of the semiconductor chip and the thermal resistance of the package on which the semiconductor substrate is mounted are not considered. For this reason, it cannot be said that it has arrange | positioned correctly along the heat distribution in a semiconductor chip, and a thermal gradient.

  In Patent Document 2, a simulation of heat conduction including a semiconductor chip and a package is performed in paragraph 0025 to obtain a chip temperature per unit area in the chip, and a difference between the maximum temperature Tmax and the minimum temperature Tmin on the chip is allowed. Whether the temperature is within the temperature Tc is calculated. If the temperature is not within the allowable temperature Tc, it is suggested that the circuit block is divided again to measure the dispersion of the power consumption. However, it does not disclose or suggest specific simulation methods for thermal conductivity and thermal resistance.

  Patent Document 3 discloses obtaining the thermal resistance of a semiconductor chip and a package, but does not disclose or suggest an arrangement method for arranging circuit elements on the semiconductor chip.

  In Patent Document 4, after designing a semiconductor integrated circuit system, after performing a thermal analysis, based on the analysis result, the element arrangement of the semiconductor integrated circuit, the mounting structure on the package substrate, the arrangement on the mounting substrate, etc. Therefore, it can be expected to realize a semiconductor integrated circuit system having excellent thermal characteristics. However, since the target of thermal analysis does not consider the size and thickness of the semiconductor chip, the diameter and length of the bonding wire, the size of the die pad (die flag), etc., grasp the proper heat distribution and thermal gradient in the semiconductor chip. I can't expect to do it.

  Patent Document 5 calculates the heat source position by specifying the heat source generated in the circuit block based on the net list data of the circuit block including the heat source in the entire electronic circuit and the simulation result by the heat source position calculating means. Therefore, there is no possibility of omission of the heat source. However, as in Patent Document 4, since the target of thermal analysis does not consider the size and thickness of the semiconductor chip, the diameter and length of the bonding wire, the size of the die pad, etc., accurate heat distribution within the semiconductor chip is obtained. We cannot expect to grasp it.

  The object of the present invention is to overcome the above problems and disadvantages. For this purpose, the size (area) of the heat source element built in the semiconductor chip, power consumption, the size of the semiconductor chip, the diameter and length of the bonding wire, the size of the die pad (die flag), and the semiconductor chip are sealed. Calculation of thermal conductivity such as package size, shape, material and material. Based on the calculation results, the temperature distribution and temperature gradient in the semiconductor chip are obtained, and various circuit elements are arranged or circuit simulated in the semiconductor integrated circuit (semiconductor chip) based on the temperature distribution and temperature gradient. Design and manufacture circuits.

  In this document, “timing element” refers to a transistor or a logic circuit used in a logic circuit. A flip-flop circuit can be given as a representative of the logic circuit. “Lead frame information” refers to at least one of the shape, material, material, various physical characteristics, size, thickness, and the like related to a lead frame that is a metal strip on which a semiconductor chip is mounted. “Package information” refers to at least one of the shape, material, material, various physical constants and characteristics, size, thickness, etc. of a part of a lead frame and a sealing body for sealing a semiconductor chip. . Physical characteristics typically include thermal conductivity, thermal resistance, and thermal capacity regardless of lead frame information and package information. In this document, “semiconductor chip” refers to a small piece obtained by dividing a semiconductor substrate on which a semiconductor integrated circuit is built. An “isothermal line” refers to a so-called temperature distribution line obtained by connecting points of the same temperature on a semiconductor chip.

The circuit simulation method of the semiconductor integrated circuit of the present invention is
(A) creating a circuit diagram of a semiconductor integrated circuit including a heat source element;
(B) performing a circuit operation simulation of the semiconductor integrated circuit based on the circuit diagram;
(C) calculating a heat generation amount of the semiconductor integrated circuit based on the circuit operation simulation;
(D) performing a floor plan of the semiconductor integrated circuit with reference to the calculated calorific value;
(E) inputting a thermal resistance to thermal simulation software based on various information of a lead frame on which the semiconductor integrated circuit is mounted and a package in which the semiconductor integrated circuit is sealed;
(F) performing a thermal simulation of the entire semiconductor integrated circuit in which the semiconductor integrated circuit is sealed in the package based on the thermal resistance;
(G) calculating a maximum thermal gradient difference based on the result of the thermal simulation;
(H) calculating a worst timing of a timing element constituting the semiconductor integrated circuit based on the calculated thermal gradient difference;
(I) A circuit simulation is performed at the worst timing based on the worst timing.

  A semiconductor integrated circuit according to another invention of the present invention is designed and manufactured based on the circuit simulation method described above.

  A circuit simulation method for a semiconductor integrated circuit according to the present invention is based on the magnitude of power of a heat source element built in a semiconductor chip, the thermal conductivity of a lead frame and package on which the semiconductor chip is mounted, and the magnitude of thermal resistance. Since circuit elements are arranged according to the actual temperature distribution and temperature gradient in the chip, a semiconductor integrated circuit having excellent temperature characteristics can be provided.

3 is a flowchart showing a method of arranging the semiconductor integrated circuit according to the first embodiment of the present invention. The schematic diagram of the lead frame applied to the arrangement | positioning method of FIG. 1, and the information collected from there are shown. 2A is a schematic diagram of a lead frame including an internal lead and an external lead, and FIG. 2B is a schematic diagram of the lead frame when the internal lead and the external lead in FIG. The lead frame information collected from each is shown. The schematic diagram of the package applied to the arrangement | positioning method of FIG. 1 and the package information collected from there are shown. The schematic diagram of arrangement | positioning of the timing element in the semiconductor chip arrange | positioned based on the arrangement | positioning method of the semiconductor integrated circuit of 1st Embodiment concerning this invention is shown. FIG. 4A shows the layout of each element, and FIG. 4B shows the temporal transition of the temperature at a point away from the heat source element by a predetermined distance. It is a flowchart which shows the circuit simulation method of the semiconductor integrated circuit of 2nd Embodiment concerning this invention. It is a thermal simulation figure for demonstrating the transient thermal analysis performed at step 208 of 2nd Embodiment shown in FIG. It is a flowchart which shows the circuit simulation method of the semiconductor integrated circuit of 3rd Embodiment concerning this invention. It is a conceptual diagram which shows time constant R1C1 applied by 3rd Embodiment, step 308,309.

(First embodiment)
FIG. 1 is a flowchart for explaining a semiconductor integrated circuit arrangement method according to the first embodiment of the present invention. Step 101 is a step of creating a circuit diagram in consideration of circuit operation when designing a circuit in general. The target circuit includes a heat source element and various logic circuits depending on the application. Examples of the circuit function including such a heat source element include an LED driver, a motor driver, and an IPD (system power supply device).

  Step 102 is a step of circuit simulation of static characteristics and dynamic characteristics along the circuit diagram created in step 101. In the circuit simulation, each node voltage in the circuit, a direct current characteristic of a current flowing through each element, a time response characteristic, a frequency response characteristic, and the like are calculated in accordance with the transistor level circuit connection information and the electrical characteristics of the elements in the circuit. For circuit simulation and thermal analysis circuit simulation, for example, SPICE (Simulation Program with Integrated Circuit Emphasis), Advanced-MS of Mentor Graphic Co., USA, etc. can be used.

  Step 103 is a step of calculating the heat generation amount by the circuit simulation in Step 102. That is, the current flowing through the circuit element during circuit operation, the applied voltage, and the power consumption are calculated including the heat source element and other circuit elements.

  Step 104 is a step of calculating the area of the heat generating portion. In the circuit simulation at step 102, the current flowing through each element and the applied voltage are obtained, so the area of the heat generating part occupying the entire semiconductor chip is calculated from these data. Most of the heat generating parts are heat source elements (power transistors). Although step 104 is not an essential component in the present invention, the heat capacity can be obtained by calculating the area of the heat generating portion, and the thermal simulation accuracy can be improved. The calculation result of the heat generating area is taken into consideration when each circuit element is arranged on the semiconductor chip in the floor plan described later. Note that step 104 may be performed before, but not after, step 103.

  Step 105 is a step of performing a floor plan. In the floor plan, the temperature distribution in the semiconductor chip is estimated based on the area of the heating element calculated in step 104, and the heat source element, each circuit element, various logic circuits, and each block element are roughly arranged in the semiconductor chip. . In the floor plan, bonding pads are arranged on the outer periphery of the semiconductor chip to take out the heat source element and each logic circuit.

  Step 106 is a step of inputting “lead frame information” to the thermal simulation software program. In this document, it is described as “lead frame information” for convenience of explanation, but is not necessarily limited to information related to the lead frame. For example, in step 106, the material, diameter, length, etc. of the bond wire may be subjected to thermal simulation. In step 106, in order to calculate the thermal conductivity and thermal resistance of the lead frame, the thermal conductivity and thermal resistance are calculated based on the material, material, size, thickness, etc. of the internal lead and external lead of the lead frame. The calculation of thermal conductivity and thermal resistance can be performed in consideration of the technical ideas disclosed in Patent Documents 2 to 5, but from the viewpoint of the convenience of thermal analysis, for example, the above-mentioned Virtuoso AMS Designer from Cadence Design Systems, USA may be used. In step 106, the heat capacity of the lead frame can be calculated, and the thermal resistance from the semiconductor chip to the lead frame is calculated. A schematic diagram of the lead frame and various information on the lead frame are shown in FIG. 2 described later.

  Step 107 is a step of inputting “package information”. The term “package information” is also used for convenience as in the “lead frame information” described above. In the package information in step 107, the thermal conductivity and thermal resistance of the semiconductor chip itself, and further the thermal conductivity, thermal resistance, thermal capacity, etc. of the resin body sealing the lead frame are calculated. Further, the thermal conductivity, thermal resistance, and thermal capacity after the above-described lead frame is sealed with the resin body are also calculated. Furthermore, the thermal conductivity and thermal resistance of the bonding wire are calculated based on the diameter and length of the bonding wire connected between the bonding pad on the semiconductor chip and the internal lead. Furthermore, when the die is fixed to some substrate instead of the lead frame, the thermal resistance of the substrate is calculated. If the substrate to which the die is fixed is attached to another substrate, the thermal conductivity and thermal resistance of the other substrate are calculated in step 107. In step 107, the heat capacity of the package can be calculated and the thermal resistance from the lead frame to the package is calculated. A schematic diagram of the package processed in step 107 and package information related thereto are shown in FIG. 3 to be described later.

  In the first embodiment, lead frame information is handled in step 106 and package information is handled in step 107. However, the order of these processing steps may be reversed. That is, package information may be handled in step 106, and lead frame information may be handled in step 107. Further, the lead frame information and the package information may be input to the thermal simulation software program in one step.

  In step 108, thermal analysis (thermal simulation) of the entire semiconductor integrated circuit is performed based on the magnitude of the thermal resistance calculated from the lead frame information in step 106 and the package information in step 107. In step 108, steady state analysis, that is, thermal simulation is performed in a state where the circuit operation is stable and the heat distribution in the semiconductor chip (die) is settled.

  Step 109 is a step of creating an isotherm in the semiconductor chip (semiconductor integrated circuit) based on the thermal simulation (steady state analysis) performed in step 108. The isotherm is a so-called temperature distribution line obtained by connecting points of the same temperature on the semiconductor chip. It is practical to create the same temperature with a certain width. The number of isotherms to be created may be determined based on the absolute values of the maximum temperature and the minimum temperature on the semiconductor chip and the temperature difference between them. For example, if the maximum temperature on the semiconductor chip is 150 ° C. and the minimum temperature is 50 ° C., for example, if isotherms are created at intervals of 20 ° C., the number is six. The isotherm is created automatically or manually.

  In step 110, timing elements are arranged on the semiconductor chip along the isotherm created in step 109. Here, the timing element refers to a transistor, a diode, a resistor, or the like that forms a logic circuit. For example, as a method of supplying a clock signal in a logic circuit, a collective driving method, a clock tree method, a combination method of both of these, and the like are known. As timing elements, clock drivers and flip-flop circuits used for these are used. Can be mentioned. Of course, each transistor constituting the flip-flop circuit also corresponds to the timing element. Note that the setup time, hold time, and delay time of the flip-flop circuit greatly affect the operation of the logic circuit, so that sufficient consideration must be given to temperature changes.

  FIG. 2 shows an example of lead frame information considered in FIG. 1 and step 106. FIG. 2A shows a schematic diagram of a lead frame to which a die (semiconductor chip) DIE is fixed. In this document, the lead frame includes a die pad (die flag), an internal lead IL, an external lead OL, and a tab lead TL. A die pad DP is provided at the center of the lead frame, and the die pad DP is supported by a tab lead TL. A die (semiconductor chip) DIE is fixed to the die pad DP. The internal lead IL is sealed in the resin sealing body EC together with the die pad DP and the tab lead TL, and the external lead OL extends to the outside of the resin sealing body EC. The lead frame has a size such as a package length E, a lead pitch e, a lead width b, a tab lead width Wtb, and a lead frame flag gap g1. In the present invention, various information regarding these various lead frames are taken into account when calculating the thermal resistivity of the entire package.

  FIG. 2B shows the internal lead frame IL in FIG. 2A and the die width Wd, the die length Ld, the die pad width Wf, the die pad length Lf, the sealing body width E1, and the sealing body length D1. The external lead frame OL is not shown. In the present invention, such information is also taken into account when calculating the thermal resistivity and heat capacity of the entire package.

  FIG. 3 shows a cross-sectional view of the package and an example of the information considered in step 107 of FIG.

  FIG. 3A shows a state where the die d is fixed on the die pad DP through the die attach (for example, solder) da inside the resin sealing body EC. In FIG. 3A, the sealing body thickness A2 and the die thickness td, which are the thicknesses of the resin sealing body EC, are taken into account in the calculation of thermal conductivity and thermal resistance. Note that the sealing body width E1 and the sealing body length D1 of the resin sealing body EC are considered in step 106, but may be used in step 107 together with the die thickness td for calculation of thermal conductivity and thermal resistance.

  FIG. 3B is a cross-sectional view of the whole image of the semiconductor integrated circuit according to the present invention, and is also a diagram in which the internal lead IL, the external lead OL, and the bond wire bw are added to FIG. In FIG. 3B, the external lead thickness tl, the lead frame height h of the external lead OL, the lead foot length Lft, the die pad downset ddf which is the distance from the die pad DP to the internal lead IL, and the bottom of the resin sealing body EC The package standoff A1, which is the distance to the end of the external lead OL, and the bond wire bw are used for calculation of thermal conductivity and thermal resistance.

FIG. 3C shows another semiconductor integrated circuit according to the present invention. 3 (c) is different from FIG. 3 (b) in that the die d is placed on the metal placement portion Hra via the die attach da, and the metal placement portion Hra is further attached to the board B via the solder s. It is structured to be attached to a land L that is an attachment portion. In FIG. 3C, the volume of the resin sealing body EC is smaller than that of FIG. 3B, and the metal mounting portion Hra is provided. Since heat is rapidly radiated to the outside through the mounting portion Hra, the thermal resistance of the entire integrated circuit device is smaller than that in FIG. In FIG. 3C, the thermal resistance and thermal resistance corresponding to the materials and materials of the metal mounting portion Hra, the solder s, the land L, and the board B are calculated.

  FIG. 3D shows the bond wire length Lbw and the bond wire diameter dbw of the bond wire bw shown in FIGS. 3B and 3C. The material of the bond wire bw has higher thermal conductivity in the order of aluminum (Al), gold (Au), and copper (Cu). Therefore, the heat transfer is the slowest with three metals of aluminum (Al). In addition, the thermal conductivity varies with temperature. In general, the lower the temperature, the higher the thermal conductivity of the metal, and the faster the heat conduction. In the present invention, thermal simulation is performed in consideration of the thermal conductivity of the bond wire. In addition to the material, diameter, and length of the bond wire bw, the number of bond wires is used for calculation of the thermal simulation.

  In addition, the three-dimensional shape of a package can be created by inputting each piece of information considered in steps 106 and 107 to CAD (computer-aided design) software. By grasping the three-dimensional shape, an overall image of the semiconductor integrated circuit can be grasped, and it can be determined whether or not the input of lead frame information and package information to the thermal simulation software is appropriate. That is, one of the features of the present invention is to perform an optimal thermal simulation while grasping a member to be subjected to the thermal simulation in a three-dimensional shape.

  FIG. 4 is a diagram for explaining the arrangement in step 110 of FIG. 1 and the temperature distribution on the semiconductor chip. FIG. 4a is an example when the timing element is arranged on the isotherm of the semiconductor chip, and FIG. 4b is a schematic diagram showing the temperature difference between the heat source element and the reference point.

  FIG. 4A shows a state in which the heat source element 2 is arranged at one corner of the semiconductor chip (die) 1 and the reference point 3 is provided in the vicinity of the heat source element 2. A monitoring element for measuring a so-called temperature is placed at the reference point 3. The first isotherm L1 is formed by connecting a point that is a predetermined temperature, for example, 20 ° C. lower than the center of the heat source element 2. The second isotherm L2 is formed by connecting points that are, for example, 20 ° C. lower than the first isotherm L1. The third isotherm L3 is formed by connecting points that are, for example, 20 ° C. lower than the second isotherm L2. Therefore, the second isotherms L2 and L3 are formed by connecting points that are 40 ° C. and 60 ° C. lower than the center of the heat source element 2, respectively.

  On the first isotherm L1, first timing elements 21, 22, 23 and 24 are arranged. Each of the first timing elements 21 to 24 may be a single transistor or a combination of several transistors, for example, a flip-flop circuit.

  Second timing elements 31, 32, 33 and 34 are arranged on the second isotherm L2. Similarly to the first timing element, the second timing elements 31 to 34 are each a single transistor, or may be, for example, a flip-flop circuit in which several transistors are combined.

  Third timing elements 41, 42, 43 and 44 are arranged on the third isotherm L3. Similarly to the first and second timing elements, the third timing elements 41 to 44 may each be a single transistor or may be, for example, a flip-flop circuit in which several transistors are combined.

  When the circuit block of the logic circuit is highly integrated, the number of stages of the flip-flop circuits is large, and the same circuit portion extends across the first isotherm L1, the second isotherm L2, and the third isotherm L3. In some cases, a transistor or a flip-flop circuit constituting the circuit must be arranged. In such a case, the arrangement may be determined in consideration of the setup time, hold time, and delay time required for the flip-flop circuit. That is, when the ratio occupied by the timing elements becomes high and it is difficult to place all the timing elements in the vicinity of one isotherm, they may be arranged in the vicinity of a plurality of isotherms. For example, the timing elements 21 to 24 are disposed on the isotherm L1, the timing elements 31 to 34 are disposed on the thermal isotherm L2, and the timing elements 41 to 44 are disposed on the isotherm L3. After the operation of the timing elements 21 to 24 is completed, a margin time is defined as the sum of a signal transmission time, a deviation during signal transmission, for example, a setup time and a hold time of 10%, and a delay time caused by a temperature difference between the elements in a steady state Provided to operate the timing elements 31-34. Similarly, between the timing elements 31 to 34 and the timing elements 41 to 44, a sum of a signal transmission time, a deviation time during signal transmission, and a delay time caused by a temperature difference between the elements in a steady state is provided. Thereby, a margin between the timing elements can be secured by the heat generation of the heat source element 2.

  FIG. 4B shows the temporal change in energy generated in the heat source element 2 shown in FIG. 4A and the thermal gradient between the heat source element 2 and the reference point 3 provided in the vicinity of 2 of the heat source element. The horizontal axis indicates time t.

  When electric power is supplied to the heat source element 2 at time t0, the supplied electric power instantaneously has a peak value, and thus the heat source element 2 instantaneously generates maximum energy. However, when time t1, t2, which is a relatively short time, is reached, the magnitude becomes constant at a predetermined magnitude.

  Here, attention is paid to the temperature difference between the heat source element 2 and the reference point 3. Since the heat source element 2 gradually generates heat during the period from time t0 to t1, the temperature of the heat source element 2 itself gradually increases. In addition, since the heat transfer from the heat source element 2 is not sufficiently transferred to the reference point 3, the temperature difference between the two gradually increases from time t0 to time t1. At time t1, although the heat source element 2 reaches the maximum temperature, since the heat transfer of the heat source element 2 is not sufficient at the reference point 3, the temperature difference between the two becomes the maximum value Tmax, and the thermal gradient between the two becomes the maximum. . In order to obtain the maximum value of the thermal gradient, that is, the maximum value Tmax of the temperature difference, the interval between times t0 and t2 is sampled with a pulse signal, and the peak value of the temperature is obtained. For this purpose, sampling is performed at time steps in the range of, for example, 1/3 to 1/20 of the RC time constant, which is the product of the thermal resistance R and the lead frame information obtained in steps 106 and 107, and the heat capacity C obtained from the package information. And ask. It should be noted that the sampling is not performed once. For example, the first time may be obtained by narrowing the temperature range roughly at time step 1/3 and then finely sampling the range at time step 1/5, for example.

  From time t <b> 1 to t <b> 2, the temperature of the heat source element 2 reaches the maximum temperature, and the thermal energy generated in the heat source element 2 is transmitted to the reference point 3. In this section, the temperature difference between the two decreases as the thermal energy transmitted to the reference point 3 increases and is sufficiently propagated at time t2, so that the temperature difference between the two becomes a steady value Tcons.

  The heat distribution and the thermal gradient are not limited to the present invention, and the following can be generally said. For example, when it is assumed that heat is uniformly generated from the die d in FIGS. 2 and 3 described above, the heat energy balance within the unit time is as follows: the heat generation amount W1 is the heat amount Q1 flowing in the die d and the surrounding convection. Is the sum of the amount of heat Q2 taken away, and can be expressed by the following formula 1.

Further, the amount of heat Q1 generated in the die d within a unit time can be expressed by the following formula 2 according to Fourier's heat conduction law.

Here, T is temperature (K), t is time (s), KT is thermal conductivity (W / (m · K)), ρ is density (kg / m ³ ), CP is constant pressure specific heat (J / ( kg · K)), ∇ is the Laplace operator, and V is the volume (m ³ ). Further, the amount of heat Q2 taken away by the surrounding convection within a unit time satisfies Newton's law of cooling, and can be expressed by the following Equation 3.

Here, A is the area (m ² ), h is the heat transfer coefficient (W / m ² · k), and Tm is the ambient temperature (K). By applying the lead frame information and package information according to the present invention to the above formula (1), it is possible to grasp the temperature change of the heat source element alone, the entire semiconductor integrated circuit, and each part.

  In the present invention, the arrangement on the isotherm is not limited to the timing element. For example, a differential amplifier or a current mirror circuit that requires the same temperature characteristics may be used.

(Second Embodiment)
FIG. 5 is a flowchart for explaining a circuit simulation method for a semiconductor integrated circuit according to the second embodiment of the present invention. In the second embodiment, it is assumed that heat generation or heat transfer of the heat source element is intermittent, or there are a plurality of heat source elements that generate relatively large heat, that is, a steady state does not exist. Yes. In such a case, the timing design and the arrangement of the timing elements are based on the maximum value of the temporal deviation between the plurality of timing elements in the semiconductor integrated circuit due to the change in the thermal gradient in the semiconductor integrated circuit due to the heat generated by the heat source element. Considering the above, a semiconductor integrated circuit is designed and manufactured.

  FIG. 5 includes steps 201 to 211. Among these steps, each of steps 201 to 207 corresponds to each of steps 101 to 107 of the first embodiment.

  Step 201 is a step of creating a circuit diagram in consideration of circuit operation when designing a circuit in general. The target circuit includes a heat source element, various logic circuits, and a timing element depending on the application. Examples of the circuit function including such a heat source element include an LED driver, a motor driver, and an IPD (system power supply device).

  Step 202 is a step of circuit simulation of static characteristics and dynamic characteristics along the circuit diagram created in step 201. In the circuit simulation, each node voltage in the circuit, a direct current characteristic of a current flowing through each element, a time response characteristic, a frequency response characteristic, and the like are calculated in accordance with the transistor level circuit connection information and the electrical characteristics of the elements in the circuit. For circuit simulation and thermal analysis circuit simulation, for example, SPICE (Simulation Program with Integrated Circuit Emphasis), Virtuoso AMS Designer of Cadence Design Systems, Inc., USA, and the like can be used.

  Step 203 is a step of calculating the heat generation amount by the circuit simulation in Step 202. In other words, the heat source element and other circuit elements are calculated based on the current flowing in the circuit element during circuit operation and the applied voltage.

  Step 204 is a step of calculating the area of the heating element. In the circuit simulation at step 202, the current flowing through each circuit element and the applied voltage are obtained, so the area of the heat generating part occupying the entire semiconductor chip is calculated from these data. In the heat generating portion, not only the heat source element but also a relatively large heat generating element is targeted. Obtaining the area of the heat generating portion is not an essential constituent element in the present invention, but is taken into consideration when arranging each circuit element when performing a floor plan described later.

  Step 205 is a step of performing a floor plan. In the floor plan, the temperature distribution in the semiconductor chip is estimated based on the area of the heating element calculated in step 204, and the heat source element, each circuit element, various logic circuits, and each block element are roughly arranged in the semiconductor chip. . In the floor plan, bonding pads are arranged on the outer periphery of the semiconductor chip to take out the heat source element and each logic circuit.

  Step 206 is a step of inputting “lead frame information” to the thermal simulation software program. In this document, it is described as “lead frame information” for convenience of explanation, but is not necessarily limited to information related to the lead frame. For example, in step 206, the material, diameter, length, etc. of the bond wire may be the target of the thermal simulation. In step 206, in order to calculate the thermal conductivity and thermal resistance of the lead frame, the thermal conductivity and thermal resistance are calculated based on the material, material, size, thickness, etc. of the internal lead and external lead of the lead frame. The calculation of thermal conductivity and thermal resistance can be performed in consideration of the technical ideas disclosed in Patent Documents 2 to 5, but from the viewpoint of the convenience of thermal analysis, for example, the above-mentioned Virtuoso AMS Designer from Cadence Design Systems, USA may be used. A schematic diagram of the lead frame and various information of the lead frame related thereto are shown in FIG.

  Step 207 is a step for inputting “package information”. The term “package information” is also used for convenience as in the “lead frame information” described above. In the package information in step 107, the thermal conductivity and thermal resistance of the semiconductor chip itself, and further the thermal conductivity and thermal resistance of the resin body that seals the lead frame are calculated. Further, the thermal conductivity, thermal resistance, and thermal resistance after the above-described lead frame is sealed with the resin body are also calculated. Furthermore, the thermal conductivity and thermal resistance of the bonding wire are calculated based on the diameter and length of the bonding wire connected between the bonding pad on the semiconductor chip and the internal lead. Furthermore, when the die is fixed to some substrate instead of the lead frame, the thermal resistance of the substrate is calculated. If the substrate to which the die is fixed is attached to another substrate, the thermal conductivity and thermal resistance of the other substrate are calculated in step 207. The schematic diagram of the package processed in step 207 and the package information related thereto are shown in FIG.

  In the second embodiment, lead frame information is handled in step 206 and package information is handled in step 207. However, the order of these processing steps may be reversed. That is, package information may be handled in step 206 and lead frame information may be handled in step 207. Further, the lead frame information and the package information may be input to the thermal simulation software program in one step.

  Step 208 is a step of performing a thermal simulation. In step 108 of the first embodiment, after heat transfer of the heat source element is stabilized, that is, in a steady state, a thermal simulation is performed between the heat source element and the monitor point on the semiconductor chip, but step 208 of the second embodiment. Performs heat simulation in a state where heat generation and heat transfer of the heat source element are changed, that is, in a transient state.

  Step 209 is a step for extracting the maximum thermal gradient in the semiconductor chip. In other words, the maximum temperature difference between a predetermined position in the semiconductor chip and the reference point is subjected to thermal simulation by the same method as that used in the first embodiment, and the maximum thermal gradient of the entire semiconductor chip is calculated. .

  Step 210 is a step of calculating the worst timing between the timing element to be arranged and other timing elements based on the maximum thermal gradient calculated in step 209. In order to calculate the worst timing, the maximum temperature difference Tmax shown in FIG. 4B must be obtained. For this purpose, first, an RC time constant that is a product of the thermal resistance R and the thermal capacity C is obtained from the lead frame information and the package information. Next, the temperature difference between times to to t2 is obtained in a time step sufficiently smaller than the RC time constant. The time step can be selected from 1/3 to 1/20 of the time constant RC, for example. Thus, the maximum value Tmax at the worst timing can be accurately grasped.

  In step 211, the worst timing circuit simulation of the semiconductor integrated circuit is performed in consideration of the worst timing calculated in step 210. The worst timing occurs when a margin provided between timing elements reaches a limit value (minimum margin value). Therefore, since the timing element is arranged on the semiconductor chip in consideration of the worst timing, it is possible to prevent a malfunction of the circuit caused by, for example, insufficient margin of the setup time, hold time, and delay time of the timing element.

  When there are a plurality of heat source elements, for example, when the heat source element 2 is constituted by the heat source element 2a and the heat source element 2b, the heat source element 2a and the heat source element 2b take into account the on / off timing of the heat source element 2a and the heat source element 2b. Simulate the temperature distribution characteristics of the gradient. That is, for example, when the operation pattern a and the operation pattern b are present, the reference point with the time transition of the heat source element 2a and the heat source element 2b based on the energy of the heat source element 2a and the heat source element 2b at the time of each operation pattern. Calculate the temperature difference from the (monitor point).

  When calculating the maximum temperature difference Tmax, that is, the thermal gradient difference, the material conditions in Step 206 and Step 207 may be the best conditions. That is, package external conditions, internal die bonding, and wire bonding are set to ideal conditions, for example, the thermal resistance is set to a range of, for example, 0 to 0.5 times that of the substance, while a semiconductor integrated circuit (semiconductor The thermal resistance of aluminum (Al), copper (Cu), gold (Au), or a mixture of these with silicon, for example, or a refractory metal material, which is a wiring material used for the internal wiring of the chip) Is selected in the range of 10 to 1 times the actual size, and thermal simulation is performed. By such setting, the maximum temperature difference Tmax can be accurately grasped, and therefore, sufficient margins with timing element setup time, hold time, and delay time can be secured.

  FIG. 6 is a diagram illustrating step 208 of the second embodiment shown in FIG. 5, for example, a case where heat generation of the heat source element 2 of FIG. 2 occurs intermittently. For example, when the heat source element 2 is a high-side transistor of a DC / DC converter (not shown), generally, the high-side transistor is controlled to be turned on / off by a drive signal of pulse width modulation (PWM). The

  FIG. 6A is a waveform showing a change in thermal energy of the heat source element 2. For example, when the heat source element 2 is an n-type MOS transistor, the drive signal for controlling the heat source element 2 has substantially the same waveform. At times t11 to t12, t13 to t14, t15 to t16, and times t17 to t18, the drive signal is at a high level H, the heat source element 2 is turned on, and energy is consumed. At time t12 to t13, t14 to t15, t15 to t16, and after time t18, the drive signal is at the low level L, the heat source element 2 is turned off, and the operation is stopped.

  FIG. 6B is a diagram showing a change in temperature difference between the reference point 3 and the heat source element 2 when the heat energy of the heat source element 2 changes as shown in FIG. The temperature difference between the reference point 3 and the heat source element 2 rises at time t11 to t12, t13 to t14, t15 to t16, and time t17 to t18, and after time t12 to t13, t14 to t15, t15 to t16, and time t18. To descend. The temperature difference calculation method in this case is the same as the temperature difference calculation method obtained in the first embodiment. In the second embodiment, the temperature difference becomes the maximum ΔTmax at times t12, t14, and time t16. Note that the time at which the maximum temperature difference ΔTmax occurs exists in addition to the times t12, t14, and t16.

(Third embodiment)
FIG. 7 is a flowchart showing a circuit simulation method of the semiconductor integrated circuit according to the third embodiment. The third embodiment is applied, for example, when applied to circuit simulation of the semiconductor integrated circuit designed and manufactured in the first embodiment or the second embodiment of the present invention. That is, the third embodiment is used when verifying whether or not the arrangement of the timing elements in the already manufactured and completed semiconductor integrated circuit is appropriate. The third embodiment includes steps 301 to 310, but each of steps 301 to 304 is the same as each of steps 201 to 204 in the second embodiment.

  Step 301 is a step of creating a circuit diagram in consideration of circuit operation when designing a circuit in general. The target circuit includes a heat source element, various logic circuits, and a timing element depending on the application. Examples of the circuit function including such a heat source element include an LED driver, a motor driver, and an IPD (system power supply device).

  Step 302 is a step of circuit simulation of static characteristics and dynamic characteristics along the circuit diagram created in step 301. In the circuit simulation, each node voltage in the circuit, a direct current characteristic of a current flowing through each element, a time response characteristic, a frequency response characteristic, and the like are calculated in accordance with the transistor level circuit connection information and the electrical characteristics of the elements in the circuit. For circuit simulation and thermal analysis circuit simulation, for example, SPICE (Simulation Program with Integrated Circuit Emphasis), Virtuoso AMS Designer of Cadence Design Systems, Inc., USA, and the like can be used.

  Step 303 is a step of calculating the heat generation amount by the circuit simulation in Step 302. In other words, the heat source element and other circuit elements are calculated based on the current flowing in the circuit element during circuit operation and the applied voltage.

  Step 304 is a step of calculating the area of the heating element. In the circuit simulation of step 302, the current flowing through each circuit element and the applied voltage are obtained, so the area of the heat generating part occupying the entire semiconductor chip is calculated from these data. In the heat generating portion, not only the heat source element but also a relatively large heat generating element is targeted. Obtaining the area of the heat generating portion is not an essential constituent element in the present invention, but is taken into consideration when arranging each circuit element when performing a floor plan described later.

  Steps 305 to 307 are the same as steps 206 to 208 in the second embodiment. In the third embodiment, since the elements in the semiconductor integrated circuit are already arranged, step 105 in the first embodiment and step 205 in the second embodiment are not necessary.

  Step 306 is a step of inputting “lead frame information” to the thermal simulation software program. In this document, it is described as “lead frame information” for convenience of explanation, but is not necessarily limited to information related to the lead frame. For example, in step 306, the material, diameter, length, etc. of the bond wire may be subjected to thermal simulation. In step 306, in order to calculate the thermal conductivity and thermal resistance of the lead frame, the thermal conductivity and thermal resistance are calculated based on the material, material, size, thickness, etc. of the internal lead and external lead of the lead frame. The calculation of thermal conductivity and thermal resistance can be performed in consideration of the technical ideas disclosed in Patent Documents 2 to 5, but from the viewpoint of the convenience of thermal analysis, for example, the above-mentioned Virtuoso AMS Designer from Cadence Design Systems, USA may be used. A schematic diagram of the lead frame and various information of the lead frame related thereto are shown in FIG.

  Step 307 is a step for inputting “package information”. The term “package information” is also used for convenience as in the “lead frame information” described above. In the package information in step 307, the thermal conductivity and thermal resistance of the semiconductor chip itself, and further the thermal conductivity and thermal resistance of the resin body that seals the lead frame are calculated. Further, the thermal conductivity and thermal resistance after the above-described lead frame is sealed with the resin body are also calculated. Furthermore, the thermal conductivity and thermal resistance of the bonding wire are calculated based on the diameter and length of the bonding wire connected between the bonding pad on the semiconductor chip and the internal lead. Furthermore, when the die is fixed to some substrate instead of the lead frame, the thermal resistance of the substrate is calculated. If the substrate on which the die is fixed is attached to another substrate, the thermal conductivity and thermal resistance of the other substrate are calculated in step 307. The schematic diagram of the package processed in step 307 and the package information related thereto are shown in FIG.

  In the third embodiment, lead frame information is handled in step 306 and package information is handled in step 307. However, the order of these processing steps may be reversed. That is, package information may be handled in step 306 and lead frame information may be handled in step 307. Further, the lead frame information and the package information may be input to the thermal simulation program in one step.

  Step 308 is a step for performing a thermal simulation. In step 108 of the first embodiment, a heat simulation between the heat source element 2 and the reference point 3 (monitor point) on the semiconductor chip is performed after the heat transfer of the heat source element is stabilized, that is, in a steady state. In step 308 of the third embodiment, thermal simulation is performed in a state where heat generation and heat transfer of the heat source element 2 are changed, that is, in a transient state.

  Step 308 is a step of extracting the position maximum thermal gradient from the thermal gradient for each time and each pattern calculated in step 307. Comparing step 308 with step 209 in the second embodiment, the implementation method is the same, but the accuracy of the obtained thermal gradient is different. The arrangement of circuit elements in the second embodiment is a rough floor plan, and simulation is performed with a rough arrangement, whereas in the third embodiment, circuit simulation is performed after arrangement of circuit elements, particularly timing elements, is completed. Therefore, since the setup time, hold time, etc. can be accurately grasped, these margin settings can be utilized in the design and manufacture of the next semiconductor integrated circuit.

  Step 309 is a step of feeding back the setup time, hold time, and delay time information based on the maximum thermal gradient obtained in Step 308 to each circuit element, particularly the timing element. For example, when there is a temperature difference between timing elements with signal transmission, a time delay due to the temperature difference is converted into a time constant R1C1 and fed back. Such feedback enables more accurate circuit simulation.

  Step 310 is a step of performing a final circuit simulation after replacing the delay time obtained in Step 309 with the time constant R1C1. This circuit simulation may be performed statically or dynamically. According to such circuit simulation and thermal simulation, it is possible to accurately grasp the delay time of the data signal and the clock signal input to the timing element.

  FIG. 8 is a conceptual diagram showing time constants applied in the third embodiment, steps 308 and 309. In FIG. 8A, since both the D flip-flop FF1 and the D flip-flop FF2 are placed at a temperature of 25 ° C., there is no temperature difference between them. In this case, the time constant interposed between the two is zero. FIG. 8B shows a state where the D flip-flop FF1a is placed at a temperature of 25 ° C. and the D flip-flop FF1b is placed at a temperature of 80 ° C. In such a case, a temperature difference of 55 ° C. occurs between the two. Due to such a temperature difference, both cause a delay time, and the delay time is indicated by a time constant R1C1 of the resistor R1 and the capacitor C1. In the third embodiment, such thermal information is fed back to the timing element, and circuit simulation is performed again in the fed back state. Through such circuit simulation, it is possible to perform thermal analysis in line with the substance. Each D flip-flop has an input terminal CP1, a D input terminal D1, and Q output terminals Q1 and Q2.

  As described above, according to the semiconductor integrated circuit arrangement method and circuit simulation method of the present invention, the setup time, hold time, and delay time of the timing element including the heat source element are accurately determined based on the lead frame information and the package information. Since it can be grasped, it is possible to provide a semiconductor integrated circuit whose circuit operation is stable with respect to a temperature change. Therefore, its industrial applicability is extremely high.

1 Semiconductor chip (semiconductor integrated circuit)
2 Heat source element 3 Reference point (monitor point)
21-24, 31-34, 41-44 Timing element A1 Package standoff A2 Sealing body thickness b Lead width B Board bw Bond wire d Die (semiconductor chip)
D1 Sealing body length da Die attach dbw Bond wire diameter ddf Die pad down set DP Die pad (Die flag)
e Lead pitch E Package length E1 Sealed body width EC Resin sealed body gl Flag gap h Lead frame height Hra Metal placement L Land L1, L2, L3 Isotherm Lbw Bond wire length Ld Die length Lf Die pad length Lft Lead Foot length OL External lead s Solder td Die thickness TL Tab lead tl Lead width Wd Die width Wf Die pad width Wtb Tab lead width

Claims (8)

Creating a circuit diagram of a semiconductor integrated circuit including a heat source element;
Performing circuit operation simulation of the semiconductor integrated circuit based on the circuit diagram;
Calculating a heat generation amount of the semiconductor integrated circuit based on the circuit operation simulation;
Performing a floor plan of the semiconductor integrated circuit with reference to the calculated calorific value;
Inputting a thermal resistance to thermal simulation software based on various information of a lead frame on which the semiconductor integrated circuit is mounted and a package in which the semiconductor integrated circuit is sealed;
Performing a thermal simulation of the entire semiconductor integrated circuit in which the semiconductor integrated circuit is sealed in the package based on the thermal resistance;
Calculating a maximum thermal gradient difference based on the result of the thermal simulation;
Calculating a worst timing of a timing element constituting the semiconductor integrated circuit based on the calculated thermal gradient difference;
A circuit simulation method for a semiconductor integrated circuit, comprising: performing a circuit simulation at the worst timing based on the worst timing.   2. The circuit simulation method for a semiconductor integrated circuit according to claim 1, wherein the timing element is a flip-flop circuit.   3. The circuit simulation method for a semiconductor integrated circuit according to claim 2, wherein the worst timing of the flip-flop circuit is calculated from a setup time, a hold time, and a delay time.   The maximum thermal gradient difference is obtained in a time step of 1/3 to 1/20 of an RC time constant that is a product of a thermal resistance R and a thermal capacity C calculated from the lead frame information and the package information. A circuit simulation method for a semiconductor integrated circuit according to claim 1.   5. When calculating the thermal gradient difference, the magnitude of the thermal resistance calculated from the lead frame information and the package information is obtained in a range of 10 times to 1 time of the substance. A circuit simulation method for a semiconductor integrated circuit.   5. The semiconductor integrated circuit according to claim 4, wherein, in calculating the thermal gradient difference, a thermal resistance of a wiring material used for an internal wiring of the semiconductor integrated circuit is performed in a range of 10 times to 1 time of the substance. Circuit simulation method.   A semiconductor integrated circuit designed and manufactured based on the circuit simulation method for a semiconductor integrated circuit according to claim 1.   The semiconductor integrated circuit according to claim 7, wherein the semiconductor integrated circuit has a circuit function of any one of an LED driver, a power supply circuit, an intelligent power device, and a central processing unit.