JP6655305B2 - Method of arranging semiconductor integrated circuit and semiconductor integrated circuit - Google Patents

Description

  The present invention relates to an arrangement method of a semiconductor integrated circuit and a semiconductor integrated circuit designed and manufactured based on the arrangement method.

  For example, in a layout of a semiconductor integrated circuit having a built-in heat source element through which a large current flows, such as various driver integrated circuits, a power supply integrated circuit, a CPU (Central Processing Unit), and an IPD (Intelligent Power Device), heat measures have been taken. There are not many things.

  Patent Literature 1 discloses a method of arranging a heat source element and a temperature dependent element such that two or more temperature dependent elements have substantially the same temperature change.

  Patent Literature 2 discloses an automatic semiconductor integrated circuit arranging method in which circuit blocks that generate a large amount of power consumption are distributed and arranged on a semiconductor substrate to make the temperature distribution on the semiconductor substrate uniform. For this purpose, in a method of grouping basic logic circuits by function into circuit blocks and automatically arranging a plurality of circuit blocks on a semiconductor substrate, a simulation output result obtained by simulating a circuit operation and a basic logic circuit The power consumption of the circuit block is calculated using the power consumption calculation rule file storing the means for calculating the power consumption. The circuit blocks are arranged on the semiconductor substrate so as to average the power consumption per unit area by using the calculation result, the circuit connection information, and the arrangement restriction means for arranging and wiring the basic logic circuit on the semiconductor substrate. Is what you do.

  Patent Literature 3 discloses a method of calculating the thermal resistance of a heat radiation path from a surface mount device. By designing using such a thermal resistance calculation method as a means, it is possible to design and manufacture a device having high heat reliability.

  Patent Literature 4 states that a semiconductor integrated circuit is designed with good workability even when the semiconductor integrated circuit is scaled up and highly integrated, and a method of designing a semiconductor integrated circuit system having excellent thermal characteristics is provided. For this purpose, a semiconductor integrated circuit (LSI) including a housing for housing the system, a mounting board housed in the housing and constituting the system, and a package board mounted on the mounting board, based on the system specification information. A first step of designing the device, a step of performing thermal analysis of at least one of the mounting board and the semiconductor integrated circuit in the housing based on the design result obtained in the first step, and a step of performing thermal analysis. A second step of designing a semiconductor integrated circuit system based on the analysis result is included. According to Patent Document 4, by optimizing the element arrangement of a semiconductor integrated circuit based on not only internal conditions of the semiconductor integrated circuit but also thermal analysis information of a mounting board including a housing and a package board, a mounting board, It is stated that it is possible to optimize the entire package substrate and semiconductor integrated circuit.

  Patent Literature 5 considers the position information of a heat source when designing the layout of an electronic circuit, and says that optimum electrical characteristics can be obtained by this. For this purpose, in an electronic circuit arrangement creating apparatus for creating an arrangement of an electronic circuit including a plurality of circuit blocks and at least one heat source, circuit netlist data including a netlist of a first circuit block; A circuit simulation is performed based on. Based on the simulation result data, a heat source position calculating means for searching for a heat source and calculating a heat source position, a calculated heat source position, and arrangement information of all circuit blocks based on a previously input floor plan, A heat source relative position calculating means for calculating a heat source relative position for calculating a relative position of the heat source; and a heat source based on the calculated relative position of the heat source when the arrangement of the second circuit block different from the first circuit block is created. The arrangement heat source display control means for controlling the display of the symbol (2) at a specified relative position of the second circuit block.

JP-A-7-322286 JP-A-9-266254 JP-A-64-13445 JP 2008-102631 A JP 2013-161352 A

  Patent Document 1 can improve the thermal matching between temperature-dependent elements in a semiconductor integrated circuit in which a heat source element and a temperature-dependent element coexist. However, the size and thickness of the semiconductor chip and the thermal resistance of the package on which the semiconductor substrate is mounted are not taken into consideration. For this reason, it cannot be said that the semiconductor chips are properly arranged along the heat distribution and the thermal gradient in the semiconductor chip.

  In Patent Document 2, in paragraph 0025, a simulation of heat conduction including a semiconductor chip and a package is executed to determine a chip temperature per unit area in the chip, and the difference between the maximum temperature Tmax and the minimum temperature Tmin on the chip is allowable. It is calculated whether the temperature is within the temperature Tc. If the temperature is not within the allowable temperature Tc, it is suggested that the circuit block is divided again to measure the dispersion of the power consumption. However, it does not disclose or suggest a specific method of simulating thermal conductivity and thermal resistance.

  Patent Document 3 discloses that the thermal resistance of a semiconductor chip and a package is obtained, but does not disclose or suggest a method of arranging circuit elements on the semiconductor chip.

  Patent Document 4 discloses that after performing a thermal analysis in designing a semiconductor integrated circuit system, based on the analysis result, the element arrangement of the semiconductor integrated circuit, the mounting structure on a package substrate, the arrangement on a mounting substrate, and the like are described. Since it has been determined, it can be expected that a semiconductor integrated circuit system having excellent thermal characteristics will be realized. However, since the target of thermal analysis does not consider the size and thickness of the semiconductor chip, the diameter and length of the bonding wire, the size of the die pad (die flag), etc., it is possible to grasp the appropriate heat distribution and thermal gradient in the semiconductor chip I can't expect to do that.

  Patent Document 5 discloses that, based on netlist data of a circuit block including a heat source in an entire electronic circuit and a simulation result, a heat source generated in the circuit block is calculated by a heat source position calculation unit to calculate a heat source position. Therefore, there is no possibility that the determination of the heat source is omitted. However, as in Patent Document 4, the object of the thermal analysis does not consider the size and thickness of the semiconductor chip, the diameter and length of the bonding wire, the size of the die pad, and the like. We cannot expect to know.

  An object of the present invention is to overcome the above problems and disadvantages. For this purpose, the size (area) of the heat source element built into the semiconductor chip, the power consumption, the size of the semiconductor chip, the diameter and length of the bonding wire, the size of the die pad (die flag), and the sealing of the semiconductor chip are performed. Calculate the thermal conductivity of the package size, shape, material, material, etc. Based on the calculation results, a temperature distribution and a temperature gradient in the semiconductor chip are obtained, and various circuit elements are arranged or a circuit simulation is performed in the semiconductor integrated circuit (semiconductor chip) based on the temperature distribution and the temperature gradient. A circuit is manufactured.

  In this document, a “timing element” refers to a transistor or a logic circuit used for a logic circuit. As a typical example of the logic circuit, a flip-flop circuit can be given. The “lead frame information” refers to at least one of a shape, a material, a material, various physical characteristics, a size, a thickness, and the like of a lead frame which is a metal strip on which a semiconductor chip is mounted. The “package information” refers to at least one of the shape, material, material, various physical constants and characteristics, size, thickness, and the like of the sealing body that seals a part of the lead frame and the semiconductor chip. . The physical characteristics typically include thermal conductivity, thermal resistance, and thermal capacity irrespective of lead frame information and package information. In this document, a “semiconductor chip” refers to a small piece obtained by dividing a semiconductor substrate on which a semiconductor integrated circuit is formed. The “isothermal line” refers to a so-called temperature distribution line obtained by connecting points having the same temperature on a semiconductor chip.

The method for arranging a semiconductor integrated circuit according to the present invention includes:
(A) creating a circuit diagram of a semiconductor integrated circuit;
(B) performing a circuit operation simulation of the semiconductor integrated circuit based on the circuit diagram;
(C) calculating a heat value of the semiconductor integrated circuit based on the circuit operation simulation;
(D) performing a floor plan of the semiconductor integrated circuit with reference to the calculated heat value;
(E) calculating a thermal resistance based on lead frame information on which the semiconductor integrated circuit is mounted and package information on which the semiconductor integrated circuit is sealed along the floor plan;
(F) performing a thermal simulation of the entire semiconductor integrated circuit sealed in the package based on the calculated thermal resistance;
(G) creating an isotherm (temperature distribution line) of the semiconductor integrated circuit based on the result of the thermal simulation;
(H) arranging at least a timing element on the semiconductor chip along the isotherm.

  Another aspect of the present invention is a semiconductor integrated circuit designed and manufactured based on the above arrangement method.

  The method for arranging a semiconductor integrated circuit according to the present invention is based on the magnitude of the power of the heat source element built into the semiconductor chip, the thermal conductivity of the lead frame and package on which the semiconductor chip is mounted, and the magnitude of the thermal resistance. Since the temperature distribution and the temperature gradient in the inside are grasped according to the actual situation and the circuit elements are arranged, a semiconductor integrated circuit having excellent temperature characteristics can be provided.

4 is a flowchart illustrating a method of arranging the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 2 shows a schematic view of a lead frame applied to the arrangement method of FIG. 1 and information collected therefrom. FIG. 2A is a schematic view of a lead frame including an internal lead and an external lead, and FIG. 2B is a schematic view of the lead frame when the internal lead and the external lead in FIG. Respectively show the lead frame information collected from. FIG. 2 shows a schematic diagram of a package applied to the arrangement method of FIG. 1 and package information collected therefrom. FIG. 1 is a schematic diagram of an arrangement of timing elements in a semiconductor chip arranged based on an arrangement method of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 4A shows an arrangement diagram of each element, and FIG. 4B shows a temporal transition of the temperature at a point separated by a predetermined distance from the heat source element. 6 is a flowchart illustrating a circuit simulation method for a semiconductor integrated circuit according to a second embodiment of the present invention. FIG. 6 is a thermal simulation diagram for explaining a transient thermal analysis performed in step 208 of the second embodiment shown in FIG. 5. 11 is a flowchart illustrating a circuit simulation method for a semiconductor integrated circuit according to a third embodiment of the present invention. FIG. 13 is a conceptual diagram showing a time constant R1C1 applied in steps 308 and 309 in the third embodiment.

(1st Embodiment)
FIG. 1 is a flowchart illustrating a method for arranging a semiconductor integrated circuit according to a first embodiment of the present invention. Step 101 is a step of creating a circuit diagram in consideration of the circuit operation when designing a circuit. The target circuit includes a heat source element and various logic circuits depending on the application. Circuit functions including such a heat source element include, for example, an LED driver, a motor driver, an IPD (system power supply), and the like.

  Step 102 is a step of performing circuit simulation of static characteristics and dynamic characteristics according to the circuit diagram created in step 101. In the circuit simulation, DC characteristics, time response characteristics, frequency response characteristics, and the like of each node voltage in the circuit, current flowing in each element, and the like are calculated in accordance with circuit connection information at a transistor level and electrical characteristics of elements in the circuit. For the circuit simulation and the thermal analysis circuit simulation, for example, SPICE (Simulation Program with Integrated Circuit Emphasis), Advanced-MS of Mentor Graphic Co., USA, or the like can be used.

  Step 103 is a step of calculating the amount of heat generated by the circuit simulation in step 102. That is, the current flowing to the circuit element during the circuit operation, the applied voltage, and the power consumption are calculated including the heat source element and other circuit elements.

  Step 104 is a step of calculating the area of the heat generating portion. In the circuit simulation in step 102, since the current flowing through each element and the voltage to be applied are determined, the area of the heat generating portion in the entire semiconductor chip is calculated from the data. Most of the heat generating portion is a heat source element (power transistor). Although step 104 is not an essential component in the present invention, the heat capacity can be obtained by calculating the area of the heat generating portion, and the accuracy of the heat simulation can be improved. The calculation result of the heat generating area is considered when arranging each circuit element on the semiconductor chip according to a floor plan described later. Step 104 may be performed before step 103 instead of after step 103.

  Step 105 is a step of performing a floor plan. In the floor plan, the temperature distribution in the semiconductor chip is estimated based on the area of the heating element calculated in step 104, and the heat source element, each circuit element, various logic circuits, and each block element are roughly arranged in the semiconductor chip. . In the floor plan, bonding pads are arranged around the outside of the semiconductor chip to take out heat source elements and each logic circuit to the outside.

  Step 106 is a step of inputting "lead frame information" to the thermal simulation software program. In this document, the information is described as “lead frame information” for convenience of description, but is not necessarily limited to information related to the lead frame. For example, in step 106, the material, diameter, length, and the like of the bond wire may be subjected to thermal simulation. In step 106, the thermal conductivity and the thermal resistance are calculated mainly based on the material, material, size, thickness and the like of the internal lead and the external lead of the lead frame in order to calculate the thermal conductivity and the thermal resistance of the lead frame. The thermal conductivity and the thermal resistance can be calculated in consideration of the technical ideas disclosed in Patent Documents 2 to 5, but from the viewpoint of the convenience of thermal analysis, for example, the commercially available Virtuoso AMS Designer of Cadence Design Systems, USA may be used. In step 106, the heat capacity of the lead frame can be calculated and the thermal resistance from the semiconductor chip to the lead frame can be calculated. The schematic diagram of the lead frame and various information related to the lead frame are shown in FIG. 2 described later.

  Step 107 is a step of inputting “package information”. The word “package information” is used for convenience similarly to the “lead frame information” described above. In the package information in step 107, the thermal conductivity and thermal resistance of the semiconductor chip itself, and the thermal conductivity, thermal resistance, heat capacity, and the like of the resin body sealing the lead frame are calculated. Further, the thermal conductivity, thermal resistance, and heat capacity after the above-described lead frame is sealed with the resin body are also calculated. Further, the thermal conductivity and the thermal resistance of the bonding wire are calculated based on the diameter and the length of the bonding wire connected between the bonding pad on the semiconductor chip and the internal lead. Further, when the die is fixed to some substrate instead of the lead frame, the thermal resistance of the substrate is calculated. When the substrate to which the die is fixed is attached to another substrate, the thermal conductivity and the thermal resistance of the other substrate are calculated in step 107. In step 107, the heat capacity of the package can be calculated, and the thermal resistance from the lead frame to the package is calculated. Note that a schematic diagram of the package processed in step 107 and package information relating to the package are shown in FIG. 3 described later.

  In the first embodiment, the lead frame information is handled in step 106 and the package information is handled in step 107. However, the order of these processing steps may be reversed. That is, package information may be handled in step 106, and lead frame information may be handled in step 107. Further, the lead frame information and the package information may be input to the thermal simulation software program in one step.

  In step 108, a thermal analysis (thermal simulation) of the entire semiconductor integrated circuit is performed based on the magnitude of the thermal resistance calculated based on the lead frame information in step 106 and the package information in step 107. Step 108 is a steady analysis, that is, a thermal simulation is performed in a state where the circuit operation is stable and the heat distribution in the semiconductor chip (die) is calm.

  Step 109 is a step of creating an isotherm in the semiconductor chip (semiconductor integrated circuit) based on the thermal simulation (steady-state analysis) performed in step 108. The isotherm is a so-called temperature distribution line obtained by connecting points of the same temperature on the semiconductor chip. It is practical to have a certain width for the same temperature. The number of isotherms to be created may be determined based on the absolute values of the maximum temperature and the minimum temperature on the semiconductor chip and the temperature difference between them. For example, when the maximum temperature on the semiconductor chip is 150 ° C. and the minimum temperature is 50 ° C., if the isotherms are created at intervals of 20 ° C., the number is six. Isotherms are created automatically or manually.

  In step 110, a timing element is arranged on the semiconductor chip along the isotherm created in step 109. Here, the timing element refers to a transistor, a diode, a resistor, or the like included in a logic circuit. For example, in a logic circuit, as a method of supplying a clock signal, a batch driving method, a clock tree method, a combination method of the both, and the like are known. As a timing element, a clock driver and a flip-flop circuit used for these are used. Can be mentioned. Of course, each transistor forming the flip-flop circuit also corresponds to a timing element. Note that the setup time, the hold time, and the delay time of the flip-flop circuit greatly affect the operation of the logic circuit, so that sufficient consideration must be given to temperature changes.

  FIG. 2 shows an example of the lead frame information considered in step 106 of FIG. 1. FIG. 2A is a schematic view of a lead frame to which a die (semiconductor chip) DIE is fixed. In this document, the lead frame includes a die pad (die flag), an internal lead IL, an external lead OL, and a tab lead TL. A die pad DP is provided at the center of the lead frame, and the die pad DP is supported by a tab lead TL. A die (semiconductor chip) DIE is fixed to the die pad DP. The internal lead IL is sealed in the resin sealing body EC together with the die pad DP and the tab lead TL, and the external lead OL extends outside the resin sealing body EC. The lead frame has a size such as a package length E, a lead pitch e, a lead width b, a tab lead width Wtb, and a lead frame flag gap g1. In the present invention, various kinds of information on such various lead frames are considered when calculating the thermal resistivity of the entire package.

  FIG. 2B shows the internal lead frame IL in FIG. 2A for displaying the die width Wd, die length Ld, die pad width Wf, die pad length Lf, sealing body width E1, and sealing body length D1. This shows a state where the external lead frame OL is not shown. In the present invention, such information is also taken into account when calculating the thermal resistivity and heat capacity of the entire package.

  FIG. 3 shows an example of a cross-sectional view of the package and its information considered in step 107 of FIG.

  FIG. 3A shows a state in which the die d is fixed on the die pad DP via the die attach (for example, solder) da inside the resin sealing body EC. In FIG. 3A, the thickness A2 of the sealing body, which is the thickness of the resin sealing body EC, and the thickness td of the die are considered in calculating the thermal conductivity and the thermal resistance. In addition, although the sealing body width E1 and the sealing body length D1 of the resin sealing body EC are considered in step 106, they may be used in step 107 for calculating the thermal conductivity and the thermal resistance together with the die thickness td.

  FIG. 3B is a cross-sectional view of an overall image of the semiconductor integrated circuit according to the present invention, and is also a diagram in which the internal leads IL, the external leads OL, and the bond wires bw are added to FIG. In FIG. 3B, the external lead thickness tl, the lead frame height h of the external lead OL, the lead foot length Lft, the die pad down set ddf which is the distance from the die pad DP to the internal lead IL, and the bottom of the resin sealing body EC The package standoff A1, which is the distance to the end of the external lead OL, and the bond wire bw are used for calculating the thermal conductivity and the thermal resistance.

FIG. 3C shows another semiconductor integrated circuit according to the present invention. FIG. 3C is different from FIG. 3B in that the die d is mounted on the metal mounting portion Hra via the die attach da, and the metal mounting portion Hra is mounted on the board B via the solder s. It has a structure to be attached to a land L which is an attachment portion. FIG. 3C shows that the volume of the resin sealing body EC is smaller than that of FIG. 3B and that the metal mounting portion Hra is provided, so that the heat generated by the die d is relatively small in the heat resistance. Since heat is rapidly radiated to the outside via the mounting portion Hra, the thermal resistance of the entire integrated circuit device becomes smaller than that of FIG. In FIG. 3C, the thermal resistance and the thermal resistance according to the material of the metal mounting portion Hra, the solder s, the land L, and the board B are calculated.

  FIG. 3D shows the bond wire length Lbw and the bond wire diameter dbw of the bond wires bw shown in FIGS. 3B and 3C. The thermal conductivity of the material of the bond wire bw increases in the order of aluminum (Al), gold (Au), and copper (Cu). Therefore, heat transfer is the slowest among three metals of aluminum (Al). Further, the thermal conductivity also changes with temperature. In general, the lower the temperature of a metal, the higher the thermal conductivity and the faster the thermal conductivity. In the present invention, a thermal simulation is performed in consideration of the thermal conductivity of such a bond wire. In addition, the number of the bond wires bw in addition to the material, the diameter, and the length are used for calculating the thermal simulation.

  The three-dimensional shape of the package can be created by inputting each piece of information considered in steps 106 and 107 into CAD (computer-aided design) software. By grasping the three-dimensional shape, the entire image of the semiconductor integrated circuit can be grasped, and it can be determined whether or not the input of the lead frame information and the package information to the thermal simulation software is appropriate. That is, one feature of the present invention is to perform an optimal thermal simulation while grasping a member to be subjected to the thermal simulation in a three-dimensional shape.

  FIG. 4 is a diagram for explaining the arrangement in step 110 of FIG. 1 and the temperature distribution on the semiconductor chip. FIG. 4A is an example when a timing element is arranged on an isotherm of a semiconductor chip, and FIG. 4B is a schematic diagram showing a temperature difference between a heat source element and a reference point.

  FIG. 4A shows a state in which a heat source element 2 is arranged at one corner of a semiconductor chip (die) 1 and a reference point 3 is provided near the heat source element 2. At the reference point 3, a monitor element for measuring the so-called temperature is placed. The first isotherm L <b> 1 is formed by connecting a point lower by a predetermined temperature, for example, 20 ° C., from the center of the heat source element 2. The second isotherm L2 is formed by connecting, for example, points 20 ° C. lower than the first isotherm L1. The third isotherm L3 is formed by connecting points, for example, 20 ° C. lower than the second isotherm L2. Therefore, the second isotherms L2 and L3 are formed by connecting points lower by 40 ° C. and 60 ° C. from the center of the heat source element 2, respectively.

  On the first isotherm L1, first timing elements 21, 22, 23 and 24 are arranged. Each of the first timing elements 21 to 24 is a single transistor or a combination of several transistors, for example, a flip-flop circuit.

  Second timing elements 31, 32, 33 and 34 are arranged on the second isotherm L2. Each of the second timing elements 31 to 34 may be a single transistor, like the first timing element, or may be a combination of several transistors, for example, a flip-flop circuit.

  Third timing elements 41, 42, 43 and 44 are arranged on the third isotherm L3. Each of the third timing elements 41 to 44 is a single transistor, like the first and second timing elements, or is a combination of several transistors, for example, a flip-flop circuit.

  When the circuit blocks of the logic circuit are highly integrated, the number of stages of the flip-flop circuit is also large, and the same circuit portion extends over the first isotherm L1, the second isotherm L2, and the third isotherm L3. May be required to arrange transistors and flip-flop circuits. In such a case, the arrangement may be determined in consideration of the setup time, the hold time, and the delay time required for the flip-flop circuit. That is, when the proportion of the timing elements becomes high and it is difficult to place all the timing elements near one isotherm, they may be arranged near a plurality of isotherms. For example, the timing elements 21 to 24 are arranged on the isotherm L1, the timing elements 31 to 34 are arranged on the thermal isotherm L2, and the timing elements 41 to 44 are arranged on the isotherm L3. After the operation of the timing elements 21 to 24 is completed, a sum of a signal transmission time, a deviation during signal transmission, for example, a setup time and a hold time of 10%, and a delay time caused by a temperature difference between the elements in a steady state is set as a margin time. And the timing elements 31 to 34 are operated. Similarly, between the timing elements 31 to 34 and the timing elements 41 to 44, a sum of a signal transmission time, a shift time during signal transmission, and a delay time caused by a temperature difference between elements in a steady state is provided. Thus, a margin between the timing elements can be secured by the heat generated by the heat source element 2.

  FIG. 4B shows a change with time of energy generated in the heat source element 2 shown in FIG. 4A and a heat gradient between the heat source element 2 and a reference point 3 provided near the heat source element 2. It is a figure which shows a horizontal axis and time t.

  When power is supplied to the heat source element 2 at time t0, the supplied power has a peak value instantaneously, so that the maximum energy is instantaneously generated in the heat source element 2. However, when the times t1 and t2, which are relatively short times, are reached, the magnitude becomes constant at a predetermined magnitude.

  Here, attention is paid to the temperature difference between the heat source element 2 and the reference point 3. In the section from time t0 to t1, the heat source element 2 gradually generates heat, so that the temperature of the heat source element 2 itself gradually increases. In addition, since the heat transfer from the heat source element 2 is not sufficiently transferred to the reference point 3, the temperature difference between the two gradually increases from time t0 to time t1. At time t1, the heat source element 2 reaches the maximum temperature, but the heat transfer of the heat source element 2 is not sufficient at the reference point 3, so that the temperature difference between the two becomes the maximum value Tmax, and the thermal gradient between the two becomes the maximum. . In order to obtain the maximum value of the thermal gradient, that is, the maximum value Tmax of the temperature difference, the section from time t0 to t2 is sampled with a pulse signal, and the peak value of the temperature is obtained. For this purpose, sampling is performed at a time step in the range of, for example, 1/3 to 1/20 of the RC time constant which is a product of the thermal resistance R obtained in steps 106 and 107 and the heat capacity C obtained from the lead frame information and the package information. Ask for it. Note that the sampling may be performed not once but, for example, in the first time, the temperature range may be roughly narrowed down by the time step 1/3, and then the range may be finely sampled by the time step 1/5, for example.

  From time t1 to time t2, the temperature of the heat source element 2 reaches the maximum temperature, and the heat energy generated in the heat source element 2 is transmitted to the reference point 3. In this section, as the thermal energy transmitted to the reference point 3 increases, the temperature difference between the two decreases, and at time t2, the temperature difference is sufficiently propagated, so that the temperature difference between the two becomes a steady value Tcons.

  Now, the following can be generally said about the heat distribution and the heat gradient without being limited to the present invention. For example, assuming that the heat is uniformly generated from the die d in FIGS. 2 and 3 described above, the balance of the heat energy per unit time is determined by the heat generation amount W1 being equal to the heat amount Q1 flowing through the die d and the surrounding convection. And the calorific value Q2 carried away, and can be expressed by Equation 1 below.

Further, the amount of heat Q1 generated in the die d per unit time can be expressed by the following equation 2 according to Fourier's law of heat conduction.

Here, T is temperature (K), t is time (s), KT is thermal conductivity (W / (m · K)), ρ is density (kg / m ³ ), CP is constant pressure specific heat (J / ( kg · K)), ∇ is a Laplace operator, and V is a volume (m ³ ). Further, the amount of heat Q2 taken away by surrounding convection within a unit time satisfies Newton's law of cooling, and can be expressed by the following equation (3).

Here, A is the area (m ² ), h is the heat transfer coefficient (W / m ² · k), and Tm is the ambient temperature (K). By applying the lead frame information and package information according to the present invention to the above equation (1), it is possible to grasp the temperature change of the heat source element alone, the entire semiconductor integrated circuit, and each part.

  In the present invention, the elements arranged on the isotherm are not limited to the timing elements. For example, a differential amplifier or a current mirror circuit that requires the same temperature characteristics may be used.

(2nd Embodiment)
FIG. 5 is a flowchart illustrating a circuit simulation method for a semiconductor integrated circuit according to the second embodiment of the present invention. The second embodiment assumes a case where heat generation or heat transfer of the heat source element is intermittent, or a case where there are a plurality of heat source elements that generate relatively large heat, that is, a case where a steady state does not exist. I have. In such a case, the timing design and the arrangement of the timing elements are made based on the maximum value of the time lag between the plurality of timing elements in the semiconductor integrated circuit due to a change in the thermal gradient in the semiconductor integrated circuit due to the heat generated by the heat source element. In consideration of this, a semiconductor integrated circuit is designed and manufactured.

  FIG. 5 includes steps 201 to 211. Of these steps, each of steps 201 to 207 corresponds to each of steps 101 to 107 of the first embodiment.

  Step 201 is a step of creating a circuit diagram in consideration of circuit operation when designing a circuit. The target circuit includes a heat source element, various logic circuits, and a timing element depending on the application. Circuit functions including such a heat source element include, for example, an LED driver, a motor driver, an IPD (system power supply), and the like.

  Step 202 is a step of performing circuit simulation of static characteristics and dynamic characteristics along the circuit diagram created in step 201. In the circuit simulation, DC characteristics, time response characteristics, frequency response characteristics, and the like of each node voltage in the circuit, current flowing in each element, and the like are calculated in accordance with circuit connection information at a transistor level and electrical characteristics of elements in the circuit. For the circuit simulation and the thermal analysis circuit simulation, for example, SPICE (Simulation Program with Integrated Circuit Emphasis) or Virtuoso AMS Designer of Cadence Design Systems, USA can be used.

  Step 203 is a step of calculating the amount of heat generated by the circuit simulation in step 202. That is, the calculation is performed including the heat source element and other circuit elements based on the current flowing through the circuit element and the applied voltage during the circuit operation.

  Step 204 is a step of calculating the area of the heating element. In the circuit simulation in step 202, the current flowing through each circuit element and the voltage to be applied are obtained, and the area of the heating portion in the entire semiconductor chip is calculated from the data. In the heat generating portion, not only the heat source element but also a relatively large heat generating element is targeted. Determining the area of the heat generating portion is not an essential component in the present invention, but is considered when arranging each circuit element when performing a floor plan described later.

  Step 205 is a step of performing a floor plan. In the floor plan, the temperature distribution in the semiconductor chip is estimated based on the area of the heating element calculated in step 204, and the heat source element, each circuit element, various logic circuits, and each block element are roughly arranged in the semiconductor chip. . In the floor plan, bonding pads are arranged around the outside of the semiconductor chip to take out heat source elements and each logic circuit to the outside.

  Step 206 is a step of inputting "lead frame information" to the thermal simulation software program. In this document, the information is described as “lead frame information” for convenience of description, but is not necessarily limited to information related to the lead frame. For example, in step 206, the material, diameter, length, and the like of the bond wire may be subjected to thermal simulation. In step 206, the thermal conductivity and the thermal resistance are calculated mainly based on the material, material, size, thickness and the like of the internal lead and the external lead of the lead frame in order to calculate the thermal conductivity and the thermal resistance of the lead frame. The thermal conductivity and the thermal resistance can be calculated in consideration of the technical ideas disclosed in Patent Documents 2 to 5, but from the viewpoint of the convenience of thermal analysis, for example, the commercially available Virtuoso AMS Designer of Cadence Design Systems, USA may be used. The schematic diagram of the lead frame and various information related to the lead frame are shown in FIG. 2 described above.

  Step 207 is a step of inputting “package information”. The word “package information” is used for convenience similarly to the “lead frame information” described above. In the package information in step 107, the thermal conductivity and thermal resistance of the semiconductor chip itself, and the thermal conductivity and thermal resistance of the resin body sealing the lead frame are calculated. Further, the thermal conductivity, the thermal resistance, and the thermal resistance after the above-described lead frame is sealed with the resin body are also calculated. Further, the thermal conductivity and the thermal resistance of the bonding wire are calculated based on the diameter and the length of the bonding wire connected between the bonding pad on the semiconductor chip and the internal lead. Further, when the die is fixed to some substrate instead of the lead frame, the thermal resistance of the substrate is calculated. When the substrate to which the die is fixed is attached to another substrate, the thermal conductivity and the thermal resistance of the other substrate are calculated in step 207. The schematic diagram of the package processed in step 207 and the package information related thereto are shown in FIG. 3 described above.

  Although the lead frame information is handled in step 206 and the package information is handled in step 207 in the second embodiment, the order of these processing steps may be reversed. That is, package information may be handled in step 206, and lead frame information may be handled in step 207. Further, the lead frame information and the package information may be input to the thermal simulation software program in one step.

  Step 208 is a step of performing a thermal simulation. In step 108 of the first embodiment, a heat simulation was performed between the heat source element and the monitor point on the semiconductor chip after the heat transfer of the heat source element was stabilized, that is, in a steady state, but in step 208 of the second embodiment. Performs a heat simulation in a state where heat generation and heat transfer of the heat source element are changing, that is, in a transient state.

  Step 209 is a step of extracting the maximum thermal gradient in the semiconductor chip. In other words, the maximum temperature difference between the predetermined position in the semiconductor chip and the reference point is subjected to thermal simulation by the same method as that used in the first embodiment, and the maximum thermal gradient of the entire semiconductor chip is calculated. .

  Step 210 is a step of calculating the worst timing between the arranged timing element and another timing element based on the maximum thermal gradient calculated in step 209. In order to calculate the worst timing, the maximum value Tmax of the temperature difference shown in FIG. First, an RC time constant, which is a product of the thermal resistance R and the thermal capacity C, is obtained from the lead frame information and the package information. Next, the temperature difference between times to and t2 is determined in a time step sufficiently smaller than the RC time constant. The time step can be selected, for example, from 1/3 to 1/20 of the time constant RC. As a result, the maximum value Tmax at the worst timing can be accurately grasped.

  In step 211, the worst timing circuit simulation of the semiconductor integrated circuit is performed in consideration of the worst timing calculated in step 210. The worst timing occurs when the margin provided between the timing elements reaches a limit value (minimum value of the margin). Therefore, since the timing element is arranged on the semiconductor chip in consideration of the worst timing, it is possible to prevent a malfunction of the circuit caused by insufficient margin of the setup time, the hold time, and the delay time of the timing element, for example.

  When there are a plurality of heat source elements, for example, when the heat source element 2 is composed of the heat source elements 2a and 2b, the heat in the integrated circuit is considered in consideration of the on / off timing of the heat source elements 2a and 2b. Simulate the temperature distribution characteristics of the gradient. That is, for example, when the operation pattern a and the operation pattern b are present, the reference points are set based on the respective energies of the heat source element 2a and the heat source element 2b at the time of each operation pattern, along with the time transition of the heat source elements 2a and 2b. Calculate the temperature difference from the (monitor point).

  When calculating the maximum temperature difference Tmax, that is, the thermal gradient difference, the material conditions in step 206 and step 207 may be set to the best conditions. That is, the external conditions of the package, the internal die bonding, and the wire bonding are set to ideal conditions, for example, the magnitude of the thermal resistance is set, for example, in a range of 0 to 0.5 times that of the actual one. Thermal resistance of aluminum (Al), copper (Cu), gold (Au), or a mixed material thereof with, for example, silicon, or a refractory metal material, which is a wiring material used for the internal wiring of the chip) Is selected in the range of 10 times to 1 time of the actual body, and a thermal simulation is performed. With such a setting, the maximum temperature difference Tmax can be accurately grasped, so that a sufficient margin between the setup time, the hold time, and the delay time of the timing element can be secured.

  FIG. 6 is a diagram for explaining step 208 of the second embodiment shown in FIG. 5, for example, in a case where the heat source element 2 of FIG. 2 generates heat intermittently. For example, when the heat source element 2 is a high-side transistor of a DC / DC converter (not shown), the high-side transistor is generally controlled to be on / off by a drive signal of pulse width modulation (PWM, Plus Width Modulation). You.

  FIG. 6A is a waveform showing a change in thermal energy of the heat source element 2. For example, when the heat source element 2 is an n-type MOS transistor, the drive signal for controlling the heat source element 2 has substantially the same waveform. At times t11 to t12, t13 to t14, t15 to t16, and times t17 to t18, the drive signal is at the high level H, the heat source element 2 is turned on, and energy is consumed. From time t12 to t13, t14 to t15, t15 to t16, and after time t18, the drive signal is at the low level L, the heat source element 2 is turned off, and the operation is stopped.

  FIG. 6B is a diagram showing a change in the temperature difference between the reference point 3 and the heat source element 2 when the heat energy of the heat source element 2 changes as shown in FIG. The temperature difference between the reference point 3 and the heat source element 2 increases at times t11 to t12, t13 to t14, t15 to t16, and times t17 to t18, and after time t12 to t13, t14 to t15, t15 to t16, and after time t18. Descend. The method of calculating the temperature difference in such a case is the same as the method of calculating the temperature difference obtained in the first embodiment. Further, in the second embodiment, at times t12, t14, and t16, the temperature difference becomes the maximum ΔTmax. The time at which the maximum temperature difference ΔTmax occurs also exists at times other than the times t12, t14, and t16.

(Third embodiment)
FIG. 7 is a flowchart illustrating a circuit simulation method for a semiconductor integrated circuit according to the third embodiment. The third embodiment is applied, for example, when applied to a circuit simulation of a semiconductor integrated circuit designed and manufactured in the first embodiment or the second embodiment of the present invention. That is, the third embodiment is used for verifying whether the arrangement of the timing elements in a semiconductor integrated circuit already manufactured and completed is appropriate. The third embodiment includes steps 301 to 310, but each of steps 301 to 304 is the same as each of steps 201 to 204 in the second embodiment.

  Step 301 is a step of creating a circuit diagram in consideration of circuit operation when designing a circuit. The target circuit includes a heat source element, various logic circuits, and a timing element depending on the application. Circuit functions including such a heat source element include, for example, an LED driver, a motor driver, an IPD (system power supply), and the like.

  Step 302 is a step of performing circuit simulation of static characteristics and dynamic characteristics according to the circuit diagram created in step 301. In the circuit simulation, DC characteristics, time response characteristics, frequency response characteristics, and the like of each node voltage in the circuit, current flowing in each element, and the like are calculated in accordance with circuit connection information at a transistor level and electrical characteristics of elements in the circuit. For the circuit simulation and the thermal analysis circuit simulation, for example, SPICE (Simulation Program with Integrated Circuit Emphasis) or Virtuoso AMS Designer of Cadence Design Systems, USA can be used.

  Step 303 is a step of calculating the amount of heat generated by the circuit simulation in step 302. That is, the calculation is performed including the heat source element and other circuit elements based on the current flowing through the circuit element and the applied voltage during the circuit operation.

  Step 304 is a step of calculating the area of the heating element. In the circuit simulation in step 302, the current flowing through each circuit element and the voltage to be applied are obtained, and the area of the heat generating portion in the entire semiconductor chip is calculated from the data. In the heat generating portion, not only the heat source element but also a relatively large heat generating element is targeted. Determining the area of the heat generating portion is not an essential component in the present invention, but is considered when arranging each circuit element when performing a floor plan described later.

  Steps 305 to 307 are the same as steps 206 to 208 of the second embodiment. In the third embodiment, steps 105 in the first embodiment and step 205 in the second embodiment become unnecessary because the elements in the semiconductor integrated circuit are already arranged.

  Step 306 is a step of inputting “lead frame information” into the thermal simulation software program. In this document, the information is described as “lead frame information” for convenience of description, but is not necessarily limited to information related to the lead frame. For example, in step 306, the material, diameter, length, and the like of the bond wire may be subjected to thermal simulation. In step 306, the thermal conductivity and the thermal resistance are calculated mainly based on the material, material, size, thickness, etc. of the internal lead and the external lead of the lead frame in order to calculate the thermal conductivity and the thermal resistance of the lead frame. The thermal conductivity and the thermal resistance can be calculated in consideration of the technical ideas disclosed in Patent Documents 2 to 5, but from the viewpoint of the convenience of thermal analysis, for example, the commercially available Virtuoso AMS Designer of Cadence Design Systems, USA may be used. The schematic diagram of the lead frame and various information related to the lead frame are shown in FIG. 2 described above.

  Step 307 is a step of inputting “package information”. The word “package information” is used for convenience similarly to the “lead frame information” described above. In the package information in step 307, the thermal conductivity and thermal resistance of the semiconductor chip itself, and the thermal conductivity and thermal resistance of the resin body sealing the lead frame are calculated. Further, the thermal conductivity and the thermal resistance after the above-described lead frame is sealed in the resin body are also calculated. Further, the thermal conductivity and the thermal resistance of the bonding wire are calculated based on the diameter and the length of the bonding wire connected between the bonding pad on the semiconductor chip and the internal lead. Further, when the die is fixed to some substrate instead of the lead frame, the thermal resistance of the substrate is calculated. If the substrate to which the die is fixed is attached to another substrate, the thermal conductivity and thermal resistance of the other substrate are calculated in step 307. The schematic diagram of the package processed in step 307 and the package information related thereto are shown in FIG. 3 described above.

  In the third embodiment, the lead frame information is handled in step 306, and the package information is handled in step 307. However, the order of these processing steps may be reversed. That is, the package information may be handled in step 306, and the lead frame information may be handled in step 307. Further, the lead frame information and the package information may be input to the thermal simulation program in one step.

  Step 308 is a step of performing a thermal simulation. In step 108 of the first embodiment, a heat simulation is performed between the heat source element 2 and the reference point 3 (monitor point) on the semiconductor chip after the heat transfer of the heat source element is stabilized, that is, in a steady state. In step 308 of the third embodiment, a heat simulation is performed in a state in which heat generation and heat transfer of the heat source element 2 are changing, that is, in a transient state.

  Step 308 is a step of extracting the position maximum thermal gradient from the thermal gradient for each pattern calculated at step 307 at each time. Comparing step 308 with step 209 in the second embodiment, the method of execution is the same, but the accuracy of the obtained thermal gradient is different. The arrangement of the circuit elements in the second embodiment is a rough floor plan, and the simulation is performed with a rough arrangement. On the other hand, in the third embodiment, the circuit simulation is performed after the arrangement of the circuit elements, especially the timing elements, is completed. Therefore, the setup time, the hold time, and the like can be accurately grasped, so that these margin settings can be used at the time of designing and manufacturing the next semiconductor integrated circuit.

  Step 309 is a step of feeding back information on the set-up time, hold time, and delay time based on the maximum thermal gradient obtained in step 308 to each circuit element, especially the timing element. For example, when there is a temperature difference between timing elements having signal transmission, a time delay due to the temperature difference is converted into a time constant R1C1 and fed back. Such feedback allows more accurate circuit simulation.

  Step 310 is a step of performing a final circuit simulation after replacing the delay time obtained in step 309 with the time constant R1C1. This circuit simulation may be performed statically or dynamically. According to such a circuit simulation and a thermal simulation, the delay time of the data signal and the clock signal input to the timing element can be accurately grasped.

  FIG. 8 is a conceptual diagram showing a time constant applied in steps 308 and 309 in the third embodiment. In FIG. 8A, since the D flip-flop FF1 and the D flip-flop FF2 are both set at a temperature of 25 ° C., there is no temperature difference between them. In this case, the time constant interposed between the two is zero. FIG. 8B shows a state where the D flip-flop FF1a is placed at a temperature of 25 ° C. and the D flip-flop FF1b is placed at a temperature of 80 ° C. In such a case, a temperature difference of 55 ° C. occurs between them. Since such a temperature difference causes a delay time between the two, the delay time is indicated by the time constant R1C1 of the resistor R1 and the capacitor C1. In the third embodiment, such heat information is fed back to the timing element, and the circuit simulation is performed again in a state where the feedback is made. By such a circuit simulation, it is possible to perform a thermal analysis in accordance with the substance. Each D flip-flop has an input terminal CP1, a D input terminal D1, and Q output terminals Q1 and Q2.

  As described above, the method for arranging a semiconductor integrated circuit and the method for simulating a circuit according to the present invention accurately set up the setup time, hold time, and delay time of a timing element including a heat source element based on lead frame information and package information. Since it can be grasped, it is possible to provide a semiconductor integrated circuit whose circuit operation is stable with respect to a temperature change, so that its industrial applicability is extremely high.

1 semiconductor chip (semiconductor integrated circuit)
2 Heat source element 3 Reference point (monitor point)
21 to 24, 31 to 34, 41 to 44 Timing element A1 Package standoff A2 Sealing body thickness b Lead width B Board bw Bond wire d Die (semiconductor chip)
D1 Sealed body length da Die attach dbw Bond wire diameter ddf Die pad down set DP Die pad (Die flag)
e Lead pitch E Package length E1 Sealed body width EC resin sealed body gl Flag gap h Lead frame height Hra Metal mounting part L Land L1, L2, L3 Isothermal line Lbw Bond wire length Ld Die length Lf Die pad length Lft Lead Foot length OL External lead s Solder td Die thickness TL Tab lead tl Lead width Wd Die width Wf Die pad width Wtb Tab lead width

Claims (6)

Creating a circuit diagram of a semiconductor integrated circuit including the heat source element;
Performing a circuit operation simulation of the semiconductor integrated circuit based on the circuit diagram;
Calculating a heat value of the semiconductor integrated circuit based on the circuit operation simulation;
Performing a floor plan on a semiconductor chip of the semiconductor integrated circuit with reference to the calculated heat value;
Calculating a thermal resistance based on lead frame information of a lead frame on which the semiconductor chip is mounted and package information of a package in which the semiconductor chip is sealed;
Performing a thermal simulation of the entire semiconductor integrated circuit sealed in the package based on the calculated thermal resistance ;
Creating an isotherm of the semiconductor chip based on the result of the thermal simulation;
Placing a timing device included in at least the semiconductor integrated circuit on the semiconductor chip along the isotherm,
A method for arranging a semiconductor integrated circuit, comprising:   2. The method according to claim 1, wherein an area of a heat generating portion of the heat source element is calculated before or after the step of calculating a heat generation amount of the semiconductor integrated circuit. And wherein before calculating the thermal resistance on the basis of the lead frame information and the package information, whether the three-dimensional shape of the entire encapsulated the semiconductor integrated circuit in the package it is appropriate to check in CAD 3. The method for arranging semiconductor integrated circuits according to claim 1 or claim 2. Arrangement method of a semiconductor integrated circuit according to any one of claims 1-3 wherein the thermal simulation, wherein the heat source element is calculated based on the heating characteristics of the steady state operation. Arrangement method of a semiconductor integrated circuit according to any one of claims 1-4, characterized in that the timing element is a flip-flop circuit. The semiconductor integrated circuit, LED drivers, power supply circuit, the intelligent power device, and the semiconductor integrated according to any one of claims 1 to 5, characterized in that it comprises at least one circuit function of the central processing unit Circuit placement method .