CN111682062A - 一种igbt器件的背面结构及其制备方法、igbt器件 - Google Patents

一种igbt器件的背面结构及其制备方法、igbt器件 Download PDF

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CN111682062A
CN111682062A CN202010594130.8A CN202010594130A CN111682062A CN 111682062 A CN111682062 A CN 111682062A CN 202010594130 A CN202010594130 A CN 202010594130A CN 111682062 A CN111682062 A CN 111682062A
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igbt device
region
buffer
activation efficiency
buffer layer
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李立
金锐
王耀华
董少华
刘江
高明超
吴军民
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State Grid Corp of China SGCC
Electric Power Research Institute of State Grid Shanxi Electric Power Co Ltd
Global Energy Interconnection Research Institute
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State Grid Corp of China SGCC
Electric Power Research Institute of State Grid Shanxi Electric Power Co Ltd
Global Energy Interconnection Research Institute
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Publication of CN111682062A publication Critical patent/CN111682062A/zh
Priority to US17/759,411 priority patent/US20230077959A1/en
Priority to PCT/CN2021/100045 priority patent/WO2021259088A1/zh
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Abstract

本发明提供一种IGBT器件的背面结构及其制备方法、IGBT器件,通过将缓冲层中与IGBT器件的有源区对应的区域设置为第一激活效率缓冲区,与IGBT器件的终端区对应的区域设置为第二激活效率缓冲区,且第二激活效率缓冲区的激活率大于第一激活效率缓冲区的激活效率,从而降低了终端区的空穴注入效率;IGBT器件芯片过流关断时,终端区注入的空穴在IGBT关断时都要通过主结进行收集,从而降低了有源区边缘主结处的电流集中现象,提高了器件的过流关断性能。

Description

一种IGBT器件的背面结构及其制备方法、IGBT器件
技术领域
本发明涉及半导体器件技术领域,具体涉及一种IGBT器件的背面结构及其制备方法、IGBT器件。
背景技术
IGBT(Insulated Gate Bipolar Transistor)又称作绝缘栅双极型晶体管,是目前最具代表性的电力电子器件。IGBT是由BJT(双极结型晶体三极管)和MOS(绝缘栅型场效应管)组成的复合全控型-电压驱动式-功率半导体器件,具有自关断的特征,因此同时具有BJT器件与MOS器件的优点,如电压控制开关、工作频率高、驱动控制电路简单和双极导电等。自IGBT技术诞生以来,经过30多年的发展,IGBT技术经历了四代变更,依次为第一代平面栅穿通型、第二代平面栅非穿通型、第三代沟槽栅场截止型和第四代载流子存储沟槽栅双极晶体管。
IGBT器件具有自关断的特征,其导通时可以看做导线,断开时当做开路。在电力系统实际应用中,IGBT器件需要保证在比较恶劣的情况下安全关断,同时能够承受长时间的故障电流,这对IGBT器件的关断能力提出了更高的要求。因此,对于在电力系统领域应用的IGBT器件,在满足基本静动态特性、可靠性的同时,还需要具备较强的过流关断能力。
传统IGBT器件包括漂移区、设置在漂移区上方的终端区及分设在终端区的两端的两有源区,还包括设置于漂移区远离所述有源区一侧的缓冲层、背面P+区和集电极金属层,缓冲层、背面P+区和集电极金属层构成IGBT器件的背面结构,所述缓冲层可通过热退火或激光退火的方式进行激活,其中通过热退火得到的缓冲层的激活率在100%左右,通过激光退火得到的缓冲层的激活率在85%以上。该器件在关断时,其终端区由背面P+区注入的空穴都要通过有源区边缘处的主结进行收集,空穴电流会在主结处出现电流集中的现象,很容易导致关断失效。
发明内容
因此,本发明要解决的技术问题在于克服现有IGBT器件在关断时,在有源区边缘主结处出现电流集中,易导致关断失效的缺陷,从而提供一种IGBT器件的背面结构及其制备方法、IGBT器件。
为此,本发明提供一种IGBT器件的背面结构,包括缓冲层,所述缓冲层包括与所述IGBT器件的有源区对应的第一激活效率缓冲区及与所述IGBT器件的终端区对应的第二激活效率缓冲区,其中,所述第一激活效率缓冲区的激活率小于所述第二激活效率缓冲区的激活效率。
进一步地,所述第一激活效率缓冲区的激活率为15-25%,所述第二激活效率缓冲区的激活率为85-95%。
进一步地,所述缓冲层的掺杂元素为磷,结深为2-3μm。
进一步地,所述缓冲层远离所述IGBT器件的漂移区的一侧还设置有背面P+区及集电极金属层,且所述缓冲层、背面P+区和集电极金属层层叠设置。
进一步地,所述背面P+区的掺杂元素为硼,厚度为0.4-0.6μm。
本发明还提供一种IGBT器件,其采用上述的IGBT器件的背面结构。
本发明还提供一种IGBT器件的背面结构的制备方法,包括以下步骤:
(1)在完成IGBT器件的正面结构的制备后,对圆晶的背面进行第一离子注入,形成缓冲层;
(2)对所述缓冲层进行第一激光退火,所述缓冲层中与所述IGBT器件的有源区对应的区域形成第一激活效率缓冲区,所述缓冲层中与所述IGBT器件的终端区对应的区域形成第二激活效率缓冲区。
进一步地,所述第一激活效率缓冲区的形成条件为:激光波长为510-550nm,激光能量为1.5-2.5J/cm2
所述第二激活效率缓冲区的形成条件为:激光波长为510-550nm,激光能量为5-6J/cm2
进一步地,所述IGBT器件的背面结构的制备方法还包括以下步骤:
(3)对圆晶的背面进行第二离子注入,以在所述缓冲层远离所述IGBT器件的漂移区的一侧形成背面P+层,并对所述背面P+层进行第二激光退火;
(4)在所述背面P+层远离所述缓冲层的一侧形成背面金属电极。
进一步地,所述第一离子注入的剂量为5E13cm-2-1E14cm-2,注入元素为磷;
所述第二离子注入的剂量为1E14cm-2-5E14cm-2,注入元素为硼。
本发明技术方案,具有如下优点:
1.本发明提供的IGBT器件的背面结构及IGBT器件,其缓冲层包括与所述IGBT器件的有源区对应的第一激活效率缓冲区及与所述IGBT器件的终端区对应的第二激活效率缓冲区,其中,所述第一激活效率缓冲区的激活率小于所述第二激活效率缓冲区的激活效率;
有效掺杂浓度(NDSPT)与IGBT器件的寄生晶体管PNP的电流增益(βPNP)成反比,终端区的空穴注入效率随着电流增益(βPNP)的增大而增大,即随着有效掺杂浓度(NDSPT)的增加,空穴注入效率逐渐减低。通过将所述缓冲层中与IGBT器件的有源区对应的区域设置为第一激活效率缓冲区,与IGBT器件的终端区对应的区域设置为第二激活效率缓冲区,且所述第二激活效率缓冲区的激活率大于所述第一激活效率缓冲区的激活效率,增加了终端区的有效掺杂浓度(NDSPT),降低了终端区的空穴注入效率;IGBT器件芯片过流关断时,终端区注入的空穴在IGBT关断时都要通过主结进行收集,从而降低了有源区边缘主结处的电流集中现象,提高了器件的过流关断性能。
2.本发明提供的IGBT器件,具有更高的击穿电压及更小的漏电流更小,击穿特性更加优异。
3.本发明提供的IGBT器件的背面结构的制备方法,其缓冲层仅需要在第一离子注入后进行第一激光退火即可制得,与传统IGBT制造工艺兼容,同时,不需要额外的光刻工艺步骤,制备工艺简单。
附图说明
为了更清楚地说明本发明具体实施方式或现有技术中的技术方案,下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施方式,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本发明实施例1中提供的IGBT器件的结构示意图;
图2是本发明对比例1中提供的IGBT器件的结构示意图;
图3是本发明实施例中提供的IGBT器件与对比例1提供的IGBT器件的击穿电压对比关系曲线;
附图标记:
1-漂移区;2-有源区;3-终端区;4-缓冲层;41-第一激活效率缓冲区;42-第二激活效率缓冲区;5-背面P+区;6-集电极金属层。
具体实施方式
提供下述实施例是为了更好地进一步理解本发明,并不局限于所述最佳实施方式,不对本发明的内容和保护范围构成限制,任何人在本发明的启示下或是将本发明与其他现有技术的特征进行组合而得出的任何与本发明相同或相近似的产品,均落在本发明的保护范围之内。
在本发明的描述中,需要说明的是,术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。此外,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性。
实施例1
如图1所示,本实施例提供一种IGBT器件的背面结构,包括缓冲层4,缓冲层4包括与IGBT器件的有源区2对应的第一激活效率缓冲区41及与IGBT器件的终端区3对应的第二激活效率缓冲区42,其中,第一激活效率缓冲区41的激活率小于第二激活效率缓冲区42的激活效率。
由于有效掺杂浓度(NDSPT)与IGBT器件的寄生晶体管PNP的电流增益(βPNP)成反比,IGBT器件的终端区3的空穴注入效率随着电流增益(βPNP)的增大而增大,即随着有效掺杂浓度(NDSPT)的增加,空穴注入效率逐渐减低。通过将缓冲层4中与有源区2对应的区域设置为第一激活效率缓冲区41,与终端区3对应的区域设置为第二激活效率缓冲区42,且第二激活效率缓冲区42的激活率大于第一激活效率缓冲区41的激活效率,增加了终端区3的有效掺杂浓度(NDSPT),降低了终端区3的空穴注入效率;IGBT器件芯片过流关断时,终端区3注入的空穴在IGBT关断时都要通过主结进行收集,从而降低了有源区2边缘主结处的电流集中现象,提高了器件的过流关断性能。同时也使IGBT器件具有更高的击穿电压及更小的漏电流更小,击穿特性更加优异。
具体的,缓冲层4的掺杂元素为磷,结深为2-3μm,其中,第一激活效率缓冲区41的激活率为15-25%,第二激活效率缓冲区42的激活率为85-95%。
进一步地,缓冲层4远离IGBT器件的漂移区1的一侧还设置有背面P+区5及集电极金属层6,且缓冲层4、背面P+区5和集电极金属层6层叠设置。具体的,背面P+区5的掺杂元素为硼,厚度为0.4-0.6μm。
本实施例还提供一种IGBT器件,其采用上述的IGBT器件的背面结构。IGBT器件的正面结构包括有源区2及设置于有源区外侧的终端区3,终端区3与有源区2平齐。该IGBT器件具有上述背面结构的全部优点,在此不再赘述。
实施例2
本实施例提供一种IGBT器件的背面结构的制备方法,可得到实施例1提供的IGBT器件,具体包括以下步骤:
(1)在完成IGBT器件的正面结构的制备后,对圆晶的背面进行第一离子注入,形成缓冲层;
(2)对缓冲层进行第一激光退火,其中,缓冲层中与IGBT器件的有源区对应的区域形成第一激活效率缓冲区,缓冲层中与IGBT器件的终端区对应的区域形成第二激活效率缓冲区。具体的,第一离子注入的剂量为5E13cm-2-1E14cm-2,注入元素为磷;第一激活效率缓冲区的形成条件为激光波长为510-550nm,激光能量为1.5-2.5J/cm2;第二激活效率缓冲区的形成条件为:激光波长为510-550nm,激光能量为5-6J/cm2
(3)对圆晶的背面进行第二离子注入,以在缓冲层远离IGBT器件的漂移区的一侧形成背面P+层,并对背面P+层进行第二激光退火;具体的,第二离子注入的剂量为1E14cm-2-5E14cm-2,注入元素为硼。
(4)在背面P+层远离缓冲层的一侧形成背面金属电极。
对比例1
如图2所示,本对比例提供一种IGBT器件,其与实施例1的唯一不同之处在于,其背面结构中缓冲层的激活率为90%。
试验例
通过对IGBT的集电极-发射极进行击穿电压测试(测试条件Vge=0V,集电极-发射极间逐渐加电压,从0V至击穿点)可得到实施例与对比例公开的IGBT器件的击穿电压对比关系曲线。如图3所示,其横轴VCE表示IGBT器件芯片集电极-发射极电压,纵轴ICES表示IGBT器件芯片的集电极-发射极漏电流。
由图3可知,实施例提供的IGBT器件的击穿电压更第一,漏电流更小,具有更优的击穿特性。
显然,上述实施例仅仅是为清楚地说明所作的举例,而并非对实施方式的限定。对于所属领域的普通技术人员来说,在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本发明创造的保护范围之中。

Claims (10)

1.一种IGBT器件的背面结构,包括缓冲层,其特征在于,所述缓冲层包括与所述IGBT器件的有源区对应的第一激活效率缓冲区及与所述IGBT器件的终端区对应的第二激活效率缓冲区,其中,所述第一激活效率缓冲区的激活率小于所述第二激活效率缓冲区的激活效率。
2.根据权利要求1所述的IGBT器件的背面结构,其特征在于,所述第一激活效率缓冲区的激活率为15-25%,所述第二激活效率缓冲区的激活率为85-95%。
3.根据权利要求1或2所述的IGBT器件的背面结构,其特征在于,所述缓冲层的掺杂元素为磷,结深为2-3μm。
4.根据权利要求3所述的IGBT器件的背面结构,其特征在于,所述缓冲层远离所述IGBT器件的漂移区的一侧还设置有背面P+区及集电极金属层,且所述缓冲层、背面P+区和集电极金属层层叠设置。
5.根据权利要求4所述的IGBT器件的背面结构,其特征在于,
所述背面P+区的掺杂元素为硼,厚度为0.4-0.6μm。
6.一种IGBT器件,其特征在于,包括权利要求1-5任一项所述的IGBT器件的背面结构。
7.一种IGBT器件的背面结构的制备方法,其特征在于,包括以下步骤:
(1)在完成IGBT器件的正面结构的制备后,对圆晶的背面进行第一离子注入,形成缓冲层;
(2)对所述缓冲层进行第一激光退火,所述缓冲层中与所述IGBT器件的有源区对应的区域形成第一激活效率缓冲区,所述缓冲层中与所述IGBT器件的终端区对应的区域形成第二激活效率缓冲区。
8.根据权利要求7所述的IGBT器件的背面结构的制备方法,其特征在于,
所述第一激活效率缓冲区的形成条件为:激光波长为510-550nm,激光能量为1.5-2.5J/cm2
所述第二激活效率缓冲区的形成条件为:激光波长为510-550nm,激光能量为5-6J/cm2
9.根据权利要求7所述的IGBT器件的背面结构的制备方法,其特征在于,还包括以下步骤:
(3)对圆晶的背面进行第二离子注入,以在所述缓冲层远离所述IGBT器件的漂移区的一侧形成背面P+层,并对所述背面P+层进行第二激光退火;
(4)在所述背面P+层远离所述缓冲层的一侧形成背面金属电极。
10.根据权利要求9所述的IGBT器件的背面结构的制备方法,其特征在于,
所述第一离子注入的剂量为5E13cm-2-1E14cm-2,注入元素为磷;
所述第二离子注入的剂量为1E14cm-2-5E14cm-2,注入元素为硼。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021259088A1 (zh) * 2020-06-24 2021-12-30 全球能源互联网研究院有限公司 Igbt器件的背面结构及其制备方法、igbt器件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101345255A (zh) * 2007-07-10 2009-01-14 三菱电机株式会社 功率用半导体装置及其制造方法
US20140197451A1 (en) * 2011-07-05 2014-07-17 Mitsubishi Electric Corporation Semiconductor device
CN104143568A (zh) * 2014-08-15 2014-11-12 无锡新洁能股份有限公司 具有终端结构的场截止型igbt器件及其制造方法
CN109671771A (zh) * 2018-11-19 2019-04-23 全球能源互联网研究院有限公司 Igbt芯片的背面结构、igbt芯片结构及制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5036327B2 (ja) * 2007-01-23 2012-09-26 三菱電機株式会社 半導体装置及びその製造方法
CN103065962B (zh) * 2011-10-18 2015-08-19 上海华虹宏力半导体制造有限公司 绝缘栅双极晶体管的制造方法
CN106684118A (zh) * 2016-02-25 2017-05-17 宗仁科技(平潭)有限公司 开关型功率半导体器件及其制作方法
CN111682062A (zh) * 2020-06-24 2020-09-18 全球能源互联网研究院有限公司 一种igbt器件的背面结构及其制备方法、igbt器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101345255A (zh) * 2007-07-10 2009-01-14 三菱电机株式会社 功率用半导体装置及其制造方法
US20140197451A1 (en) * 2011-07-05 2014-07-17 Mitsubishi Electric Corporation Semiconductor device
CN104143568A (zh) * 2014-08-15 2014-11-12 无锡新洁能股份有限公司 具有终端结构的场截止型igbt器件及其制造方法
CN109671771A (zh) * 2018-11-19 2019-04-23 全球能源互联网研究院有限公司 Igbt芯片的背面结构、igbt芯片结构及制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021259088A1 (zh) * 2020-06-24 2021-12-30 全球能源互联网研究院有限公司 Igbt器件的背面结构及其制备方法、igbt器件

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