CN111640729B - 一种易于大尺寸元件底部填充的转接板及其制造方法 - Google Patents

一种易于大尺寸元件底部填充的转接板及其制造方法 Download PDF

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CN111640729B
CN111640729B CN202010316234.2A CN202010316234A CN111640729B CN 111640729 B CN111640729 B CN 111640729B CN 202010316234 A CN202010316234 A CN 202010316234A CN 111640729 B CN111640729 B CN 111640729B
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李全兵
顾骁
宋健
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • H01L21/4814Conductive parts
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    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8134Bonding interfaces of the bump connector
    • H01L2224/81345Shape, e.g. interlocking features
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract

本发明涉及一种易于大尺寸元件底部填充的转接板及其制造方法,所述转接板包括铜柱层(1),所述铜柱层(1)图形与后续贴装元件底部焊垫图形对应,所述铜柱层(1)外围包封有介质材料(2),所述介质材料(2)采用光敏性材料,所述光敏性材料经光照后溶解度会发生变化。本发明一种易于大尺寸元件底部填充的转接板及其制造方法,它能够抬高表面贴装器件底部的间隙,使其更加易于塑封料的填充。

Description

一种易于大尺寸元件底部填充的转接板及其制造方法
技术领域
本发明涉及一种易于大尺寸元件底部填充的转接板及其制造方法,属于半导体封装技术领域。
背景技术
目前一些大颗SIP产品直接将尺寸比较大的QFN或者LGA产品进行表面贴装并使用塑封料直接进行底部填充,而这些产品表面贴装后底部间距一般小于50um,塑封料很难将底部完全填充,会有填充不充分的问题,导致后续产品失效。
发明内容
本发明所要解决的技术问题是针对上述现有技术提供一种易于大尺寸元件底部填充的转接板及其制造方法,它能够抬高表面贴装器件底部的间隙,使其更加易于塑封料的填充。
本发明解决上述问题所采用的技术方案为:一种易于大尺寸元件底部填充的转接板,它包括铜柱层,所述铜柱层图形与贴装元件底部焊垫图形相对应,所述铜柱层之间设置有介质材料,所述介质材料采用光敏性材料,所述光敏性材料经光照后溶解度会发生变化。
所述光敏性材料为叠氮醌类化合物材料,经光照后会发生光分解反应,溶解度发生变化,由油溶性转变为水溶性。
所述转接板尺寸与贴装元件尺寸相同。
一种易于大尺寸元件底部填充的转接板的制造方法,所述方法包括以下步骤:
步骤一、取一铜基材,使用化学蚀刻或者机械冲压的方式形成铜柱层,铜柱层图形与贴装元件底部焊垫图形和尺寸相同;
步骤二、利用网板印刷方式使用光敏性材料完全填充至铜柱层的镂空区域,然后冷却定型形成整片转接板;
步骤三、将整片转接板切割成单颗结构。
一种易于大尺寸元件底部填充的转接板的使用方法,所述方法包括以下步骤:
步骤一、在线路板上贴装单颗转接板结构;
步骤二、将贴装转接板的产品进行曝光工艺,在紫外光源的照射下,光敏性材料发生光分解反应,由油溶性性质转变为水溶性性质,使光敏性材料易溶于水;
步骤三、将贴装元件贴装在转接板上,贴装元件的底部焊垫位置对准转接板的铜柱层的图形;
步骤四、使用常温水进行冲洗,水洗后光敏性材料溶于水中;
步骤五、将线路板表面、转接板、贴装元件进行整体塑封,塑封料可以完全填充至贴装元件底部与线路板之间的空间。
与现有技术相比,本发明的优点在于:
1、本发明的转接板设置于贴装元件的底部,在保证产品能够正常运行的前提下,增加贴装元件的底部高度,增大填充空间,保证贴装元件的底部被完全填充,保证产品可靠性;
2、本发明可以控制铜柱层的高度以适应不同尺寸的贴装元件。
附图说明
图1、图2为本发明一种易于大尺寸元件底部填充的转接板的结构示意图,其中图2为图1的A-A剖视图。
图3~图5为本发明一种易于大尺寸元件底部填充的转接板的各工序流程示意图。
图6~图10为本发明一种易于大尺寸元件底部填充的转接板使用方法的各工序流程示意图。
其中:
铜柱层1
介质材料2。
具体实施方式
以下结合附图实施例对本发明作进一步详细描述。
参见图1、图2,本发明涉及的一种易于大尺寸元件底部填充的转接板,它包括铜柱层1,所述铜柱层1图形与贴装元件底部焊垫图形相对应,所述铜柱层1之间设置有介质材料2,所述介质材料2采用光敏性材料,所述光敏性材料经光照后溶解度会发生变化。
所述光敏性材料为叠氮醌类化合物材料,经光照后发生光分解反应,由油溶性可以转变为水溶性。
所述转接板尺寸与贴装元件尺寸相同。
其制造方法包括以下步骤:
步骤一、参见图3,取一铜基材,使用化学蚀刻或者机械冲压方式形成铜柱层,铜柱层图形与贴装元件底部焊垫图形和尺寸相同;
步骤二、参见图4,利用网板印刷方式使用光敏性材料完全填充至铜柱层的镂空区域,然后使其冷却定型形成整片转接板结构;
步骤三、参见图5,将整片转接板切割成单颗结构。
其使用方法步骤如下:
步骤一、参见图6,在线路板上贴装单颗转接板结构;
步骤二、参见图7,将贴装转接板的产品进行曝光工艺,在紫外光源的照射下,光敏性材料发生光分解反应,由油溶性性质转变为水溶性性质,使光敏性材料易溶于水;
步骤三、参见图8,将贴装元件贴装在转接板上,贴装元件的底部焊垫位置对准转接板的铜柱层的图形;
步骤四、参见图9,使用常温水对转接板进行冲洗,水洗后光敏性材料溶于水中,留下垫高的铜柱层,可以增加贴装元件的底部填充空间;
步骤五、参见图10,将线路板表面、转接板、贴装元件进行整体塑封,由于贴装元件的底部被转接板垫高,塑封料可以完全填充至贴装元件底部与线路板之间的空间。
上述实施例外,本发明还包括有其他实施方式,凡采用等同变换或者等效替换方式形成的技术方案,均应落入本发明权利要求的保护范围之内。

Claims (5)

1.一种易于大尺寸元件底部填充的转接板,其特征在于:它包括铜柱层(1),所述铜柱层(1)图形与贴装元件底部焊垫图形相对应,所述铜柱层(1)之间设置有介质材料(2),所述介质材料(2)采用光敏性材料,所述光敏性材料经光照后溶解度会发生变化,在紫外光源的照射下,光敏性材料发生光分解反应,由油溶性性质转变为水溶性性质,使光敏性材料易溶于水。
2.根据权利要求1所述的一种易于大尺寸元件底部填充的转接板,其特征在于:所述光敏性材料为叠氮醌类化合物材料,经光照后发生光分解反应,由油溶性可以转变为水溶性。
3.根据权利要求1所述的一种易于大尺寸元件底部填充的转接板,其特征在于:所述转接板尺寸与贴装元件尺寸相同。
4.一种易于大尺寸元件底部填充的转接板的制造方法,其特征在于所述方法包括以下步骤:
步骤一、取一铜基材,使用化学蚀刻或机械冲压方式形成铜柱层,铜柱层图形与贴装元件底部焊垫图形和尺寸相同;
步骤二、采用网板印刷方式使用光敏性材料完全填充至铜柱层的镂空区域,然后冷却定型形成整片转接板,在紫外光源的照射下,光敏性材料发生光分解反应,由油溶性性质转变为水溶性性质,使光敏性材料易溶于水;
步骤三、将整片转接板切割成单颗结构。
5.一种如权利要求1所述的易于大尺寸元件底部填充的转接板的使用方法,其特征在于所述方法包括以下步骤:
步骤一、在线路板上贴装单颗转接板结构;
步骤二、将贴装转接板的产品进行曝光工艺,在紫外光源的照射下,光敏性材料发生光分解反应,由油溶性性质转变为水溶性性质,使光敏性材料易溶于水;
步骤三、将贴装元件贴装在转接板上,贴装元件的底部焊垫位置对准转接板的铜柱层的图形;
步骤四、使用常温水进行冲洗,水洗后光敏性材料溶于水中;
步骤五、将线路板表面、转接板、贴装元件进行整体塑封,塑封料可以完全填充至贴装元件底部与线路板之间的空间。
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CN102265394A (zh) * 2008-12-24 2011-11-30 Lg伊诺特有限公司 多行引线框架的结构及其半导体封装及制造方法
CN108198761A (zh) * 2017-12-29 2018-06-22 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺
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