CN111640702A - Semiconductor manufacturing apparatus and method for manufacturing semiconductor device - Google Patents

Semiconductor manufacturing apparatus and method for manufacturing semiconductor device Download PDF

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Publication number
CN111640702A
CN111640702A CN202010118139.1A CN202010118139A CN111640702A CN 111640702 A CN111640702 A CN 111640702A CN 202010118139 A CN202010118139 A CN 202010118139A CN 111640702 A CN111640702 A CN 111640702A
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pushing
bare chip
peeling
block
unit
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CN111640702B (en
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名久井勇辉
五十岚维月
齐藤明
冈本直树
栗原芳弘
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Fasford Technology Co Ltd
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Fasford Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68742—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a lifting arrangement, e.g. lift pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67138—Apparatus for wiring semiconductor or solid state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling

Abstract

The invention provides a semiconductor manufacturing apparatus and a semiconductor device manufacturing method, which can control a pushing unit with an optimal time sequence from the viewpoint of low pressure or high speed picking performance of a bare chip. The semiconductor manufacturing apparatus includes: a pushing unit for pushing the bare chip from the lower part of the cutting belt, wherein the pushing unit is provided with a plurality of blocks contacted with the cutting belt; a collet for adsorbing the bare chip; and a control unit configured to perform feedback control on a peeling model that reproduces characteristics of the pushing unit so that an output of the peeling model follows a target value of a peeling amount of the bare chip from the dicing tape and a bending stress of the entire bare chip, and to set a pushing amount as a control input to the peeling model to a pushing amount of the block of the pushing unit.

Description

Semiconductor manufacturing apparatus and method for manufacturing semiconductor device
Technical Field
The present invention relates to a semiconductor manufacturing apparatus, and is applicable to, for example, a chip mounter provided with a pusher unit.
Background
In general, in a die mounter which mounts a semiconductor chip called a bare chip on a surface of, for example, a wiring board, a lead frame, or the like (hereinafter, collectively referred to as a substrate), the following operations (operations) are repeated: the bare chip is carried onto the substrate using a suction nozzle such as a collet, and is mounted by applying a pressing force and heating the bonding material.
In a die mounting process performed by a semiconductor manufacturing apparatus such as a die mounter, there is a peeling process of peeling off a die divided from a semiconductor wafer (hereinafter, referred to as a wafer). In the peeling step, the bare chips are pushed from the back surface of the dicing tape by the pushing unit, the bare chips are peeled one by one from the dicing tape held in the bare chip supply unit, and the bare chips are carried onto the substrate using a suction nozzle such as a collet.
For example, according to japanese patent laid-open No. 2005-117019 (patent document 1), when a bare chip to be peeled out of a plurality of bare chips attached to a dicing tape is pushed and peeled from the dicing tape, a suction block (pushing unit) peels the bare chip from the dicing tape at a low pressure from the periphery of the bare chip by pushing up a multi-layered block into a pyramid shape by one driving shaft of a pusher.
Documents of the prior art
Patent document
Patent document 1: japanese patent laid-open publication No. 2005-117019
Patent document 2: japanese patent laid-open publication No. 2017-224640
Disclosure of Invention
In recent years, wafers (bare chips) have become thinner due to the advent of bare chip package-on-package and 3D-NAND (three-dimensional NAND flash memory). When the bare chip is made thin, the rigidity of the bare chip becomes extremely low as compared with the adhesive force of the dicing tape. Therefore, in order to pick up a thin bare chip of, for example, several tens of μm or less, it is necessary to reduce the pressure applied to the bare chip (low pressure).
In the pushing of the multi-layer block by one drive shaft as described above, since the pushing amount of each block is mechanically limited to be fixed, the pushing is a linear timing in which the block waits for a fixed time until the separation is sufficiently performed after the equal acceleration, the constant velocity operation, and the equal deceleration. However, when conditions such as the type of dicing tape and the thickness of a bare chip are changed in the linear sequence, the amount of pushing the block is not necessarily optimal. In addition, in the linear timing, the timing may not be optimal from the viewpoint of low pressure or high speed pickup of the bare chip.
The invention provides a semiconductor manufacturing apparatus capable of controlling a pushing unit with an optimal sequence from the viewpoint of low pressure performance or high speed pickup performance of a bare chip.
Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.
A brief description of a typical configuration of the present invention is as follows.
That is, the semiconductor manufacturing apparatus includes: a pushing unit for pushing the bare chip from the lower side of the dicing tape, the pushing unit having a plurality of blocks in contact with the dicing tape; a collet for adsorbing the bare chip; and a control unit configured to perform feedback control on a peeling model that reproduces characteristics of the pushing unit so that an output of the peeling model follows a target value of a peeling amount of the bare chip from the dicing tape and a bending stress of the entire bare chip, and to set a pushing amount as a control input to the peeling model to a pushing amount of the block of the pushing unit.
Effects of the invention
According to the semiconductor manufacturing apparatus, the control can be performed at an optimum timing from the viewpoint of low pressure or high speed pickup of the bare chip.
Drawings
Fig. 1 is a diagram illustrating the structure of the main part of the jack unit.
Fig. 2 is a diagram illustrating a pushing timing of the pushing unit.
Fig. 3 is a block diagram illustrating a feedback control system.
Fig. 4 is a diagram illustrating a bare chip lift-off model.
Fig. 5 is a diagram illustrating a bonding material model.
Fig. 6 is a flow chart illustrating the calculation of a bare chip lift-off model.
Fig. 7 is a conceptual view of the chip mounter of the embodiment as viewed from above.
Fig. 8 is a diagram illustrating the operation of the pick-up head and the mounting head when viewed from the direction of arrow a in fig. 7.
Fig. 9 is a perspective view showing an external appearance of the bare chip supply portion of fig. 7.
Fig. 10 is a schematic cross-sectional view showing a main portion of the bare chip supply portion of fig. 7.
Fig. 11 is an external perspective view of the pushing unit of fig. 9.
Fig. 12 is a top view of a portion of the 1 st unit of fig. 11.
Fig. 13 is a top view of a portion of the 2 nd unit of fig. 11.
Fig. 14 is a top view of a portion of the 3 rd cell of fig. 11.
Fig. 15 is a longitudinal sectional view of the pushing unit of fig. 11.
Fig. 16 is a longitudinal sectional view of the pushing unit of fig. 11.
Fig. 17 is a diagram showing the structure of a collet section in the pusher unit and the pickup head of the embodiment.
Fig. 18 is a flowchart for explaining a pick-up operation of the chip mounter of fig. 7.
Fig. 19 is a flowchart for explaining a manufacturing method of the semiconductor device of the embodiment.
Fig. 20 is a diagram illustrating numerical examples of the nonlinear timing and the linear timing.
Fig. 21 is a block diagram illustrating a feed-forward control system for each axis.
Fig. 22 is a flowchart illustrating an example of the pushing control of each block.
Fig. 23 is a flowchart illustrating another example of the pushing control of each block.
Fig. 24 is a block diagram illustrating a feedback control system.
Fig. 25 is a flowchart illustrating the pushing control of each block.
Description of the reference numerals
11: wafer with a plurality of chips
13: pushing unit
16: cutting belt
22: collet clamp
8: control unit
10: chip mounter
D: bare chip
Detailed Description
Hereinafter, embodiments and examples will be described with reference to the drawings. However, in the following description, the same components are denoted by the same reference numerals, and redundant description thereof may be omitted. In addition, although the drawings schematically show the width, thickness, shape, and the like of each part as compared with the actual form in order to make the description more clear, the drawings are merely examples in principle and do not limit the explanation of the present invention.
First, the pushing unit will be described with reference to fig. 1 and 2. Fig. 1 is a diagram showing a configuration of a main part of the jack unit, fig. 1 (a) is a sectional view taken along line a-a of fig. 1 (b), and fig. 1 (b) is a plan view. Fig. 2 is a diagram showing a pushing sequence of the pushing unit, fig. 2 (a) is a diagram showing a linear sequence, fig. 2 (b) is a diagram showing a first example of a nonlinear pushing sequence, and fig. 2 (c) is a diagram showing a second example of a nonlinear pushing sequence.
As shown in fig. 1, the pushing unit TUU includes: a dome DM of a dicing tape DCT positioned on the outer periphery of a bare chip D to be picked up and a push block part BLK positioned at an opening part of the dome DM are sucked. The ejector block BLK is constituted by, for example, three blocks BLK1, BLK2, and BLK 3. As shown in fig. 1 (b), the rectangular frame-shaped block BLK2 is located inside the rectangular frame-shaped block BLK1, and the rectangular block BLK3 is located inside the rectangular frame-shaped block BLK2 in a plan view. As shown in fig. 1 (a), block BLK1 is pushed to a position above dome DM, and blocks BLK2 and BLK3 are pushed to a position above block BLK 1.
As described above, the pushing operation of the conventional block is performed according to the linear pushing sequence in which the block waits for a fixed time period after the constant acceleration, the constant speed operation, or the constant deceleration until the separation is sufficiently performed. As shown in FIG. 2 (a), in the linear pushing sequence, the pushing amount of the block of the pushing unit TUU increases in proportion to the time and reaches the maximum value (h) of the pushing amountgmax) The back pushing action is stopped to wait for the timing sequence of stripping the bare chip D from the cutting belt DCT. Here, the maximum amount of push (h) will be reachedgmax) Is set as tgmax. Further, the pushing of the inner block is performed after the right end of the time axis shown in fig. 2 (a).
In the inventors' studies, the bare chip showed the following nonlinear behavior: the peeling starts slowly from the dicing tape and the peeling accelerates as the peeling progresses. In the linear timing, the timing may not be optimal from the viewpoint of low pressure and high speed pickup of the bare chip.
Therefore, in the embodiment, the pushing is performed according to the nonlinear pushing timing in which the speed in the pushing process is made variable in accordance with the peeling of the bare chip. In order to realize the pushing, the pushing is performed by performing feedback control on the pushing unit. The block pushing speed and the block pushing amount of the pushing unit can be set in a programmable manner.
Next, feedback control will be described with reference to fig. 3. Fig. 3 (a) is a block diagram showing a general feedback control system, and fig. 3 (b) is a block diagram showing a control system of a pushing unit according to an embodiment.
As shown in fig. 3 (a), a general feedback control (PID control) system is composed of a control target, a sensor, and a PID controller. The PID controller (c)(s) determines an input to a control target (operation amount: u (s)) by combining three operations of proportional operation (P), integral operation (I), and differential operation (D) with respect to a deviation signal (e (s)) between an output (control amount: y (s)) measured by a sensor from the control target (g (s)) and a target value (r (s)) to be followed.
The control amount of the pushing unit as a control target includes a peeling amount of the bare chip D from the dicing tape DCT and a bending stress of the entire bare chip D. They are difficult to measure by sensors.
Therefore, in the embodiment, as shown in fig. 3 (b), a feedback control system is configured for the peeling model. In an embodiment, a peeling amount and a bending stress of the entire bare chip are supplied to a target input (r (s)) of a peeling model (gm (s)), and the peeling amount is supplied to the peeling model (gm (s)) and an actual pushing target (g (s)) as control inputs (u (s)). By configuring the compensator (c (s)) as a PID controller so that the output (y (s)) follows the target input (r (s)), the pushing amount as the control input (u (s)) is adjusted in accordance with the operation of the stripping model (gm (s)).
When the characteristics of the actual pushing object (g (s)) can be sufficiently reproduced by the peeling model (gm (s)) by supplying the generated pushing amount to the actual pushing object (g (s)), the actual pushing object (g (s)) can obtain a peeling result designed in the feedback control system using the peeling model (gm (s)).
The peeling model had the following characteristics obtained by the study of the inventors.
(1) The peeling is started with a pushing amount above a certain amount.
(2) The peeling is accelerated as the peeling proceeds from the start of peeling (the peeling acceleration as the peeling proceeds because the curvature becomes larger as the bare chip is closer to the root as the restoring force wrThe larger the bending moment becomes).
(3) The pushing amount is much more necessary in a dicing tape having a high peel strength, and the pushing time is much more expensive in a dicing tape having tackiness (the pushing amount at the start of peeling, the speed at which peeling proceeds are changed by changing the parameters of the adhesive material of the dicing tape).
Next, a peeling model will be described with reference to fig. 4 to 6. Fig. 4 is a view showing a die peeling model of a dotted line portion in fig. 1 (a), fig. 4 (a) is a view before pushing, fig. 4 (b) is a view during pushing, and fig. 4 (c) is a view showing a case where the adhesive material is broken. Fig. 5 is a diagram showing a bonding material model. Fig. 6 is a diagram showing a calculation flow of the bare chip peeling model.
One side of the bare chip D during ejection is considered as a cantilever beam held by the end face of the block BLK2 being ejected. At this time, the bare chip D is applied with a load equally distributed as shown in fig. 4 (a) by dicing the adhesive material of the tape DCT.
When the block BLK2 is pushed by the pushing amount (h), it is considered that the bare chip D is deformed as shown in fig. 4 (b) before the peeling starts.
Here, it is assumed that
w: sticking force of adhesive Material applied to Unit area [ N ]
L: width [ mm ] of block BLK1
h: pushing amount of block BLK2 [ mm ]
b: length of one side of Block BLK2 [ mm ]
E: young's modulus of bare chip [ N/mm ]2]
x: the amount of deflection at a position x from the end of the bare chip.
And the adhesive material fixing the bare chip D was modeled. Fig. 5 is a diagram showing an adhesive model (three-element model).
By receiving a reaction force (w) against the bending of the bare chip Dr) According to the damping constant (C)2) Deformation occurs over time. Is set at a reaction force (w)r) Specific elastic constant (K)1、K2) In the large case, at the displacement of (1、2) When the predetermined deformation amount is reached, the adhesive is broken. Is set at a displacement of1) In the event of the limit value being reached, the interface breaks down in the event of a displacement of: (2) Cohesive failure occurs when the limit is reached.
When the adhesive material is broken, since the bare chip D has the shape as shown in fig. 4 (c), w is recalculated so that a uniform distribution load is applied only to a portion (non-broken portion) where there is no breakage.
Calculation of the bare chip peeling model will be described with reference to fig. 6.
The position of the most front end (front end of the nondestructive part) which is not destroyed is xminWill not breakThe deflection of the front end of the damaged portion is xminUsing E, h, L, w, xminTo calculate xminUsing xmin、E、h、L、xminTo calculate an updated load (w) (step S1).
And x at the front end of the nondestructive partminReaction force (w) generated byr) As xmin-xmin+1The bending moment therebetween is calculated (step S2).
Using wr、K1To calculate x of the front end of the nondestructive partminAmount of deformation of the adhesive material (b) ((1) Using wr、K1、C2To calculate the deformation amount (1) (step S3). It is determined whether or not the deformation amount exceeds a predetermined value (whether or not the adhesive is broken) (step S4).
At xminWhen the adhesive material is broken, x is setminThe calculated step size Δ x is increased (step S5).
This was repeated until no further disruption occurred.
Next, the time is increased by a step Δ t, using wr、1、2、K1、C2To calculate xminThe amount of deformation of the adhesive (step S6).
Let x beminAmount of deflection (x) of bare chip D in (1)min) Reducing the amount of deformation of the bonding material: (1、2) The distributed load (w) is recalculated to update the total deflection.
The calculation results (numerical examples) of the nonlinear sequence and the constant rate advance pushing sequence (linear sequence) will be described with reference to fig. 20. Fig. 20 (a) is a graph showing the pushing amount and the peeling amount in a linear sequence, and fig. 20 (b) is a graph showing the bare chip bending stress in a linear sequence. Fig. 20 (c) is a graph showing the pushing amount and the peeling amount in the nonlinear sequence, and fig. 20 (d) is a graph showing the bare chip bending stress in the nonlinear sequence.
In linear time sequence, set as
The pushing amount is 300 μm, and the pushing speed is 1 mm/sec.
In non-linear timing, for the lift-off model,
when L is 0.5mm, b is 10mm, E is 185000N/mm2The thickness of the bare chip is 20 μm, K1＝20N/mm、K2＝1.5N/mm、C20.01N/(mm/s), and the elongation allowed by the adhesive material is 0.6mm,
to form C(s) ═ Kp+Ki/s+KdS
Kp＝[1，0]、Ki＝[0，0]、Kd＝[0，0]
r(s) ([ 0.5, 0] (peeling amount ═ 0.5mm, bare chip bending stress ═ 0).
Here, Gm(s) and G(s) are set to have no error.
As shown in fig. 20 (a) and (b), the peeling time was 0.65 seconds and the maximum pressure was 10MPa in the linear sequence. As shown in fig. 20 (c) and (d), the peeling time was 0.58 seconds and the maximum pressure was 8.5Mpa in the nonlinear sequence, and both the peeling time and the maximum pressure were more effective than the linear sequence.
Next, feedforward control for each axis using the peeling model generated in the feedback control system will be described with reference to fig. 21 to 23. Fig. 21 is a diagram illustrating the feedforward control system for each axis, where fig. 21 (a) is a block line diagram for the block BLK1, fig. 21 (b) is a block line diagram for the block BLK2, and fig. 21 (c) is a block line diagram for the block BLK 3. Fig. 22 is a flowchart showing an example of the pushing control of each block. Fig. 23 is a flowchart showing another example of the pushing control of each block.
Although the configurations and operations of (a), (b), and (c) of fig. 21 are basically the same as those of (b) of fig. 3, the control input (u (s)) is input to the motor drivers for blocks BLK1, BLK2, and BLK3 as controllers, and the pushing operation of blocks BLK1, BLK2, and BLK3 as actual pushing targets (g (s)) is controlled.
As shown in fig. 21 (a), a peeling model (gm (s)) for the block BLK1 is generated in the same manner as in fig. 3 (b). This is the peel model generation of block BLK1 of step S11 of fig. 22, 23. The resulting stripping model (gm (s)) for block BLK1 becomes the target input (r (s)) for block BLK 2.
As shown in fig. 21 (b), a peeling model (gm (s)) for the block BLK2 is generated in the same manner as in fig. 3 (b). This is the peel model generation of block BLK2 of step S21 of fig. 22, 23. The resulting stripping model (gm (s)) for block BLK2 becomes the target input (r (s)) for block BLK 3.
As shown in fig. 21 (c), a peeling model (gm (s)) for the block BLK3 is generated in the same manner as in fig. 3 (b). This is the peel model generation of block BLK3 of step S31 of fig. 22, 23.
In the flow of fig. 22, the pushing control of each block is performed while generating a peeling model of each block. That is, after the peel model of the block BLK1 is generated in step S11, the pushing operation of the block BLK1 is performed in parallel with the peel model generation of the block BLK2 in step S21 (step S12). Next, after the peel model of the block BLK2 is generated in step S21, the pushing operation of the block BLK2 is performed in parallel with the peel model generation of the block BLK3 in step S31 (step S22). Finally, after the peel model of the block BLK3 is generated in step S31, the block BLK3 is pushed (step S32).
In the flow of fig. 23, after the peeling models of all the blocks are generated, the pushing control of each block is performed. That is, the peel model of the block BLK1 is generated (step S11), the peel model of the block BLK2 is generated (step S21), and the peel model of the block BLK3 is generated (step S31). Then, the block BLK1 is pushed (step S12), the block BLK2 is pushed (step S22), and the block BLK3 is pushed (step S32).
Next, feedback control for each axis using the peeling model generated in the feedback control system will be described with reference to fig. 24 and 25. Fig. 24 is a block diagram illustrating a feedback control system. Fig. 25 is a flowchart illustrating the pushing control of each block.
In the control system of fig. 24, the peeling model generated in the feedback control system is the same as that of fig. 3 (b), but the control input (u (s)) is input to the motor driver for blocks BLK1, BLK2, and BLK3 as the controller, the pushing operation of blocks BLK1, BLK2, and BLK3 as the actual pushing objects (g (s)) is controlled, and the peeling state confirmed by the sensor is fed back to the control input (u (s)).
As shown in fig. 25, the peeling model (gm (S)) for the block BLK1 is generated (step S) in the same manner as in fig. 2211). The control input (u (S)) is input to the motor driver for the block BLK1 as the controller, and the pushing operation of the block BLK1 as the actual pushing target (g (S)) is controlled (step S12). The detachment is confirmed by the sensor (step S13), and the nondestructive part tip (x) is determinedmin) Whether or not the adhesive material at (b) is broken as a result of the simulation (step S14). If not, the process returns to step S11 to generate the peeling model (gm (S)) for the block BLK1 again.
If so, the generated stripping model (gm (S)) for block BLK1 becomes the target input (r (S)) for block BLK2, and the stripping model (gm (S)) for block BLK2 is generated (step S21). The control input (u (S)) is input to the motor driver for the block BLK2 as the controller, and the pushing operation of the block BLK2 as the actual pushing target (g (S)) is controlled (step S22). The detachment is confirmed by the sensor (step S23), and the nondestructive part tip (x) is determinedmin) Whether or not the adhesive material at (b) is broken as a result of the simulation (step S24). If not, the process returns to step S21 to generate the peeling model (gm (S)) for the block BLK2 again.
If so, the generated stripping model (gm (S)) for block BLK2 becomes the target input (r (S)) for block BLK3, and the stripping model (gm (S)) for block BLK3 is generated (step S31). The control input (u (S)) is input to the motor driver for the block BLK3 as the controller, and the pushing operation of the block BLK3 as the actual pushing target (g (S)) is controlled (step S32). The detachment is confirmed by the sensor (step S33), and the nondestructive part tip (x) is determinedmin) Whether or not the adhesive material at (b) is broken as a result of the simulation (step S34). If not, the process returns to step S13, and the peeling model for the block BLK3 is generated again (gm (S).
The control of each axis may be performed by using both feedforward control and feedback control.
Next, a non-linear pushing timing sequence will be described with reference to fig. 2 (b) and (c).
As shown in fig. 2 (b), the nonlinear push sequence of the first example is a sequence of: the pushing amount of the block of the pushing unit does not necessarily increase in proportion to the time, inThe maximum value (h) of the pushing quantity is reachedgmax) Thereafter, the pushing operation is reduced without stopping, and the bare chip is waited to be peeled off from the dicing tape. In the figure, there is a convex inflection point above. T of the first non-linear push sequencegmaxT of linear thrusting sequence than (a) of FIG. 2gmaxThe early stage, namely the pushing speed is high. Further, the pushing of the inner block is performed after the right end of the time axis shown in fig. 2 (b).
As shown in fig. 2 (c), in the non-linear thrusting sequence of the second example, the following sequence is used: the pushing amount of the block of the pushing unit is not necessarily increased in proportion to the time, and reaches the maximum value (h) of the pushing amountlmax) Then, the pushing action is temporarily reduced without stopping, and reaches a minimum value (h)lmin) Then, the bare chip is waited for to be peeled off from the dicing tape while being increased. Here, a maximum (h) of the pushing amount will be reachedlmax) Is set as tlmaxThe minimum value (h) of the pushing amount is reachedlmin) Is set as tlmin. In the figure, there are inflection points that are convex upward and inflection points that are convex downward. Second example of t for the non-linear push timinglmaxT of linear thrusting sequence than (a) of FIG. 2gmaxThe early stage, namely the pushing speed is high. Further, the pushing of the inner block is performed after the right end of the time axis shown in fig. 2 (c).
[ examples ] A method for producing a compound
Fig. 7 is a schematic plan view showing the chip mounter according to the embodiment. Fig. 8 is a diagram illustrating the operation of the pick-up head and the mounting head when viewed from the direction of arrow a in fig. 7.
The chip mounter 10 generally has: a bare chip supply section 1 that supplies a bare chip D mounted on a substrate S printed with one or more product regions (hereinafter referred to as package regions P) that eventually become one package; a pickup section 2; an intermediate stage section 3; a mounting portion 4; a conveying part 5; a substrate supply unit 6; a substrate carrying-out section 7; and a control unit 8 for monitoring and controlling the operation of each unit. The Y-axis direction is the front-rear direction of the chip mounter 10, and the X-axis direction is the left-right direction. The bare chip supply unit 1 is disposed on the front side of the chip mounter 10, and the mounting unit 4 is disposed on the inner side.
First, the bare chip supply section 1 supplies the bare chip D mounted on the package region P of the substrate S. The bare chip supply section 1 includes a wafer holding stage 12 that holds a wafer 11, and an urging unit 13 shown by a broken line that urges a bare chip D from the wafer 11. The die supplying unit 1 moves in the XY-axis direction by a driving mechanism not shown, and moves the die D to be picked up to the position of the top pushing unit 13.
The pickup section 2 includes: a pickup head 21 for picking up the bare chip D; a Y drive section 23 of the pickup head for moving the pickup head 21 in the Y axis direction; and driving units, not shown, for moving the collet 22 up and down, rotating it, and moving it in the X-axis direction. The pickup head 21 has a collet 22 (see fig. 10) for sucking and holding the pushed bare chip D at the tip, picks up the bare chip D from the bare chip supply unit 1, and mounts the bare chip D on the intermediate stage 31. The pickup head 21 includes driving units, not shown, for moving the collet 22 up and down, rotating, and moving in the X-axis direction.
The intermediate stage portion 3 includes: an intermediate stage 31 on which the bare chip D is temporarily placed; and a stage recognition camera 32 for recognizing the bare chip D on the intermediate stage 31.
The mounting section 4 picks up the bare chip D from the intermediate stage 31 and mounts it on the package region P of the substrate S being conveyed or on the bare chip already mounted on the package region P of the substrate S. The mounting portion 4 has: a mounting head 41 including a collet 42 (see fig. 2) for holding the bare chip D by suction at the tip end, similarly to the pickup head 21; a Y drive unit 43 that moves the mounting head 41 in the Y axis direction; and a substrate recognition camera 44 that takes an image of a position recognition mark (not shown) of the package region P of the substrate S to recognize the mounting position.
With this configuration, the mounting head 41 corrects the pickup position and the posture based on the imaging data of the stage recognition camera 32, picks up the bare chip D from the intermediate stage 31, and mounts the bare chip D on the substrate based on the imaging data of the substrate recognition camera 44.
The conveying unit 5 includes a substrate conveying claw 51 for gripping and conveying the substrate S, and a conveying path 52 for moving the substrate S. The substrate S is moved by a nut, not shown, of a substrate transport claw 51 provided in the transport path 52 being driven by a ball screw, not shown, provided along the transport path 52.
With such a configuration, the substrate S moves from the substrate supply unit 6 to the mounting position along the conveyance path 52, and after mounting, moves to the substrate carry-out unit 7, and the substrate S is delivered to the substrate carry-out unit 7.
The control unit 8 includes: a memory for storing a program (software) for monitoring and controlling the operation of each part of the chip mounter 10; and a Central Processing Unit (CPU) that executes a program stored in the memory.
Next, the structure of the bare chip supply section 1 will be described with reference to fig. 9 and 10. Fig. 9 is a perspective view showing an external appearance of the bare chip supply portion of fig. 7. Fig. 10 is a schematic cross-sectional view showing a main portion of the bare chip supply portion of fig. 7.
The bare chip supply unit 1 includes a wafer holding stage 12 that moves in the horizontal direction (XY-axis direction) and a pusher unit 13 that moves in the vertical direction. The wafer holding stage 12 includes: an extension ring 15 holding the wafer ring 14; and a support ring 17 for horizontally positioning the dicing tape 16 held by the wafer ring 14 and having the plurality of bare chips D bonded thereto. The pushing unit 13 is disposed inside the support ring 17.
The bare chip supply unit 1 lowers the extension ring 15 holding the wafer ring 14 when the bare chip D is pushed. As a result, the dicing tape 16 held by the wafer ring 14 is pulled, the interval of the bare chips D is expanded, and the bare chips D are pushed from below by the pushing unit 13, thereby improving the pick-up performance of the bare chips D. The adhesive for bonding the bare chip to the substrate is changed from a liquid state to a film state, and a film-like adhesive material called a Die Attach Film (DAF)18 is attached between the wafer 11 and the dicing tape 16. In the wafer 11 having the die bonding film 18, the wafer 11 and the die bonding film 18 are diced. Therefore, in the peeling step, the wafer 11 and the die bonding film 18 are peeled from the dicing tape 16. The peeling step will be described below regardless of the presence of the die bond film 18.
Next, the pushing unit 13 will be described with reference to fig. 11 to 16. Fig. 11 is an external perspective view of the pusher unit of the embodiment. Fig. 12 is a top view of a portion of the 1 st unit of fig. 11. Fig. 13 is a top view of a portion of the 2 nd unit of fig. 11. Fig. 14 is a top view of a portion of the 3 rd cell of fig. 11. Fig. 15 is a longitudinal sectional view of the pushing unit of fig. 11. Fig. 16 is a longitudinal sectional view of the pushing unit of fig. 11.
The pusher unit 13 includes a1 st unit 13a, a2 nd unit 13b to which the 1 st unit 13a is attached, and a3 rd unit 13c to which the 2 nd unit 13b is attached. The 2 nd unit 13b and the 3 rd unit 13c are portions that are common regardless of the type, and the 1 st unit 13a is a portion that can be replaced for each type.
The 1 st unit 13a has: a block portion 13a1 having blocks a1 to a 4; a dome head 13a2 having a plurality of suction holes; the suction holes 13a 3; and a suction hole 13a4 for suction of a dome, which converts the vertical movement of the concentric blocks B1 to B4 of the 2 nd unit 13B into the vertical movement of the four concentric square blocks a1 to a 4. The four blocks a 1-a 4 can move up and down independently. The planar shapes of the concentric square blocks a1 to a4 are configured to match the shape of the bare chip D. When the bare chip size is large, the number of blocks configured in a concentric square shape is larger than four. This can be achieved by moving the plurality of output units of the 3 rd unit and the concentric blocks of the 2 nd unit up and down independently of each other (without moving up and down). The pushing speed and the pushing amount of the four blocks A1-A4 can be set in a programmable manner.
The 2 nd unit 13B has circular tube-shaped blocks B1 to B6 and an outer peripheral portion 13B2, and converts the vertical movement of the output portions C1 to C6 arranged on the circumference of the 1 st unit 13a into vertical movement of six concentric blocks B1 to B6. The six blocks B1-B6 can independently move up and down. Here, since the 1 st cell 13a has only four blocks a1 to a4, the blocks B5 and B6 are not used.
The 3 rd cell 13c includes a central portion 13c0 and six peripheral portions 13c1 to 13c 6. The center portion 13C0 has six output portions C1 to C6 arranged at equal intervals on the circumference of the upper surface and independently moving up and down. The peripheral portions 13C1 to 13C6 can drive the output portions C1 to C6 independently of each other. The peripheral portions 13c1 to 13c6 include motors M1 to M6, respectively, and the central portion 13c0 includes push rod mechanisms P1 to P6 for converting the rotation of the motors into vertical movement by a cam or a link. The pusher mechanisms P1 to P6 give vertical motions to the output sections C1 to C6. The motors M2 and M5 and the pusher mechanisms P2 and P5 are not shown. Here, since the 1 st cell 13a has only four blocks a1 to a4, the peripheral portions 13c5 and 13c6 are not used. Therefore, the motors M5, M6, the pusher mechanisms P5, P6, and the outputs C5, C6 are not used.
Next, the relationship between the pushing unit and the collet will be described with reference to fig. 17. Fig. 17 is a diagram showing the structure of a collet section in the pusher unit and the pickup head of the embodiment.
As shown in fig. 17, the collet part 20 includes: a collet 22; a collet holder 25 that holds the collet 22; and suction holes 22v, 25v provided respectively for sucking the bare chip D. The suction surface of the collet 22 for sucking the bare chip has substantially the same size as the bare chip D.
The 1 st cell 13a has a crown 13a2 at the upper surface peripheral portion. The ejector 13a2 has a plurality of suction holes HL and hollow portions CV, and sucks the bare chip Dd around the bare chip D to be picked up by the collet 22 through the dicing tape 16 by sucking from the suction hole 13a 3. In fig. 17, although only one row of suction holes HL is shown around the block portion 13a1, a plurality of rows are provided to stably hold the bare chip Dd that is not the object of pickup. The bare chips D to be picked up by the collet 22 are sucked through the suction holes 13a4 sucked from the dome through the gaps A1v, A2v, A3v between the blocks A1 to a4 in the concentric rectangular shape and the hollow portion in the dome of the 1 st cell 13a, and are sucked through the dicing tape 16. Suction from the suction hole 13a3 and suction from the suction hole 13a4 can be performed independently.
The pusher unit 13 of the present embodiment can be applied to various bare chips by changing the shape of the block of the unit 1 and the number of blocks, and for example, can be applied to a bare chip having a die size of 20mm □ or less when the number of blocks is six. The number of output units of the 3 rd unit, the number of concentric blocks of the 2 nd unit, and the number of concentric square blocks of the 1 st unit are increased, so that the semiconductor device can be applied to a die having a die size larger than 20mm □.
Next, a pickup operation by the pusher unit 13 with the above-described configuration will be described with reference to fig. 18. Fig. 18 is a flowchart showing a processing flow of the pickup operation.
Step PS 1: the control section 8 moves the wafer holding stage 12 so that the picked-up bare chip D is positioned directly above the ejector unit 13, and moves the ejector unit 13 so that the upper surface of the 3 rd unit is in contact with the back surface of the dicing tape 16. At this time, as shown in fig. 19, the controller 8 sucks the dicing tape 16 through the suction holes HL of the dome head 13A2 and the gaps A1v, A2v, and A3v between the blocks so that the blocks A1 to a4 of the block portion 13A1 are flush with the surface of the dome head 13 A2.
Step PS 2: the control unit 8 lowers the collet 20 to position it above the bare chip D to be picked up, and sucks the bare chip D through the suction holes 22v and 25 v.
Step PS 3: the control unit 8 sequentially raises the blocks of the block portion 13a1 from the outside to perform the peeling operation. Here, the control unit 8 performs feed-forward control using the separation model according to the embodiment. That is, the controller 8 drives the pusher mechanism P4 by the motor M4 to raise only the outermost block a4 by several tens μ M to several hundreds μ M, and then lowers and stops it. The ascending and descending speeds are not fixed. As a result, a pushing portion where the dicing tape 16 is raised is formed around the block a4, and a minute space, i.e., a peeling start point is formed between the dicing tape 16 and the die bonding film 18. This space significantly reduces the Anchor effect (Anchor effect), i.e., the pressure applied to the bare chip D, and the subsequent peeling operation can be reliably performed. Next, the controller 8 drives the pusher mechanism P3 by the motor M3 to raise and stop only the second outer block A3 to a position higher than the block a 4. Next, the controller 8 drives the pusher mechanism P2 by the motor M2 to raise and stop only the third outer block a2 higher than the block A3. Finally, the controller 8 drives the pusher mechanism P1 by the motor M1 to raise and stop only the innermost block a1 higher than the block a 2.
Step PS 4: the control unit 8 raises the collet. In the final state of step S3, the contact area between the dicing tape 16 and the bare chip D becomes an area that can be peeled off by the ascent of the collet, and the bare chip D can be peeled off by the ascent of the collet 22.
Step PS 5: the controller 8 causes the blocks A1 to a4 of the block portion 13A1 to be flush with the surface of the dome head 13A2, and stops the suction of the dicing tape 16 by the suction holes HL of the dome head 13A2 and the gaps A1v, A2v, and A3v between the blocks. The control section 8 moves the pusher unit 13 so that the upper surface of the 1 st unit is separated from the back surface of the dicing tape 16.
The controller 8 repeats steps PS1 to PS5 to pick up the acceptable bare chips of the wafer 11.
Next, a method for manufacturing a semiconductor device using the chip mounter of the embodiment will be described with reference to fig. 19. Fig. 19 is a flowchart showing a method of manufacturing the semiconductor device of fig. 7.
Step BS 11: the wafer ring 14 holding the dicing tape 16 on which the bare chips D separated from the wafer 11 are attached is stored in a wafer cassette (not shown), and is carried into the die mounter 10. The control section 8 supplies the wafer ring 14 to the die supply section 1 from a wafer cassette filled with the wafer ring 14. Further, the substrate S is prepared and carried into the chip mounter 10. The controller 8 mounts the substrate S on the substrate transport claw 51 via the substrate supply unit 6.
Step BS 12: the control section 8 peels off the bare chip D as described above, and picks up the peeled bare chip D from the wafer 11. In this manner, the bare chip D peeled off from the dicing tape 16 together with the die bonding film 18 is sucked and held by the collet 22 and is conveyed to the next step (step BS 13). When the collet 22, which has carried the bare chips D to the next step, is returned to the bare chip supply unit 1, the next bare chip D is peeled off from the dicing tape 16 in accordance with the above-described procedure, and the bare chips D are peeled off one by one from the dicing tape 16 in accordance with the same procedure thereafter.
Step BS 13: the control unit 8 mounts the picked bare chip on the substrate S or laminates the bare chip on the mounted bare chip. The control unit 8 places the bare chip D picked up from the wafer 11 on the intermediate stage 31, picks up the bare chip D again from the intermediate stage 31 by the mounting head 41, and mounts it on the conveyed substrate S.
Step BS 14: the controller 8 takes out the substrate S with the bare chips D mounted thereon from the substrate transfer claw 51 by the substrate carry-out section 7. The substrate S is carried out from the chip mounter 10.
As described above, the bare chip D is mounted on the substrate S via the die bonding film 18 and is carried out from the die mounter. Then, the electrodes of the substrate S are electrically connected to each other through the Au wires in the wire bonding step. Next, the substrate S on which the bare chip D is mounted is carried into a die mounter, the 2 nd bare chip D is stacked on the bare chip D mounted on the substrate S via the die bonding film 18, and after being carried out from the die mounter, the substrate S is electrically connected to the electrode of the substrate S via the Au wire in the wire bonding step. The 2 nd bare chip D is peeled off from the dicing tape 16 by the above-described method, and then is carried to a chip attaching step to be laminated on the bare chip D. After repeating the above steps a predetermined number of times, the substrate S is conveyed to a molding step, and the plurality of bare chips D and the Au wires are sealed with a molding resin (not shown), thereby completing the stack package.
As described above, when a stack package in which a plurality of bare chips are three-dimensionally mounted on a substrate is assembled, the thickness of the bare chips is required to be as thin as 20 μm or less in order to prevent an increase in the package thickness. On the other hand, since the thickness of the dicing tape is about 100 μm, the thickness of the dicing tape becomes even 4 to 5 times the thickness of the bare chip.
When the thin bare chip is to be peeled off from the dicing tape, the deformation of the bare chip following the deformation of the dicing tape is likely to occur more significantly, but the chip mounter of the present embodiment can reduce damage to the bare chip when the bare chip is picked up from the dicing tape.
The present invention made by the present inventors has been described specifically above based on the embodiments and examples, but the present invention is not limited to the embodiments and examples described above, and various modifications can be made.
For example, although the plurality of blocks in unit 1 are described as concentric rectangular blocks, the blocks may be concentric circular or concentric elliptical blocks, or may be configured by arranging rectangular blocks in parallel.
In addition, although the pickup object bare chip and the peripheral bare chip are adsorbed/released at the same timing in the embodiment, the pickup object bare chip and the peripheral bare chip may be adsorbed/released at different timings. This enables more reliable peeling.
In the embodiment, the blocks of the respective layers are sequentially pushed, but since the respective layers are independent and can perform different operations, the pushing/pulling operations in both directions may be used in combination.
In the embodiments, although the example using the die bond film is described, a preform portion in which an adhesive is applied to a substrate may be provided without using the die bond film.
In the embodiments, the die mounter has been described which picks up the bare chip from the bare chip supply unit by the pickup head and mounts the bare chip on the intermediate stage, and mounts the bare chip mounted on the intermediate stage on the substrate by the mounting head.
For example, the present invention can be applied to a die mounter which mounts a bare chip of a bare chip supply section on a substrate by a mounting head without an intermediate stage and a pickup head.
Further, the present invention can be applied to a flip chip bonding machine that picks up a bare chip from a bare chip supply unit without an intermediate stage, rotates a bare chip pickup head upward, delivers the bare chip to a mounting head, and mounts the bare chip on a substrate by the mounting head.
Further, the present invention can be applied to a chip sorter in which a bare chip picked up by a pickup head from a bare chip supply unit is placed on a tray or the like without an intermediate stage and a mounting head.

Claims (15)

1. A semiconductor manufacturing apparatus is characterized by comprising:
a pushing unit which pushes the bare chip from below the dicing tape and has a plurality of blocks contacting the dicing tape;
a collet that adsorbs the bare chip; and
and a control unit configured to perform feedback control on a peeling model that reproduces characteristics of the pushing unit so that an output of the peeling model follows a target value of a peeling amount of the die from the dicing tape and a bending stress of the entire die, and to set a pushing amount as a control input to the peeling model to a pushing amount of the block of the pushing unit.
2. The semiconductor manufacturing apparatus according to claim 1,
the peeling model includes a deformation amount of the adhesive material calculated based on an attaching force of the adhesive material of the dicing tape calculated based on a pushing amount of the block, a width of the block, and a young's modulus of the bare chip and an adhesive material model of the adhesive material.
3. The semiconductor manufacturing apparatus according to claim 2,
the bonding material model includes an elastic constant and a damping constant.
4. The semiconductor manufacturing apparatus according to claim 3,
the peeling mold has:
a characteristic that peeling starts when the pushing amount is a predetermined value or more;
the characteristic that peeling is accelerated as peeling proceeds from the start of peeling; and
the pushing amount of the start of peeling and the speed of peeling progress are changed by changing the parameters of the adhesive.
5. The semiconductor manufacturing apparatus according to claim 1,
the control unit is configured to reduce the pushing amount and raise an inner block adjacent to the outer block, when the outer block among the plurality of blocks is raised to reach a maximum pushing amount.
6. The semiconductor manufacturing apparatus according to claim 1,
the control unit is configured to, after an outer block among the plurality of blocks is raised to reach a maximum value of the pushing amount, decrease the pushing amount to reach a minimum value of the pushing amount, and then increase the pushing amount to raise an inner block adjacent to the outer block.
7. The semiconductor manufacturing apparatus according to claim 1,
the pushing unit is configured to have a plurality of independent drive shafts corresponding to the plurality of blocks, and to be able to set a pushing speed and a pushing amount of the blocks in a programmable manner.
8. The semiconductor manufacturing apparatus according to claim 1,
the die further includes a die bonding film between the die and the dicing tape.
9. The semiconductor manufacturing apparatus according to claim 1,
the pick-up head is further provided with a pick-up head, and the collet is mounted on the pick-up head.
10. The semiconductor manufacturing apparatus according to claim 9,
further provided with:
an intermediate stage on which a bare chip picked up by the pickup head is placed; and
and a mounting head for mounting the bare chip mounted on the intermediate stage onto a substrate or a mounted bare chip.
11. A method for manufacturing a semiconductor device, comprising:
(a) and a step of carrying the wafer ring holding the dicing tape into a semiconductor manufacturing apparatus, the semiconductor manufacturing apparatus including: a pushing unit having a plurality of blocks contacting the dicing tape and pushing a bare chip from below the dicing tape, and a collet adsorbing the bare chip; and
(b) a step of pushing the bare chip by the pushing unit and picking up the bare chip by the collet,
in the step (b), a feedback control is performed on a peeling model for reproducing the characteristics of the pushing means so that the output of the peeling model follows the target values of the peeling amount of the bare chip from the dicing tape and the bending stress of the entire bare chip, and the pushing amount input as the control input to the peeling model is made to be the pushing amount of the block of the pushing means to push the bare chip.
12. The method for manufacturing a semiconductor device according to claim 11,
in the step (b), after the outer block of the plurality of blocks is raised to reach the maximum value of the pushing amount, the pushing amount is reduced, and the inner block adjacent to the outer block is raised.
13. The method for manufacturing a semiconductor device according to claim 11,
in the step (b), after the outer block among the plurality of blocks is raised to reach the maximum value of the pushing amount, the pushing amount is decreased to reach the minimum value of the pushing amount, and then the pushing amount is increased to raise the adjacent inner block of the outer block.
14. The method for manufacturing a semiconductor device according to claim 11,
the method further comprises (c) a step of attaching the bare chip to a substrate or an already attached bare chip.
15. The method for manufacturing a semiconductor device according to claim 14,
the step (b) further includes a step of mounting the picked bare chip on an intermediate stage,
the step (c) further includes a step of picking up the bare chip from the intermediate stage.
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