CN111630355A - 光检测装置 - Google Patents

光检测装置 Download PDF

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CN111630355A
CN111630355A CN201980009407.1A CN201980009407A CN111630355A CN 111630355 A CN111630355 A CN 111630355A CN 201980009407 A CN201980009407 A CN 201980009407A CN 111630355 A CN111630355 A CN 111630355A
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array substrate
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polysilicon layer
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passive quenching
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藤田卓也
田村有正
牧野健二
马场隆
山本晃永
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Hamamatsu Photonics KK
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Abstract

光检测装置具备由化合物半导体构成的雪崩光电二极管阵列基板(10)。在雪崩光电二极管阵列基板(10)，二维排列有以盖革模式动作的多个雪崩光电二极管(20)。电路基板(50)具有互相并联连接并形成至少1个信道(40)的多个输出单元(30)。各输出单元(30)具有被动淬灭元件(31)及电容元件(32)。被动淬灭元件(31)与多个雪崩光电二极管(20)的至少一个串联连接。电容元件(32)与至少1个雪崩光电二极管(20)串联连接且与被动淬灭元件(31)并联连接。

Description

光检测装置
技术领域
本发明涉及一种光检测装置。
背景技术
已知有一种二维排列有多个雪崩光电二极管的光检测装置(例如专利文献1)。多个雪崩光电二极管以盖革模式进行动作。多个雪崩光电二极管形成于由化合物半导体构成的半导体基板。
现有技术文献
专利文献
专利文献1：日本特表2012-531753号公报
发明内容
发明所要解决的问题
在形成于由化合物半导体构成的半导体基板的多个雪崩光电二极管以盖革模式动作的情况下，暗脉冲及剩余脉冲对应于温度变化而增加。若噪声因暗脉冲及剩余脉冲而增加，则有无法适当地检测来自雪崩光电二极管的信号的担忧。
已知在雪崩光电二极管以盖革模式动作的情况下，为了将雪崩倍增淬灭，而在雪崩光电二极管串联配置被动淬灭元件。对应于该被动淬灭元件的电阻值，决定连接于该被动淬灭元件的雪崩光电二极管内部所产生的雪崩倍增过程是否被适当地淬灭。若淬灭元件的电阻值不充分，则有因产生闭锁电流等而未适当淬灭的情况。为了适当淬灭，需要选择充分必要的淬灭元件的电阻值。
被动淬灭元件的电阻值越大，与被动淬灭元件串联连接的雪崩光电二极管的淬灭所需要的时间越增加。若淬灭所需要的时间增加，则无法以雪崩光电二极管检测光的死区时间增加。这样，为了兼得适当的淬灭及死区时间的降低并确保光检测灵敏度及光检测时间分辨率，寻求具有最适合的电阻值的被动淬灭元件的电路设计。
由于被动淬灭元件中的寄生电容也对脉冲信号带来影响，因而也谋求该寄生电容的去除。为了进一步提高光检测时间分辨率，也谋求提高脉冲信号的峰值。以满足上述所期望的全部条件的方式，设计使形成于由化合物半导体构成的半导体基板的多个雪崩光电二极管以盖革模式动作的装置是极其困难的。
本发明的一个方式的目的在于，提供一种光检测装置，其在多个雪崩光电二极管形成于由化合物半导体构成的半导体基板的结构中，兼得光检测灵敏度及光检测时间分辨率的提高。
解决问题的技术手段
本发明的一个方式所涉及的光检测装置具备雪崩光电二极管阵列基板及电路基板。雪崩光电二极管阵列基板由化合物半导体构成。在电路基板安装有雪崩光电二极管阵列基板。在雪崩光电二极管阵列基板，二维排列有多个雪崩光电二极管。多个雪崩光电二极管以盖革模式进行动作。电路基板具有互相并联连接的多个输出单元。多个输出单元形成至少1个信道。各输出单元具有被动淬灭元件及电容元件。被动淬灭元件与多个雪崩光电二极管的至少一个串联连接。电容元件与至少1个雪崩光电二极管串联连接且与被动淬灭元件并联连接。
本一个方式中，具有被动淬灭元件及电容元件的多个输出单元设置于与雪崩光电二极管阵列基板分体的电路基板。因此，与多个输出单元配置于雪崩光电二极管阵列基板的情况相比，可扩大可形成多个输出单元的空间。若输出单元设置于与雪崩光电二极管阵列基板分体的电路基板，则可降低产生于雪崩光电二极管的结构与输出单元间的寄生电容。该情况下，也可使用与雪崩光电二极管阵列基板不同的制造过程。因此，多个输出单元的设计变得容易。上述光检测装置具有的电容元件与至少1个雪崩光电二极管串联连接，且与被动淬灭元件并联连接。因此，通过电容元件的静电电容，可提高来自与电容元件串联连接的雪崩光电二极管的脉冲信号的峰值。因此，易检测来自多个雪崩光电二极管的脉冲信号，可进一步提高光检测时间分辨率。
本一个方式中，被动淬灭元件也可由设置于电路基板的第1多晶硅层形成。电容元件也可由设置于电路基板的第2多晶硅层、层叠于第2多晶硅层上的电介质层、及层叠于电介质层上的第3多晶硅层形成。第1多晶硅层在电路基板的厚度方向上形成为与第2多晶硅层或第3多晶硅层相同的高度。该情况下，可以简单的制造工序形成上述多个输出单元。
发明的效果
根据本发明的一个方式，提供了一种在多个雪崩光电二极管形成于由化合物半导体构成的半导体基板的结构中设计容易且可确保光检测精度的光检测装置。
附图说明
图1是一实施方式所涉及的光检测装置的立体图。
图2是显示光检测装置的截面结构的图。
图3是电路基板的俯视图。
图4是雪崩光电二极管阵列基板的光检测区域的俯视图。
图5是显示电路基板的结构的图。
图6是显示光检测装置所使用的电路结构的图。
图7是显示本实施方式的变形例所涉及的光检测装置所使用的电路结构的图。
图8是电路基板的安装区域的俯视图。
图9是显示来自雪崩光电二极管的脉冲信号的成分的图。
图10是显示再充电脉冲的特性的图。
图11是显示快速脉冲的特性的图。
具体实施方式
以下，参照附图，对本发明的实施方式进行详细的说明。另外，在说明中，对相同要素或具有相同功能的要素，使用相同符号，省略重复的说明。
首先，参照图1至图8，针对本实施方式所涉及的光检测装置的全体的结构进行说明。图1是本实施方式所涉及的光检测装置的立体图。图2是显示本实施方式所涉及的光检测装置的截面结构的图。图2中，为了提高视认性而省略阴影线。图3是电路基板的俯视图。图4是显示雪崩光电二极管阵列基板的一部分的俯视图。图6是显示本实施方式所涉及的光检测装置所使用的电路结构的图。图8是显示电路基板的一部分的俯视图。
光检测装置1如图1所示具备雪崩光电二极管阵列基板10及电路基板50。以下，将“雪崩光电二极管”称为“APD”。将“雪崩光电二极管阵列基板”称为“APD阵列基板”。电路基板50与APD阵列基板10相对配置。APD阵列基板10、电路基板50在俯视时均呈矩形状。
APD阵列基板10包含互相相对的主面10A、主面10B及侧面10C。电路基板50包含互相相对的主面50A、主面50B及侧面50C。APD阵列基板10的主面10B与电路基板50的主面50A相对。与APD阵列基板10、电路基板50的各主面平行的面为XY轴平面，与各主面正交的方向为Z轴方向。
电路基板50的侧面50C位于较APD阵列基板10的侧面10C靠XY轴平面方向的外侧。即，在俯视时，电路基板50的面积大于APD阵列基板10的面积。也可将APD阵列基板10的侧面10C及电路基板50的侧面50C设为同一面。该情况下，在俯视时，APD阵列基板10的外缘与电路基板50的外缘一致。
也可在APD阵列基板10的主面10A上配置玻璃基板。玻璃基板与APD阵列基板10通过光学粘结剂而光学连接。玻璃基板也可直接形成于APD阵列基板10上。也可将APD阵列基板10的侧面10C及玻璃基板的侧面设为同一面。该情况下，在俯视时，APD阵列基板10的外缘与玻璃基板的外缘一致。另外，也可将APD阵列基板10的侧面10C、电路基板50的侧面50C及玻璃基板的侧面设为同一面。该情况下，在俯视时，APD阵列基板10的外缘、电路基板50的外缘及玻璃基板的外缘一致。
APD阵列基板10安装于电路基板50。如图2所示，APD阵列基板10与电路基板50通过凸块电极25连接。具体而言，自APD阵列基板10的厚度方向观察，APD阵列基板10如图3所示在配置于电路基板50的中央的安装区域α上由凸块电极25连接。本实施方式中，安装区域α具有矩形状。
电路基板50在安装区域α的周围具有接地线3、阴极线5及阳极线7。接地线3、阴极线5及阳极线7自安装区域α延伸。接地线3连接于下述的接地电极63。阴极线5电连接于安装于安装区域α的APD阵列基板10，用于向APD阵列基板10的电压施加。阳极线7连接于下述的金属层65、66，用于自APD阵列基板10的信号读出。
APD阵列基板10具有以盖革模式动作的多个APD20。多个APD20如图4所示，自APD阵列基板10的厚度方向观察，二维排列于该半导体基板11的光检测区域β。光检测区域β具有矩形状，自APD阵列基板10的厚度方向观察，与电路基板50的安装区域α重叠。
APD阵列基板10具有由化合物半导体构成的N型的半导体基板11。半导体基板11具有形成主面10A的由InP构成的基板12。在基板12上，自主面10A侧向主面10B侧依次形成有由InP构成的缓冲层13、由InGaAsP构成的吸收层14、由InGaAsP构成的电场缓和层15、及由InP构成的倍增层16。吸收层14也可由InGaAs构成。半导体基板11也可由GaAs、InGaAs、AlGaAs、InAlGaAs、CdTe或HgCdTe等形成。
各APD20如图2及图4所示，自APD阵列基板10的厚度方向观察，被绝缘部21包围。各APD20具有通过自主面10B侧向倍增层16掺杂杂质而形成的P型的主动区域22。掺杂的杂质例如为Zn(锌)。绝缘部21例如通过在以湿蚀刻或干蚀刻形成的沟槽内形成聚酰亚胺(polyimide)膜而构成。主动区域22自厚度方向观察形成为圆形状，绝缘部21沿主动区域22的边缘形成为圆环状。绝缘部21在APD阵列基板10的厚度方向上自半导体基板11的主面10B侧到达基板12。
图5是显示本实施方式的变形例所涉及的光检测装置所使用的雪崩光电二极管阵列基板的一部分的图。如图5所示，主动区域22也可自厚度方向观察形成为大致矩形状。此处，所谓大致矩形状，是角带有圆度的矩形状。由此，抑制了电场向主动区域22的角的集中。该情况下，绝缘部21沿大致矩形状的主动区域22的边缘形成为环状。
APD阵列基板10具有绝缘层23及多个电极垫24。绝缘层23在主面10B侧覆盖半导体基板11。电极垫24在每个APD20，在主面10B侧形成于半导体基板11上，与主动区域22相接。电极垫24自绝缘层23露出，通过凸块电极25并连接于电路基板50。
电路基板50如图2所示，通过凸块电极25并在主面50A侧连接于APD阵列基板10。电路基板50具有多个输出单元30。多个输出单元30如图6所示，互相并联连接，形成1个信道40。多个输出单元30的各个与设置于APD阵列基板10的各APD20串联连接。各输出单元30具有互相并联连接的被动淬灭元件31及电容元件32。被动淬灭元件31及电容元件32均与APD20串联连接。
图7是用于说明本实施方式的变形例所涉及的光检测装置所使用的电路结构的图。如图7所示，也可在电路基板50形成多个信道40。该情况下，各信道40通过互相并联连接的多个输出单元30而形成。只要多个信道40的至少一个通过互相并联连接的多个输出单元30形成即可。
电路基板50具有硅基板51、及层叠于硅基板51上的配线层61。如图2所示，硅基板51自主面50B侧向主面50A侧依次具有P+层52、P－层53、P+层54。P+层52通过在P－层53掺杂杂质而设置。P+层54通过在P－层53掺杂杂质而设置。掺杂于P－层53的杂质例如为硼。在硅基板51与配线层61之间，例如设有由利用热氧化的元件分离工序形成的氧化膜层60。P+层54自氧化膜层60露出，与配线层61相接。
配线层61具有绝缘层62、接地电极63、电极垫64、金属层65、66、通孔67、68、69、70、多晶硅层71、72、73、及电介质层74。接地电极63、电极垫64、金属层65、66、通孔67、68、69、70、多晶硅层71、72、73及电介质层74在每个APD20设置。接地电极63、电极垫64及金属层65、66形成于同一层。换言之，接地电极63、电极垫64及金属层65、66在电路基板50的厚度方向上形成为同一高度。
绝缘层62例如由SiO2形成。接地电极63、电极垫64及金属层65、66例如由Al、AlCu或AlSiCu等形成。接地电极63、电极垫64及金属层65、66也可由同一材料形成。通孔67、68、69、70例如由W(钨)形成。电介质层74例如由SiO2或Si3N4形成。
配线层61被绝缘层62覆盖。硅基板51的P+层54连接于自配线层61的绝缘层62向硅基板51侧露出的通孔67。P+层54通过通孔67并连接于接地电极63。接地电极63以在电路基板50的厚度方向上配置该接地电极63的高度，经由绝缘层62相对于电极垫64及金属层65、66而配置。接地电极63不直接连接于电极垫64及金属层65、66。
电极垫64自绝缘层62露出，通过凸块电极25并连接于APD20。电极垫64如图8所示在主面50A侧二维排列。电极垫64通过通孔68并连接于多晶硅层71。多晶硅层71通过通孔69并连接于金属层65。电极垫64以在电路基板50的厚度方向上配置该电极垫64的高度，经由绝缘层62相对于金属层65、66而配置。电极垫64不直接连接于金属层65、66。多晶硅层71包含于第1多晶硅层。
多晶硅层71构成被动淬灭元件31。通过上述的结构，被动淬灭元件31通过凸块电极25、电极垫64及通孔68并串联连接于APD20。即，来自APD20的脉冲信号通过凸块电极25、电极垫64及通孔68并输入至被动淬灭元件31。输入至被动淬灭元件31的上述脉冲信号通过被动淬灭元件31、信道69及金属层65并自信道40输出。
电极垫64以在电路基板50的厚度方向上配置该电极垫64的高度，连接于金属层66。金属层66通过通孔70并连接于多晶硅层72。多晶硅层72层叠于电介质层74之上。电介质层74层叠于多晶硅层73之上。多晶硅层73通过未图示的通孔并连接于金属层65。多晶硅层71及多晶硅层73在电路基板50的厚度方向上形成为同一高度。多晶硅层71及多晶硅层72也可在电路基板50的厚度方向上形成为同一高度。多晶硅层72包含于第3多晶硅层。多晶硅层73包含于第2多晶硅层。
多晶硅层72、电介质层74及多晶硅层73构成电容元件32。通过上述的结构，电容元件32通过凸块电极25、电极垫64及通孔68并串联连接于APD20。即，来自APD20的脉冲信号通过凸块电极25、电极垫64及通孔68并输入至电容元件32的多晶硅层72。对应于对电容元件32的多晶硅层72输入上述脉冲信号，而自电容元件32的多晶硅层73输出脉冲信号。自电容元件32输出的脉冲信号通过未图示的通孔及金属层65并自信道40输出。
被动淬灭元件31及电容元件32均电连接于电极垫64及金属层65。因此，被动淬灭元件31及电容元件32互相并联连接。
接着，参照图9至图11，针对光检测装置1的作用效果进行说明。图9是显示自APD20输出的脉冲信号。如图9所示，来自APD20的脉冲信号26被分成快速脉冲27及再充电脉冲28。快速脉冲27是具有脉冲信号的峰值的脉冲成分。再充电脉冲28是在快速脉冲27被检测之后被检测并具有较快速脉冲27更长的脉冲宽度的成分。
图10显示自输出单元30去除电容元件32，将被动淬灭元件31的电阻值设为参数，自APD20输出的脉冲信号的波形。图10是将纵轴的单位设为电流(A)，将横轴的单位设为时间(s)的整数图。数据a、b、c、d是将具有各不相同的电阻值的被动淬灭元件31设置于输出单元30的情况下的脉冲信号的数据。以数据a、b、c、d的顺序设有具有更高电阻值的被动淬灭元件31。
如图10所示，被动淬灭元件31的电阻值越小，再充电脉冲28的倾斜越陡。再充电脉冲28的倾斜越陡，淬灭所需要的时间越短，无法以APD20检测光的死区时间越短。通过使用电阻值较大的被动淬灭元件31，可实现抑制闭锁电流等的产生的适当的淬灭。但是，电阻值越大，死区时间越增加。
来自连接于该被动淬灭元件31的APD20的脉冲信号的脉冲宽度也根据被动淬灭元件31的电阻值而改变。如图10所示，被动淬灭元件31的电阻值越大，串联连接于被动淬灭元件31的APD20的死区时间越增加。因此，为了兼得适当的淬灭及死区时间的降低，确保光检测灵敏度及光检测时间分辨率，谋求具有最适合的电阻值的被动淬灭元件31的电路设计。
光检测装置1中，具有被动淬灭元件31及电容元件32的多个输出单元30设置于与APD阵列基板10分体的电路基板50。因此，与多个输出单元30配置于APD阵列基板10的情况相比，可更扩大可形成多个输出单元30的空间。因此，多个输出单元30的设计变得容易。
由于多个输出单元30设置于与APD阵列基板10分体的电路基板50，因而可降低产生于APD20的结构与输出单元30间的寄生电容。也可使用与APD阵列基板10不同的制造过程。由于可使用适于APD阵列基板10及电路基板50的各个的制造过程，因而多个输出单元30的设计可变得容易。
图11显示将被动淬灭元件31设为一定值，将电容元件32的静电电容作为参数，自APD20输出的脉冲信号的波形。图11是将纵轴的单位设为电流(A)，将横轴的单位设为时间(s)的单变量图。数据a是自输出单元30去除电容元件32的情况下的脉冲信号的数据。数据b、c、d是将具有各不相同的静电电容的电容元件32设置于输出单元30的情况下的脉冲信号的数据。以数据b、c、d的顺序设有具有更高静电电容的电容元件32。
如图11所示，通过设置电容元件32，快速脉冲27的峰值提高。电容元件32的静电电容越高，快速脉冲27的峰值越大。因此，通过设置电容元件32，来自多个APD20的脉冲信号的时间分辨率提高。快速脉冲27的峰值越大，可越容易检测来自多个APD20的脉冲信号。
光检测装置1中，具有与至少1个APD20串联连接且与被动淬灭元件31并联连接的电容元件32。根据上述的结构，根据使用图11说明的特性，通过电容元件32的静电电容，可提高来自与电容元件32串联连接的APD20的脉冲信号的峰值。因此，易检测来自多个APD20的脉冲信号，可提高光检测时间分辨率。光检测装置1可实现所期望的光检测灵敏度及光检测时间分辨率且对入射光子数进行计数。
在由化合物半导体构成的APD阵列基板10中多个APD20以盖革模式动作的结构中，可通过降低赋予各APD20的电场强度，而抑制噪声的影响。
光检测装置1具备设置于电路基板50上的多晶硅层71、73、设置于多晶硅层73上的电介质层74、及设置于电介质层74上的多晶硅层72。被动淬灭元件31通过多晶硅层71形成，电容元件32通过多晶硅层73、电介质层74及多晶硅层72形成。多晶硅层71在电路基板50的厚度方向上形成为与多晶硅层72或多晶硅层73相同的高度。该情况下，可以简单的制造工序形成上述多个输出单元30。
以上，对本发明的实施方式进行了说明，但本发明并非限定于上述实施方式，在不脱离其主旨的范围内可进行各种变更。
例如，也可取代多晶硅层71，通过金属薄膜形成被动淬灭元件31。也可取代多晶硅层72、73，由2个金属层形成电容元件32。该情况下，电容元件32具有2个平行的金属层夹着电介质层74的结构。
符号的说明
1…光检测装置、10…APD阵列基板、20…APD、30…输出单元、31…被动淬灭元件、32…电容元件、40…信道、50…电路基板、71、72、73…多晶硅层、74…电介质层。

Claims (2)

1.一种光检测装置，其中，
包含：
雪崩光电二极管阵列基板，其二维排列有以盖革模式动作的多个雪崩光电二极管且由化合物半导体构成；及
电路基板，其安装有所述雪崩光电二极管阵列基板，
所述电路基板包含互相并联连接并形成至少1个信道的多个输出单元，
各所述输出单元包含与所述多个雪崩光电二极管的至少一个串联连接的被动淬灭元件、及与所述至少1个雪崩光电二极管串联连接且与所述被动淬灭元件并联连接的电容元件。
2.如权利要求1所述的光检测装置，其中，
所述被动淬灭元件由设置于所述电路基板的第1多晶硅层形成，
所述电容元件由设置于所述电路基板的第2多晶硅层、层叠于所述第2多晶硅层上的电介质层、及层叠于所述电介质层上的第3多晶硅层形成，
所述第1多晶硅层在所述电路基板的厚度方向上形成为与所述第2多晶硅层或所述第3多晶硅层相同的高度。
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US11125616B2 (en) 2021-09-21
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TWI806960B (zh) 2023-07-01
EP3745102A4 (en) 2021-09-08
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US20200370954A1 (en) 2020-11-26
US20210356319A1 (en) 2021-11-18
EP3745102B1 (en) 2023-07-19
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