CN111628061A - 一种氮化镓外延芯片及其制备方法 - Google Patents

一种氮化镓外延芯片及其制备方法 Download PDF

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CN111628061A
CN111628061A CN202010549161.1A CN202010549161A CN111628061A CN 111628061 A CN111628061 A CN 111628061A CN 202010549161 A CN202010549161 A CN 202010549161A CN 111628061 A CN111628061 A CN 111628061A
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gallium nitride
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李东键
叶宏伦
钟健
钟其龙
刘崇志
张本义
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Aksu Silicon Card Semiconductor Technology R & D Co ltd
Xinjiang Can Ke Semiconductor Material Manufacturing Co ltd
Can Long Technology Development Co Ltd
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Xinjiang Can Ke Semiconductor Material Manufacturing Co ltd
Can Long Technology Development Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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Abstract

本发明涉及一种氮化镓外延芯片及其制备方法,其中,氮化镓外延芯片包括衬底、种子层、缓冲层和氮化镓外延层,所述种子层设于衬底上,所述缓冲层设于种子层和氮化镓外延层之间;所述缓冲层包括两组以上的AlxGa1‑xN层,各组AlxGa1‑xN层的x值不相同。本发明在衬底和氮化镓外延层之间增设了种子层和缓冲层,用于改善氮化镓与衬底之间的晶格系数、热膨胀系数等特性的匹配性。具体通过改变衬底与氮化镓外延层之间的铝占比,使铝占比逐渐减少,镓占比逐渐增多,从而提高衬底与氮化镓的晶格系数匹配度,从而保证氮化镓晶格排列错位密度的情况下,能够提高氮化镓的生长厚度。

Description

一种氮化镓外延芯片及其制备方法
技术领域
本发明涉及半导体材料领域,具体涉及一种氮化镓外延芯片及其制备方法。
背景技术
目前III/V族氮化物半导体材主要有GaN(氮化镓)、InGaN(氮化铟镓) 和AlGaN(氮化铝镓)。这类材料被应用在光电器件、半导体激光器件、发光二极体、高电子迁移率电晶体等。氮化物半导体材料的能隙特性,可在1.9到6.2ev之间做连续性调变(非阶段性)。其具有良好的物理,化学稳定性和高饱和电子迁移率,是大功率、高频、发光器件的理想材料。
氮化镓单晶体不存在自然界,没办法从自然界中取得,所以要人工制造。目前的制造方法就是找一种单晶材料当基础,称衬底基板,然后在衬底基板上再生长氮化镓薄膜。因为衬底材料的不同,没办法完美的匹配。热膨胀时易发生龟裂,衬底材料的位错会被带进氮化镓层然后被放大。所以有研究提出了在这中间利用其他材料生长出多一层的氮化铝AlN缓冲层来解决问题。
现有的缓冲层很难生长出1微米以上厚度的氮化镓GaN ,同时得到氮化镓GaN晶格层中原子的排列错位密度(dislocation densities)的质量较差。
发明内容
针对现有技术存在的问题,本发明的目的在于提供一种氮化镓晶体外延片及其制备方法,其能够提高氮化镓外延层的生长厚度以及氮化镓晶格排列错位密度的质量。
为实现上述目的,本发明采用的技术方案是:
一种氮化镓外延芯片,其包括衬底、种子层、缓冲层和氮化镓外延层,所述种子层设于衬底上,所述缓冲层设于种子层和氮化镓外延层之间;所述缓冲层包括两组以上的AlxGa1- xN层,各组AlxGa1-xN层的x值不相同。
所述缓冲层中各组AlxGa1-xN层的x值由种子层向氮化镓外延层方向依次递减。
所述AlxGa1-xN层的x值为0.2-0.85。
所述缓冲层的各组AlxGa1-xN层的厚度由种子层向氮化镓外延层方向依次递减。
所述缓冲层的厚度为200-300nm,而每一组AlxGa1-xN层的厚度为10-100nm。
所述种子层为氮化铝层,其厚度为100-200nm。
一种氮化镓外延芯片的制备方法,其在衬底上依次生长种子层、缓冲层和氮化镓外延层,所述缓冲层包括n组AlxGa1-xN层,具体生长过程如下:
在衬底上生长氮化铝种子层;
在种子层依次生长Alx1Ga1-x2N层、Alx1Ga1-x2N层…、AlxnGa1-xnN层,形成缓冲层;
在缓冲层的AlxnGa1-xnN层上生长氮化镓外延层。
所述种子层、缓冲层和氮化镓外延层的生长方法为氢化物气相外延法、分子束外延法或有机金属化学气相沉积法。
采用上述方案后,本发明在衬底和氮化镓外延层之间增设了种子层和缓冲层,用于改善氮化镓与衬底之间的晶格系数、热膨胀系数等特性的匹配性。具体通过改变衬底与氮化镓外延层之间缓冲层中的AlxGa1-xN层的铝占比,使其铝占比逐渐减少,镓占比逐渐增多,从而提高衬底与氮化镓的晶格系数匹配度,从而保证氮化镓晶格排列错位密度的情况下,能够提高氮化镓的生长厚度。
附图说明
图1为本发明一氮化镓外延芯片结构示意图。
标号说明:
衬底1;种子层2;氮化镓外延层3;缓冲层4;AlxGa1-xN层41。
具体实施方式
如图1所示,本发明揭示了一种氮化镓外延芯片,其可以是高绝缘氮化镓、P型氮化镓或N型氮化镓。该氮化镓外延芯片包括衬底1、种子层2、缓冲层4和氮化镓外延层3,其中,种子层2设于衬底1上,缓冲层4设于种子层2和氮化镓外延层3之间。本发明在衬底1和氮化镓外延层3之间增设了种子层2和缓冲层4,用于改善氮化镓与衬底1之间的晶格系数、热膨胀系数等特性的匹配性。
如图1所示,缓冲层4包括两组以上的AlxGa1-xN层41,各组AlxGa1-xN层41的x值不相同。更进一步地,缓冲层4中各组AlxGa1-xN层41的x值由种子层2向氮化镓外延层3方向依次递减。每一组AlxGa1-xN层41的x值为0.2-0.85。
缓冲层4各组AlxGa1-xN层41的厚度也不相同,具体地,各组AlxGa1-xN层41的厚度由种子层2向氮化镓外延层3方向依次递减。缓冲层4的厚度为200-300nm,而每一组AlxGa1-xN层41的厚度为10-100nm。种子层2为氮化铝层,其厚度为100-200nm。
上述氮化镓外延芯片的制备方法为:在衬底1上依次生长种子层2、缓冲层4和氮化镓外延层3,所述缓冲层4包括n组AlxGa1-xN层41,具体生长过程如下:
在衬底1上生长氮化铝种子层;衬底1可以使用Al2O3衬底、SiC衬底或Si衬底;
在种子层2依次生长Alx1Ga1-x2N层、Alx1Ga1-x2N层…、AlxnGa1-xnN层,形成缓冲层4;
在缓冲层4的AlxnGa1-xnN层上生长氮化镓外延层3,即完成了氮化镓外延芯片的制备。
为详尽本发明内容,以下将列举几个实施例进行详述,这些实施例中,种子层2、缓冲层4和氮化镓外延层3的生长采用有机金属化学气相沉积法M0CVD。
实施例一
该实施例由下至上依次包括衬底1、氮化铝种子层2、缓冲层4和氮化镓外延层3,其中缓冲层4由两组AlxGa1-xN层41构成,分别为Alx1Ga1-x1N层和Alx2Ga1-x2N层。
本实施例中,种子层2的厚度为100nm,Alx1Ga1-x1N层的厚度为90nm、AlxGa1-xN层的厚度为70nm。该实施例中,氮化镓外延层3的生长厚度为1微米,其位错缺陷为5x109/cm2,氮化镓外延层3也没有出现裂纹等其他问题。
实施例二
与实施例一不同的是,本实施例中缓冲层4由三组AlxGa1-xN层41构成,分别为Alx1Ga1- x1N层、Alx2Ga1-x2N层和Alx3Ga1-x3N层。
本实施例中,种子层2的厚度为100nm,Alx1Ga1-x1N层厚度为90nm、Alx2Ga1-x2N层厚度为70nm和Alx3Ga1-x3N层依次是厚度为40nm。该实施例中,氮化镓外延层3的生长厚度为1.15微米,其位错缺陷为5x108/cm2,氮化镓外延层3也没有出现裂纹等其他问题。
实施例三
与实施例一不同的是,本实施例中缓冲层4由四组AlxGa1-xN层41构成,分别为Alx1Ga1- x1N层、Alx2Ga1-x2N层、Alx3Ga1-x3N层和Alx4Ga1-x4N层。本实施例中,种子层2的厚度为100nm,Alx1Ga1-x1N层厚度为90nm、Alx2Ga1-x2N层厚度为70nm、Alx3Ga1-x3N层厚度50nm为和Alx4Ga1-x4N层依次是厚度为40nm。该实施例中,氮化镓外延层3的生长厚度为1.3微米,其位错缺陷为5x108/cm2,氮化镓外延层3也没有出现裂纹等其他问题。
实施例四
与实施例一不同的是,本实施例中缓冲层4由五组AlxGa1-xN层41构成,分别为Alx1Ga1- x1N层、Alx2Ga1-x2N层、Alx3Ga1-x3N层和Alx4Ga1-x4N层、Alx4Ga1-x4N层和Alx5Ga1-x5N层。本实施例中,种子层2的厚度为90nm,Alx1Ga1-x1N层厚度为80nm、Alx2Ga1-x2N层厚度为60nm、Alx3Ga1-x3N层50nm、Alx4Ga1-x4N层厚度为40nm和Alx5Ga1-x5N层厚度为30nm。该实施例中,氮化镓外延层3的生长厚度为1.15微米,其位错缺陷为5x108/cm2,氮化镓外延层3也没有出现裂纹等其他问题。
将上述四个实施例与现有技术(对比例1和对比例2)进行对比,对比结果如表1所示。其中,对比例1和2为现有的氮化镓外延芯片,其在衬底1和氮化镓外延层3之间仅设置了种子层2,通过该对比例1和2可知,当氮化镓外延层3的生长厚度为0.05μm时,其位错缺陷密度为5x1010/cm2;当氮化镓外延层3的生长厚度增加至0.15μm时,氮化镓外延层3混出现裂纹。
Figure 516567DEST_PATH_IMAGE002
表1
从上述表1可以看出,本发明的氮化镓外延芯片的氮化镓外延层3生长厚度在1μm以上,且位错缺陷密度在5x109/cm2以上。相交于现有技术,本发明的氮化镓外延层3生长厚度以及位错缺陷密度都得到了有效提升。
以上所述,仅是本发明实施例而已,并非对本发明的技术范围作任何限制,故凡是依据本发明的技术实质对以上实施例所作的任何细微修改、等同变化与修饰,均仍属于本发明技术方案的范围内。

Claims (8)

1.一种氮化镓外延芯片,其特征在于:包括衬底、种子层、缓冲层和氮化镓外延层,所述种子层设于衬底上,所述缓冲层设于种子层和氮化镓外延层之间;所述缓冲层包括两组以上的AlxGa1-xN层,各组AlxGa1-xN层的x值不相同。
2.根据权利要求1所述的一种氮化镓外延芯片,其特征在于:所述缓冲层中各组AlxGa1- xN层的x值由种子层向氮化镓外延层方向依次递减。
3.根据权利要求1或2所述的一种氮化镓外延芯片,其特征在于:所述AlxGa1-xN层的x值为0.2-0.85。
4.根据权利要求1所述的一种氮化镓外延芯片,其特征在于:所述缓冲层的各组AlxGa1- xN层的厚度由种子层向氮化镓外延层方向依次递减。
5.根据权利要求1所述的一种氮化镓外延芯片,其特征在于:所述缓冲层的厚度为200-300nm,而每一组AlxGa1-xN层的厚度为10-100nm。
6.根据权利要求1所述的一种氮化镓外延芯片,其特征在于:所述种子层为氮化铝层,其厚度为100-200nm。
7.一种氮化镓外延芯片的制备方法,其特征在于:衬底上依次生长种子层、缓冲层和氮化镓外延层,所述缓冲层包括n组AlxGa1-xN层,具体生长过程如下:
在衬底上生长氮化铝种子层;
在种子层依次生长Alx1Ga1-x2N层、Alx1Ga1-x2N层…、AlxnGa1-xnN层,形成缓冲层;
在缓冲层的AlxnGa1-xnN层上生长氮化镓外延层。
8.根据权利要求7所述的一种氮化镓外延芯片的制备方法,其特征在于:所述种子层、缓冲层和氮化镓外延层的生长方法为氢化物气相外延法、分子束外延法或有机金属化学气相沉积法。
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