CN111627990B - Method for preparing top gate type field effect transistor by utilizing thermal evaporation aluminum seed layer - Google Patents
Method for preparing top gate type field effect transistor by utilizing thermal evaporation aluminum seed layer Download PDFInfo
- Publication number
- CN111627990B CN111627990B CN202010376603.7A CN202010376603A CN111627990B CN 111627990 B CN111627990 B CN 111627990B CN 202010376603 A CN202010376603 A CN 202010376603A CN 111627990 B CN111627990 B CN 111627990B
- Authority
- CN
- China
- Prior art keywords
- silicon wafer
- dimensional material
- thermal evaporation
- seed layer
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000002207 thermal evaporation Methods 0.000 title claims abstract description 30
- 230000005669 field effect Effects 0.000 title claims abstract description 25
- 229910052782 aluminium Inorganic materials 0.000 title claims abstract description 20
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 title claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 44
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 42
- 239000010703 silicon Substances 0.000 claims description 42
- 229910052710 silicon Inorganic materials 0.000 claims description 41
- 239000010410 layer Substances 0.000 claims description 33
- 238000001704 evaporation Methods 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 238000000231 atomic layer deposition Methods 0.000 claims description 21
- 239000011248 coating agent Substances 0.000 claims description 19
- 238000000576 coating method Methods 0.000 claims description 19
- 230000008020 evaporation Effects 0.000 claims description 13
- 239000002135 nanosheet Substances 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 12
- 238000006243 chemical reaction Methods 0.000 claims description 10
- 238000010894 electron beam technology Methods 0.000 claims description 9
- 238000001035 drying Methods 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 239000012153 distilled water Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 239000002356 single layer Substances 0.000 claims description 5
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 claims description 5
- 238000004806 packaging method and process Methods 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 239000012467 final product Substances 0.000 claims description 2
- 230000004907 flux Effects 0.000 claims description 2
- 239000002064 nanoplatelet Substances 0.000 claims description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 41
- 229910021389 graphene Inorganic materials 0.000 abstract description 41
- 230000007547 defect Effects 0.000 abstract description 6
- 229910018072 Al 2 O 3 Inorganic materials 0.000 abstract description 5
- 235000012431 wafers Nutrition 0.000 description 30
- 238000012512 characterization method Methods 0.000 description 12
- 238000001069 Raman spectroscopy Methods 0.000 description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 9
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- HITXEXPSQXNMAN-UHFFFAOYSA-N bis(tellanylidene)molybdenum Chemical compound [Te]=[Mo]=[Te] HITXEXPSQXNMAN-UHFFFAOYSA-N 0.000 description 6
- 239000010408 film Substances 0.000 description 6
- 239000007888 film coating Substances 0.000 description 4
- 238000009501 film coating Methods 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910000449 hafnium oxide Inorganic materials 0.000 description 4
- 238000002203 pretreatment Methods 0.000 description 4
- 239000002390 adhesive tape Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- -1 transition metal chalcogenides Chemical class 0.000 description 3
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000000635 electron micrograph Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910052723 transition metal Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000005411 Van der Waals force Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 230000007847 structural defect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000009210 therapy by ultrasound Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention discloses a method for preparing a top gate type field effect transistor by utilizing a thermal evaporation aluminum seed layer. The high dielectric constant gate dielectric is Al 2 O 3 Gate dielectric or HfO 2 A gate dielectric. The invention not only realizes high-quality compact Al on graphene 2 O 3 The dielectric layer grows without significant defects in the two-dimensional material.
Description
Technical Field
The invention relates to a top gate type field effect transistor, in particular to a method for preparing the top gate type field effect transistor by utilizing a thermal evaporation aluminum seed layer.
Background
Since graphene was found in 2004, two-dimensional materials have attracted widespread attention in the scientific community. The materials have wide application prospects in the aspects of logic devices, photoelectric detectors, flexible touch screens, radio frequency devices and the like. However, most novel physical phenomena and unique two-dimensional material characteristics are discovered based on the back gate structure. This is due to the lack of bulk on the surface of these van der Waals forces bonded layered two-dimensional materialsDangling bonds, high dielectric constant gate dielectrics such as alumina (Al 2 O 3 ) Hafnium oxide (HfO) 2 ) It is difficult to integrate on the surface of these two-dimensional materials, and thus it is difficult to fabricate top gate two-dimensional material field effect transistors (Field effect transistor, FETs). However, in order to apply the two-dimensional material to a practical thin film transistor circuit, a two-dimensional material device based on a top gate structure is very necessary. First, the back gate field effect transistor (Field effect transistor, FET) is not compatible with integrated circuit technology (Complementary metal oxide semiconductor, CMOS) because it cannot adjust the electrical characteristics of each device individually as a top gate field effect transistor. Second, in order to reduce the operating voltage and further reduce the device size, the gate dielectric needs to be thinner and have a higher dielectric constant. Third, for low power devices, coulomb scattering in the graphene channel can be effectively suppressed by using the gate coupling effect of the top gate, thereby improving carrier mobility and maximum saturation current.
As the most mature industrialized gate dielectric preparation technology at present, atomic layer deposition (Atomic layer deposition, ALD), excellent sample surface flatness and lower growth temperature are standard methods for preparing gate dielectric in CMOS process due to its precise thickness control. However, for most conventional two-dimensional materials, such as graphene and transition metal chalcogenides, it is difficult to grow gate dielectrics by this standard process. In order to solve the problem that the surface of the two-dimensional material lacks intrinsic dangling bonds, a gate dielectric is uniformly grown on the surface of the two-dimensional material, and various pretreatment methods are adopted by the former to form dangling bonds on the surface of the two-dimensional material. For example, the method of oxidizing the sample surface with ultraviolet ozone, bombarding the sample surface with plasma, spin-coating organic polymer on the sample surface or thermally evaporating ultrathin metal film as seed layer, etc. But these methods not only add technical complexity but also damage the lattice integrity of the two-dimensional material and reduce the overall gate capacitance of the device.
Disclosure of Invention
The invention aims to solve the technical problem that the surface pretreatment of the existing two-dimensional material (such as graphene, transition metal sulfide and the like) before integrating a high dielectric constant gate medium can cause the defect of lattice defects, and provides a method for preparing a top gate type field effect transistor by utilizing a thermal evaporation aluminum seed layer, wherein the surface pretreatment can not cause obvious structural damage or defect of the two-dimensional material.
In order to solve the technical problems, the invention provides a method for preparing a top gate type field effect transistor by utilizing a thermal evaporation aluminum seed layer, which comprises the steps of thermally evaporating an ultrathin metal medium to the surface of a two-dimensional material, drying the surface of the two-dimensional material, naturally oxidizing the surface of the two-dimensional material into the seed layer in a drying box, and growing a high dielectric constant gate medium on the surface of the two-dimensional material by utilizing an atomic layer deposition method.
The surface pretreatment method performed before ALD growth of the high dielectric constant gate dielectric comprises the following steps: the method comprises the steps of firstly thermally evaporating an ultrathin metal medium to the surface of a two-dimensional material, then placing the ultrathin metal medium into a drying oven to be naturally oxidized into a seed layer, and then preparing the top gate two-dimensional material FET through a standard micro-nano manufacturing process. The surface pretreatment method has three advantages: (1) By using a thermally evaporated ultra-thin metal medium as a seed layer, nucleation sites can be provided on the surface of the two-dimensional material, thereby effectively chemisorbing precursors in the ALD process. (2) The thermal evaporation ultrathin metal is arranged on the surface of a two-dimensional material, and belongs to a physical process. Thus, no significant structural damage or defects occur in the two-dimensional material compared to other chemical methods (e.g., ultraviolet ozone or plasma pretreatment). (3) After thermally evaporating the ultra-thin metal medium, the ultra-thin metal layer will rapidly oxidize to form amorphous Al 2 O 3 Or hafnium oxide (HfO) 2 ) And therefore does not significantly reduce top gate capacitance as does polymer coating pretreatment.
The high-dielectric-constant gate dielectric is aluminum oxide (Al) 2 O 3 ) Gate dielectric or hafnium oxide (HfO 2 ) A gate dielectric.
The method for preparing the top gate type field effect transistor by utilizing the thermal evaporation aluminum seed layer comprises the following steps:
1) Peeling the two-dimensional material crystal onto a silicon wafer by using a micromechanical peeling method, so that a single-layer two-dimensional material nano-sheet is attached to the silicon wafer;
2) Forming a source electrode pattern and a drain electrode pattern on a silicon wafer attached with a single-layer two-dimensional material nano sheet by using an electron beam exposure method, and preparing a source electrode and a drain electrode by using a thermal evaporation coating and stripping process;
3) Evaporating ultrathin metal Al on the surface of the two-dimensional material nanosheet between the source electrode and the drain electrode by using a thermal evaporation coating machine, and after the evaporation is finished, putting the silicon wafer into an oxidation box for oxidation to enable an ultrathin metal Al medium obtained by thermal evaporation to be completely oxidized;
4) Growing Al on the surface of the ultrathin metal Al medium obtained in the step 3) by utilizing an atomic layer deposition method 2 O 3 A gate dielectric;
5) In Al by electron beam exposure 2 O 3 Forming a gate electrode pattern on the gate dielectric, and preparing a gate electrode by utilizing an electron beam coating;
6) And packaging to obtain the final product.
The step 3) comprises the following steps:
(1) Placing the silicon wafer with the prepared source electrode and drain electrode into an evaporation cavity of a thermal evaporation coating machine, and vacuumizing to ensure that the pressure in the evaporation cavity is only 110 -5 Pa；
(2) Starting a thermal evaporation coating machine to plate ultrathin metal medium Al on the surface of a two-dimensional material of a silicon wafer, wherein the coating parameters are as follows: al deposition thickness 2 nm, evaporation rate: 0.3 a/s;
(3) And after the film coating is finished, taking out the silicon wafer, and putting the silicon wafer into a drying oven with the temperature of 25 ℃ and the relative humidity of 20% for 30 minutes for oxidation, so that the ultrathin metal aluminum obtained by thermal evaporation on the silicon wafer is completely oxidized.
The atomic layer deposition method comprises the following steps:
(1) Placing the silicon wafer attached with the two-dimensional material nanosheets into a reaction cavity, and introducing nitrogen with the purity of 99.9997% and the airflow flux of 40 sccm for 20 minutes;
(2) Setting the heating time to be 25-35 min, and heating the reaction cavity to 148-152 ℃;
(3) Introducing into the reaction chamberTrimethylaluminum and distilled water, wherein the charging time of trimethylaluminum is 8s-12s, the charging time of distilled water is 8s-12s, the switching valve time is 0.015s, and the period is one period, and 273 periods are carried out until Al with the thickness of 30nm grows on a silicon wafer attached with two-dimensional material nano-sheets 2 O 3 A gate dielectric;
(4) To Al (stand by) 2 O 3 And (5) after the growth of the gate dielectric is finished, taking out.
In order to reduce parasitic capacitance and enhance gate control characteristics, the gate electrode completely covers the conductive channel of the two-dimensional material nanoplatelets.
The applicant takes graphene as an example, and confirms the effectiveness of the method:
as shown in FIG. 3, the invention not only realizes high-quality dense Al on graphene by thermally evaporating an alumina seed layer on graphene before ALD growth 2 O 3 The surface roughness (Ra) of the graphene grown by ALD directly, grown with the gate dielectric, was reduced from 2.8 nm to 0.32 nm.
As shown in FIG. 4, the leakage current can be reduced from 10 after the treatment of the Al seed layer -3 A is reduced to 10 -11 A, 8 orders of magnitude lower, and Al obtained by the pretreatment method of the invention is also proved 2 O 3 Excellent insulating properties of the gate dielectric.
As shown in fig. 5, the raman characterization and atomic force characterization of graphene in the thermal evaporation Al seed layer treatment process show that no raman characteristic defect peak (D peak) appears in the whole process, and the atomic force scanning image of the device is very clean, which indicates that the method has no obvious damage to graphene.
As shown in fig. 6, the basic characterization and transport properties of the graphene top-gate devices prepared by the present invention indicate that the top-gate graphene devices have high mobility (cm) 2 V -1 s -1 ) And a high transconductance (-117 [ mu ] S), and the Al produced 2 O 3 The relative dielectric constant of the gate dielectric is 6.5, and the tunneling current (leakage current) is less than 1.6 pA/mu m 2 。
As shown in fig. 7 and 8, the method of the invention is also applicable to two-dimensional material molybdenum telluride (MoTe 2 ) And Black Phosphorus (BP), it was found by atomic force characterization that after pretreatment with a thermally evaporated aluminum seed layer, molybdenum telluride (MoTe) 2 ) And formation of dense Al on Black Phosphorus (BP) 2 O 3 A film. These results indicate that high quality Al can be achieved by functionalizing the two-dimensional material surface with a thermally evaporated aluminum seed layer 2 O 3 And growing a gate dielectric, thereby obtaining the high-performance top gate field effect transistor.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of the preparation of a top gate field effect transistor by using a thermal evaporation Al seed layer.
Fig. 2 is a schematic cross-sectional view of a top gate graphene field effect transistor prepared in accordance with the present invention. Wherein S represents a source electrode, D represents a drain electrode, G represents a top gate electrode,V TG representing the top gate voltage applied across the device,V BG representing the back gate voltage. Si and SiO 2 Respectively represent silicon and silicon dioxide, i.e. silicon wafers, wherein the oxide layer (SiO 2 ) The thickness was 300 a nm a. Graphene stands for Graphene, and Al oxide stands for an amorphous (oxidized) Al seed layer that has a natural oxidation after thermal evaporation.
Fig. 3 is a comparison of atomic force scans and electron microscopy images of graphene grown directly by ALD and graphene grown by ALD after treatment with an Al seed layer, wherein (a) and (c) are atomic force scans and electron microscopy images of graphene grown directly by ALD; (b) And (d) atomic force scan and electron microscope images of graphene grown by ALD after Al seed layer treatment, wherein Ra represents the plane roughness of the sample surface.
Fig. 4 is a comparison of leakage current of a Metal-insulator-semiconductor (MIS) structure directly grown by ALD with leakage current of a graphene MIS structure grown by ALD after Al seed layer treatment, wherein,I G represents a leakage current and is referred to as,V TG representing the top gate voltage.
Fig. 5 is a raman and atomic force characterization of graphene in a thermal evaporation Al seed layer treatment process, where a is a raman characterization, b is an atomic force characterization, G and 2D are both raman characteristic peaks of graphene, and D is a structural defect raman characteristic peak of graphene.
Fig. 6 is a basic representation and transport characteristic diagram of a graphene top gate field effect transistor, where a is a transfer characteristic diagram, b is a hysteresis scan diagram, a is an optical representation of the graphene top gate device, S represents the source, D represents the drain, TG represents the top gate electrode,I DS representing the source-drain current and,V DS representing the source-drain voltage and,V G representing the gate voltage of the semiconductor device,V TG representing the top gate voltage of the transistor,g m representing the transconductance.
FIG. 7 is a graph of molybdenum telluride (MoTe) grown by ALD after Al seed layer treatment 2 ) Atomic force scans and raman characterizations, where a is the atomic force scan and b is the raman characterizations.
Fig. 8 is an atomic force scan and raman characterization of Black Phosphorus (BP) grown by ALD after Al seed layer treatment, where a is the atomic force scan and b is the raman characterization.
Detailed Description
The invention is further described below in connection with specific preferred embodiments, but it is not intended to limit the scope of the invention.
For convenience of description, the relative positional relationship of the components, such as: the descriptions of the upper, lower, left, right, etc. are described according to the layout directions of the drawings in the specification, and do not limit the structure of the present patent.
As shown in fig. 1 and 2, an embodiment of a method for fabricating a top gate field effect transistor by thermally evaporating an aluminum seed layer according to the present invention includes the following steps:
1. preparing graphene by a micromechanical stripping method: (1) Bulk graphene crystals (model: smart Elements) were placed on a strip tape (model: scotch tape). (2) And (3) stripping the bulk graphene to a thin layer by repeatedly doubling the adhesive tape, and attaching the bulk graphene to the whole adhesive tape. (3) Tape was attached to the wafer (doping type: P-type; oxide thickness: 300 a nm). After standing for one minute, the adhesive tape is peeled off, and the monolayer (or thin layer) graphene nano-sheet can be obtained on the silicon wafer.
2. And processing the source electrode and the drain electrode of the field effect transistor by a microelectronic process:
electron beam exposure yields the desired electrode pattern: (1) And (3) positioning the position of the graphene nano sheet on the silicon wafer by using an optical microscope (model: olympus DX 51) with a coordinate displacement table, and recording the horizontal coordinate value and the vertical coordinate value. (2) Spin-coating electron beam exposure paste (model: PMMA 950K) onto a silicon wafer substrate with parameters of forward rotation 600r (or 500r, 550r, 600r, 650r, 700 r) for 10s (or 8s, 9s, 10s, 11s, 12 s), backward rotation 4000r (or 3800r, 3900r, 4000r, 4100r, 4200 r) for 40s (or 38s, 39s, 40s, 41s, 42 s). And heating for 120s (or 110s, 115s, 120s, 125s, 130 s) at 170deg.C (or 165 deg.C, 170 deg.C, 175 deg.C) on a drying table. (3) After the coordinates are determined, the desired source and drain electrode patterns (parameters are high voltage: 10 kV, aperture size: 30 μm, beam current: 217 pA) are exposed. (4) After the exposure, the silicon wafer was taken out, and left to stand in the developer for 30s (or 28s, 29s, 30s, 31s, 32 s), and in the fixer for 30s (or 28s, 29s, 30s, 31s, 32 s). And finally, taking out the silicon wafer, and flushing the residual liquid on the surface of the sample by using an air gun to obtain the required source electrode pattern and drain electrode pattern.
(II) preparing a metal electrode by thermal evaporation coating: (1) Placing the silicon wafer subjected to electron beam exposure into an evaporation cavity of a film plating machine, and vacuumizing the evaporation cavity by using a mechanical pump and a molecular pump for more than 2 hours to ensure that the pressure in the evaporation cavity is only 110% -5 Pa. (2) According to the metal (purity is 99.995%) to be plated, the preparation method is well adjustedA corresponding crucible. (3) In this experiment, titanium (Ti) was plated first and gold (Au) was plated later. Setting coating parameters (deposition thickness: ti: 4nm, au:50 nm, evaporation rate: ti: 0.5A/s, au: 1.5A/s), opening the baffle, and automatically starting coating by the coating machine. (4) And after the film coating is finished, breaking the vacuum of the thermal evaporation film coating machine, and taking out the silicon wafer to finish the film coating operation.
And (III) stripping process: (1) Placing the plated silicon wafer into a hot acetone inner cover, and placing the glass plate, preventing acetone from volatilizing, standing for 5min (or 4min,5min,6min,7 min) at 65deg.C (or 55deg.C, 60deg.C, 65deg.C, 70deg.C). (2) When bubbles appear on the gold film on the silicon wafer, the beaker filled with hot acetone and the silicon wafer is placed in an ultrasonic cleaner for ultrasonic treatment, and the silicon wafer is taken out after lasting for about 1 second. (3) And (3) placing the peeled silicon wafer into isopropanol solution for cleaning for about 1 minute, taking out, and removing the residual liquid on the surface by using an air gun to obtain the source electrode and the drain electrode of the graphene field effect transistor at the two ends of the silicon wafer.
3. Preparing an ultrathin metal aluminum seed layer: and (1) evaporating Al on the surface of the silicon wafer by using a thermal evaporation coating machine. The specific operation is as in the second point (II) in the second step, and the parameters used here are Al:2 nm, evaporation rate: 0.3 And a/s. (2) After the thermal evaporation operation, the silicon wafer was put into an oxidation tank for 30 minutes to oxidize the ultrathin metal aluminum obtained by thermal evaporation (the environment of the drying tank: temperature: 25 ℃ C.; relative humidity: 20%).
4. Atomic layer deposition for preparing high quality Al 2 O 3 Gate dielectric: (1) The silicon wafer was placed in the reaction chamber, and purged with nitrogen (purity: 99.9997%, gas flow: 40 sccm) for 20 minutes. (2) The reaction chamber was heated to 150 ℃ (or 148 ℃,149 ℃,150 ℃,151 ℃,152 ℃) and the heating period was set to 30min (or 25min,30min,35 min). (3) Introducing trimethylaluminum and distilled water into the reaction chamber, setting the introducing time of trimethylaluminum to be 10s (or 8s, 9s, 10s, 11s, 12 s), the introducing time of distilled water to be 10s (or 8s, 9s, 10s, 11s, 12 s), and switching the valve time to be 0.015s, wherein the reaction is carried out for 273 cycles (273 weeks)Phase corresponds to the grown Al 2 O 3 The gate dielectric thickness is 30 nm). (4) To Al (stand by) 2 O 3 And after the growth of the gate dielectric is finished, taking out the silicon wafer (attached with graphene).
5. Preparing a graphene top gate electrode: and repeating the second step to obtain the graphene top gate electrode. Here, in order to reduce parasitic capacitance and enhance gate control characteristics, the top gate electrode should completely cover the graphene conductive channel. But the leakage of the device is prevented by avoiding overlapping with the source electrode and the drain electrode. Here again, the top gate electrode was first plated with 4nm Ti and then 50nm Au.
6. Packaging the top gate graphene field effect transistor: (1) And fixing the silicon chip attached with the graphene nano sheet on a pin chip carrier by utilizing conductive silver paste (model: R-150-0 XX-1X-0X-0000). (2) And packaging the black phosphorus top gate device prepared in the previous step into a pin chip carrier by using a wire-bonding machine (model: west Bond). Here, we use the encapsulation parameters: bonding force: 30g/N (or 28g/N,29g/N,30g/N,31g/N,32 g/N), bond strength (relative value): 60 (or 58, 59, 60, 61, 62), bonding time: 25. mus (or 23 mus, 24 mus, 25 mus, 26 mus, 27 mus), bond point length: 19. ym (or 18 ym, 19 ym, 20 ym).
The above embodiment is to grow high quality Al on graphene 2 O 3 The gate dielectric is illustrated by way of example, but the method is not limited to graphene, and the method is also applicable to other two-dimensional materials, and by atomic force characterization, the method can be used for pre-treating a thermally evaporated aluminum seed layer, and can be used for preparing a film of molybdenum telluride (MoTe 2 ) And formation of dense Al on Black Phosphorus (BP) 2 O 3 A film. These results indicate that high quality Al can be achieved by functionalizing the two-dimensional material surface with a thermally evaporated aluminum seed layer 2 O 3 And growing a gate dielectric, thereby obtaining the high-performance top gate type field effect transistor.
The foregoing description is not intended to limit the invention in any way, but is not intended to limit the invention to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Claims (3)
1. A method for preparing a top gate type field effect transistor by utilizing a thermal evaporation aluminum seed layer is characterized by comprising the following steps:
1) Peeling the two-dimensional material crystal onto a silicon wafer by using a micromechanical peeling method, so that a single-layer two-dimensional material nano-sheet is attached to the silicon wafer;
2) Forming a source electrode pattern and a drain electrode pattern on a silicon wafer attached with a single-layer two-dimensional material nano sheet by using an electron beam exposure method, and preparing a source electrode and a drain electrode by using a thermal evaporation coating and stripping process;
3) Evaporating ultrathin metal aluminum to the surface of the two-dimensional material nanosheet between the source electrode and the drain electrode by using a thermal evaporation coating machine, and after the evaporation is finished, naturally oxidizing a silicon wafer in a drying oven to completely oxidize an ultrathin metal Al medium obtained by thermal evaporation, wherein the method specifically comprises the following steps of: (1) Placing the silicon wafer with the prepared source electrode and drain electrode into an evaporation cavity of a thermal evaporation coating machine, and vacuumizing to ensure that the pressure in the evaporation cavity is only 110 -5 Pa; (2) Starting a thermal evaporation coating machine to plate ultrathin metal medium Al on the surface of a two-dimensional material of a silicon wafer, wherein the coating parameters are as follows: al deposition thickness 2 nm, evaporation rate: 0.3 A/s; (3) After coating, taking out the silicon wafer, and putting the silicon wafer into a drying oven with the temperature of 25 ℃ and the relative humidity of 20% for 30 minutes for oxidation, so that the ultrathin metal aluminum obtained by thermal evaporation on the silicon wafer is completely oxidized;
4) Growing Al on the surface of the ultrathin metal Al medium obtained in the step 3) by utilizing an atomic layer deposition method 2 O 3 A gate dielectric;
5) In Al by electron beam exposure 2 O 3 Forming a gate electrode pattern on the gate dielectric, and preparing a gate electrode by utilizing an electron beam coating;
6) And packaging to obtain the final product.
2. The method of fabricating a top gate field effect transistor using a thermally evaporated aluminum seed layer of claim 1, wherein the atomic layer deposition process comprises:
(1) Placing the silicon wafer attached with the two-dimensional material nanosheets into a reaction cavity, and introducing nitrogen with the purity of 99.9997% and the airflow flux of 40 sccm for 20 minutes;
(2) Setting the heating time to be 25-35 min, and heating the reaction cavity to 148-152 ℃;
(3) Introducing trimethylaluminum and distilled water into the reaction cavity, setting the introducing time of trimethylaluminum to be 8s-12s, the introducing time of distilled water to be 8s-12s, and switching the valve to be 0.015s, and taking the time as one period, and carrying out 273 periods until Al with the thickness of 30nm grows on the silicon chip attached with the two-dimensional material nano-sheet 2 O 3 A gate dielectric;
(4) To Al (stand by) 2 O 3 And (5) after the growth of the gate dielectric is finished, taking out.
3. The method of fabricating a top gate field effect transistor using a thermally evaporated aluminum seed layer of claim 1, wherein said gate electrode completely covers the conductive channel of said two-dimensional material nanoplatelets.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010376603.7A CN111627990B (en) | 2020-05-07 | 2020-05-07 | Method for preparing top gate type field effect transistor by utilizing thermal evaporation aluminum seed layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010376603.7A CN111627990B (en) | 2020-05-07 | 2020-05-07 | Method for preparing top gate type field effect transistor by utilizing thermal evaporation aluminum seed layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111627990A CN111627990A (en) | 2020-09-04 |
| CN111627990B true CN111627990B (en) | 2023-08-08 |
Family
ID=72259011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010376603.7A Active CN111627990B (en) | 2020-05-07 | 2020-05-07 | Method for preparing top gate type field effect transistor by utilizing thermal evaporation aluminum seed layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111627990B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103311276A (en) * | 2013-06-07 | 2013-09-18 | 中国科学院微电子研究所 | Self-aligned graphene field effect transistor and manufacturing method thereof |
| CN103840003A (en) * | 2014-02-21 | 2014-06-04 | 西安电子科技大学 | Double-gate graphene transistor with aluminum oxide as gate dielectric and manufacturing method thereof |
| CN103903973A (en) * | 2014-03-05 | 2014-07-02 | 复旦大学 | Method for developing high K medium on graphene through spin coating of liquid metal seed layer |
| CN106374006A (en) * | 2016-10-13 | 2017-02-01 | 中国科学院上海技术物理研究所 | Room-temperature adjustable sub-Terahertz wave detector and preparation method |
| CN106546633A (en) * | 2016-12-07 | 2017-03-29 | 成都聚智工业设计有限公司 | Enhanced gas sensor of a kind of nickel oxide nanoparticle and preparation method thereof |
| CN110042365A (en) * | 2019-03-04 | 2019-07-23 | 中国科学院物理研究所 | A kind of Atomic layer deposition method in two-dimensional material surface growth aluminium oxide |
| CN110300475A (en) * | 2019-07-15 | 2019-10-01 | 中国人民解放军国防科技大学 | Electric heating radiation luminous array device and its preparing method and use |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050242387A1 (en) * | 2004-04-29 | 2005-11-03 | Micron Technology, Inc. | Flash memory device having a graded composition, high dielectric constant gate insulator |
| US8198707B2 (en) * | 2009-01-22 | 2012-06-12 | Board Of Regents, The University Of Texas System | Establishing a uniformly thin dielectric layer on graphene in a semiconductor device without affecting the properties of graphene |
| US8106383B2 (en) * | 2009-11-13 | 2012-01-31 | International Business Machines Corporation | Self-aligned graphene transistor |
-
2020
- 2020-05-07 CN CN202010376603.7A patent/CN111627990B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103311276A (en) * | 2013-06-07 | 2013-09-18 | 中国科学院微电子研究所 | Self-aligned graphene field effect transistor and manufacturing method thereof |
| CN103840003A (en) * | 2014-02-21 | 2014-06-04 | 西安电子科技大学 | Double-gate graphene transistor with aluminum oxide as gate dielectric and manufacturing method thereof |
| CN103903973A (en) * | 2014-03-05 | 2014-07-02 | 复旦大学 | Method for developing high K medium on graphene through spin coating of liquid metal seed layer |
| CN106374006A (en) * | 2016-10-13 | 2017-02-01 | 中国科学院上海技术物理研究所 | Room-temperature adjustable sub-Terahertz wave detector and preparation method |
| CN106546633A (en) * | 2016-12-07 | 2017-03-29 | 成都聚智工业设计有限公司 | Enhanced gas sensor of a kind of nickel oxide nanoparticle and preparation method thereof |
| CN110042365A (en) * | 2019-03-04 | 2019-07-23 | 中国科学院物理研究所 | A kind of Atomic layer deposition method in two-dimensional material surface growth aluminium oxide |
| CN110300475A (en) * | 2019-07-15 | 2019-10-01 | 中国人民解放军国防科技大学 | Electric heating radiation luminous array device and its preparing method and use |
Non-Patent Citations (1)
| Title |
|---|
| 吴殿仲.基于二维黑磷和硫化钼半导体纳米材料的场效应晶体管.工程科技Ⅰ辑.2020,(第undefined期),正文第52、67-68页，图4-4. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111627990A (en) | 2020-09-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Okur et al. | High-mobility pentacene phototransistor with nanostructured SiO2 gate dielectric synthesized by sol–gel method | |
| Liu et al. | Atomic layer deposited 2D MoS 2 atomic crystals: From material to circuit | |
| CN111987169B (en) | Transistor based on two-dimensional gallium oxide thin film and preparation method | |
| CN112349593B (en) | Two-dimensional thin film transistor with graphene as source and drain electrodes and preparation method | |
| CN109585567A (en) | High-performance indium gallium zinc oxygroup double-layer structure thin film transistor (TFT) and preparation method thereof | |
| CN114242780A (en) | Indium tin oxide vertical ring grid field effect transistor and preparation method thereof | |
| CN108987483B (en) | MoTe2Field effect transistor and preparation method and application thereof | |
| CN111627990B (en) | Method for preparing top gate type field effect transistor by utilizing thermal evaporation aluminum seed layer | |
| WO2024066206A1 (en) | Preparation method for and use of two-dimensional double-layer tungsten sulfide homojunction | |
| CN110634958B (en) | Semiconductor thin film field effect transistor made of unstable two-dimensional material and preparation method thereof | |
| CN113782593A (en) | Bismuth selenide oxide in-situ thermal oxide top gate field effect transistor and preparation method thereof | |
| WO2023115653A1 (en) | Fully transparent thin-film transistor based on indium tin oxide, and preparation method therefor | |
| CN111987153B (en) | Ultra-low power consumption field effect transistor and preparation method thereof | |
| CN111627991A (en) | Method for preparing top gate type field effect transistor based on black phosphorus and field effect transistor | |
| CN115207127A (en) | Multi-electric-conduction-state ferroelectric transistor device based on interlayer slippage and preparation method | |
| CN114920213A (en) | Preparation method of tungsten diselenide | |
| CN109301067B (en) | Hexamethyldisilazane modified organic thin film transistor and preparation method thereof | |
| KR20180096098A (en) | Method for manufacturing spin coating based high quality solution-processed boron nitride thin film and its application in electronic devices | |
| CN111293085A (en) | Three-dimensional CMOS (complementary metal oxide semiconductor) based on two-dimensional transition metal chalcogenide and tellurium and preparation method thereof | |
| CN105742188B (en) | Method for preparing p-type oxide thin film material by polyol reduction technology | |
| CN115142134B (en) | Method for preparing large-size two-dimensional crystalline gallium nitride by utilizing liquid gallium metal | |
| CN110890280A (en) | Method for preparing oxide semiconductor Schottky diode by using palladium/palladium oxide double-layer Schottky electrode | |
| CN117438376B (en) | Complementary field effect transistor based on two-dimensional material and preparation method thereof | |
| CN114334637A (en) | Composite dielectric layer integrated by utilizing inorganic molecular crystal, preparation and application | |
| CN117457783A (en) | Hafnium oxide-based ultrathin phototransistor based on two-dimensional channel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |