CN112349593B - Two-dimensional thin film transistor with graphene as source and drain electrodes and preparation method - Google Patents
Two-dimensional thin film transistor with graphene as source and drain electrodes and preparation method Download PDFInfo
- Publication number
- CN112349593B CN112349593B CN202011163303.7A CN202011163303A CN112349593B CN 112349593 B CN112349593 B CN 112349593B CN 202011163303 A CN202011163303 A CN 202011163303A CN 112349593 B CN112349593 B CN 112349593B
- Authority
- CN
- China
- Prior art keywords
- graphene
- film
- dimensional
- adhesive tape
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 84
- 229910021389 graphene Inorganic materials 0.000 title claims abstract description 84
- 239000010409 thin film Substances 0.000 title claims abstract description 36
- 238000002360 preparation method Methods 0.000 title claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 85
- 239000010408 film Substances 0.000 claims abstract description 78
- 239000002390 adhesive tape Substances 0.000 claims abstract description 41
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 108010025899 gelatin film Proteins 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 16
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000010931 gold Substances 0.000 claims abstract description 12
- 229910052737 gold Inorganic materials 0.000 claims abstract description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 10
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 238000001704 evaporation Methods 0.000 claims abstract description 7
- 238000002207 thermal evaporation Methods 0.000 claims abstract description 6
- NRJVMVHUISHHQB-UHFFFAOYSA-N hafnium(4+);disulfide Chemical compound [S-2].[S-2].[Hf+4] NRJVMVHUISHHQB-UHFFFAOYSA-N 0.000 claims description 57
- 239000002184 metal Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 229910001220 stainless steel Inorganic materials 0.000 claims description 8
- 239000010935 stainless steel Substances 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 7
- 230000003287 optical effect Effects 0.000 claims description 7
- 238000003825 pressing Methods 0.000 claims description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 230000008020 evaporation Effects 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 239000008367 deionised water Substances 0.000 claims description 4
- 229910021641 deionized water Inorganic materials 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 238000007747 plating Methods 0.000 claims description 4
- 238000004506 ultrasonic cleaning Methods 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000000861 blow drying Methods 0.000 claims 1
- 238000000609 electron-beam lithography Methods 0.000 abstract description 4
- 238000004377 microelectronic Methods 0.000 abstract 1
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 2
- 239000004926 polymethyl methacrylate Substances 0.000 description 2
- 230000002269 spontaneous effect Effects 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BWGNESOTFCXPMA-UHFFFAOYSA-N Dihydrogen disulfide Chemical compound SS BWGNESOTFCXPMA-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a two-dimensional thin film transistor with graphene as a source electrode and a drain electrode and a preparation method thereof, wherein the two-dimensional transistor belongs to a bottom gate top contact type transistor. The preparation method comprises the steps of firstly using a mechanical stripping method to strip a thin film from a two-dimensional material block by using a England blue adhesive tape to a special PF gel film for Gelpak mechanical stripping, and selecting a material with proper thickness and uniform surface to transfer to a silicon/silicon dioxide substrate to be used as an N-type semiconductor channel layer. And stripping two graphene films, respectively transferring the two graphene films to two ends of the semiconductor layer to be used as a source electrode and a drain electrode, and finally evaporating the gold electrode by using a mask plate through a thermal evaporation method to obtain the two-dimensional thin film transistor. The invention is different from other two-dimensional device preparation processes, does not need complex and expensive electron beam lithography, is safe and environment-friendly in used material and low in cost, not only obtains a microelectronic device taking a two-dimensional material as a source electrode, a drain electrode and a channel, but also optimizes the existing two-dimensional transistor in the aspects of mobility, on-off ratio and the like.
Description
Technical Field
The invention relates to the technical field of preparation of two-dimensional thin film transistors, in particular to a two-dimensional material graphene which is used as a source electrode and a drain electrode of a transistor, so that the traditional two-dimensional thin film transistor is optimized.
Background
In recent years, two-dimensional layered semiconductor materials typified by disulfide, graphene, black Phosphorus (BP), and the like have excellent electrical propertiesHave received a great deal of attention. Researchers have developed high-performance electronic devices based on two-dimensional semiconductors, but their practical applications are severely affected by spontaneous oxidation of semiconductor materials. For example, few layer black phosphorus has high p-type carrier mobility (1000 cm) at room temperature 2 V -1 S -1 ) And the application of the material in electronic devices and circuits is limited due to instability in air. To address device stability issues, researchers have developed various schemes to protect the channel material from spontaneous oxidation, including Polymethylmethacrylate (PMMA) coating after lift-off, atomic Layer Deposition (ALD) grown Al 2 O 3 Coating, h-BN packaging, and optionally using a glove box for isolating water and oxygen for material preparation and the like. Of course, the problem of contact between the semiconductor layer and the metal electrode in the two-dimensional transistor is also important due to the instability of the two-dimensional transistor, and further development of the two-dimensional device is seriously affected.
HfS, on the other hand 2 The hafnium disulfide has a unique structure and a band gap which can be regulated by the number of layers, is a two-dimensional material with ultrahigh electrical performance, is expected to be applied to the field of electronic/optoelectronic devices, and although hafnium disulfide has many attractive electrical and optoelectronic characteristics, the water oxygen property of hafnium disulfide is poor, and after the hafnium disulfide is exposed in air for several hours, a hafnium disulfide thin film can be seriously and spontaneously oxidized due to the adsorption of moisture and oxygen, so that the electrical performance of the device is seriously degraded. And because the two-dimensional material has a contact problem with the metal electrode, the electrical performance of the two-dimensional thin film transistor is seriously influenced.
Disclosure of Invention
The invention aims to provide an N-type two-dimensional thin film transistor taking graphene as a source/drain electrode and a preparation method thereof. The two-dimensional thin film transistor applicable to the preparation method is of a bottom-gate-top contact structure, and the transistor sequentially comprises a gate electrode, a dielectric layer, an N-type semiconductor active layer and a source/drain electrode from bottom to top. According to the method, after the preparation of the two-dimensional thin film transistor semiconductor layer is finished, the two-dimensional material source/drain electrode is prepared and transferred through the same mechanical stripping method, the limitation that the two-dimensional material can only be subjected to mask preparation through electron beam lithography and a copper net with a smaller size can be improved, the contact between the two-dimensional material and a gold electrode can be improved, and therefore the electrical performance of the N-type two-dimensional thin film semiconductor is improved.
The specific technical scheme for realizing the purpose of the invention is as follows:
a preparation method of a two-dimensional thin film transistor with graphene as a source electrode and a drain electrode comprises the following specific steps:
step 1: preparation of two-dimensional material film
A1: preparation of hafnium disulfide semiconductor film
Placing the hafnium disulfide crystal block on an England blue adhesive tape, folding the adhesive tape in half, pressing, and then tearing; naturally adhering a layer of hafnium disulfide sheet on the torn England adhesive tape, tearing the adhesive tape on the surface of a fresh adhesive tape for 3-5 times, thinning the hafnium disulfide sheet, attaching the thinned hafnium disulfide sheet to a special PF gel film for Gelpak mechanical stripping attached to a glass slide, slightly uncovering the PF gel film, observing the PF gel film by using an optical microscope, judging the thickness of the hafnium disulfide film by color, and selecting a blue semitransparent material with the thickness of 10-15nm, uniform surface and the length of 15-200 mu m to mark for later use;
a2: preparation of graphene film material
Placing the graphene crystal block on an England blue adhesive tape, folding the adhesive tape in half, pressing, and then tearing; naturally adhering a layer of graphene sheets to a torn England adhesive tape, oppositely tearing the adhesive tape on the surface of a fresh adhesive tape for 3-5 times, thinning the graphene sheets, attaching the thinned graphene sheets to a Gelpak mechanical peeling special PF gel film attached to a glass slide, slightly uncovering the PF gel film, observing the PF gel film by using an optical microscope, judging the thickness of the graphene film through color, selecting two graphene film materials with the thickness of 5-10nm, uniform surface and the length of 50-200 mu m for later use, and respectively marking the graphene film materials as a graphene film material A and a graphene film material B;
step 2: transfer of hafnium disulfide and graphene two-dimensional thin film materials
B1: cleaning of substrates
Selecting silicon dioxide/Silicon (SiO) 2 a/Si) substrate in which silicon dioxide is thermally oxidizedThe thickness of the formation layer is 300nm, the substrate is sequentially placed in acetone, isopropanol and deionized water, and is sequentially cleaned for 5 minutes by an ultrasonic cleaning machine, and then is dried by a nitrogen gun to be used as a target substrate for later use;
b2: transfer of hafnium disulfide film material
Transferring the hafnium disulfide film on the PF gel film prepared in the step A1 to the target substrate in the step B1 by using a two-dimensional material transfer system and a matched microscope to serve as a semiconductor conducting channel of the two-dimensional transistor;
b3: transfer of graphene film materials A and B
Respectively transferring the graphene film material A and the graphene film material B on the PF gel film prepared in the step A2 to two ends of a hafnium disulfide film of a target substrate in the step B2 by using a two-dimensional material transfer system and a matched microscope, wherein the graphene film materials A and B and the hafnium disulfide film are horizontally stacked in the direction of the maximum length of each material A and B, the two ends of each material A and B are overlapped by 5-15 micrometers, the graphene film materials A and B are used as two-dimensional source and drain electrodes of a transistor, and the hafnium disulfide film exposed in the middle is a semiconductor conducting channel;
and step 3: preparation of source and drain metal electrodes
C1: fixed mask
Fixing a stainless steel mask on a hafnium disulfide film of a target substrate by using a two-dimensional material transfer system, wherein the hafnium disulfide film is completely covered by the mask part of the mask and two sides of the hafnium disulfide film are exposed out of a graphene film material A and a graphene film material B;
c2: metal source and drain electrodes of evaporated metal
Performing gold evaporation on the graphene film material A and the graphene film material B by using a stainless steel mask plate by adopting a conventional vacuum thermal evaporation method to obtain gold with the thickness of 50nm as a source and drain metal electrode; and manufacturing the two-dimensional thin film transistor.
In step 3, the current of the gold evaporation plating is 80-90A, and the speed is 0.1-0.12nm/s.
The two-dimensional thin film transistor with the graphene as the source and drain electrodes is prepared by the method.
Compared with the prior art, the invention has the greatest advantages that: the invention does not use the complex electron beam lithography technology required by the preparation of most two-dimensional devices, and has simple operation and low cost; the graphene is used as the source and drain electrodes, so that the semiconductor layer and the semiconductor channel layer are simultaneously made of two-dimensional materials, and the graphene has a work function smaller than that of hafnium disulfide, so that the contact between the hafnium disulfide and the electrodes is improved, the carrier transportation is promoted, and the mobility and the switching current ratio of the two-dimensional thin film transistor are improved to a certain extent.
Drawings
Fig. 1 is a schematic cross-sectional structure diagram of a two-dimensional thin film transistor with graphene as a source/drain electrode, which is prepared by the method of the present invention;
FIG. 2 is a schematic cross-sectional structure of a two-dimensional thin film transistor prepared by a comparative example;
fig. 3 is a comparison graph of transfer characteristics curves of the two-dimensional thin film transistor with or without the graphene electrode layer according to the present invention.
Detailed Description
The invention is further illustrated by the following figures, examples and comparative examples.
Referring to fig. 1, the two-dimensional thin film transistor according to the embodiment of the present invention is a bottom-gate top-contact structure, and includes a gate electrode 5, a dielectric layer 4, a semiconductor layer 3, a two-dimensional source/drain electrode 2, and a metal electrode 1; wherein, the gate electrode 5 is a silicon substrate; the dielectric layer 4 is a silicon dioxide layer; the semiconductor layer 3 is a hafnium disulfide semiconductor material obtained by transfer through a mechanical stripping method; the source and drain electrodes 2 are made of graphene materials obtained by transferring through a mechanical stripping method; the metal electrode 1 is a gold source-drain electrode formed by thermal evaporation.
The following invention provides preferred examples and comparative examples, but should not be construed as being limited to the examples set forth herein.
Examples
The preparation method of the optimized two-dimensional thin film transistor with the graphene as the source and drain electrodes comprises the following steps:
(1) And placing the hafnium disulfide crystal block on an England blue adhesive tape, folding the adhesive tape in half, pressing, and then tearing. Naturally adhering a layer of thicker hafnium disulfide sheet on the torn England adhesive tape, tearing the adhesive tape on the surface of a fresh adhesive tape for 3-5 times, attaching the adhesive tape to a special PF gel film for Gelpak mechanical stripping attached to a glass slide, slightly uncovering the PF gel film, observing the PF gel film by using an optical microscope, judging the thickness of the hafnium disulfide film by color, and selecting a blue semitransparent material with the thickness of 10-15nm, uniform surface and the length of 15-200 mu m for marking for later use; and then placing the graphene crystal block on an England blue adhesive tape, folding the adhesive tape in half, pressing, and then tearing. Naturally adhering a layer of thicker graphene sheet on the torn England adhesive tape, tearing the adhesive tape on the surface of a fresh adhesive tape for 3-5 times, attaching the adhesive tape to a Gelpak mechanical peeling special PF gel film attached to a glass slide, slightly uncovering the adhesive tape, observing the adhesive tape by using an optical microscope, judging the thickness of the graphene film by color, selecting two graphene film materials with the thickness of 5-10nm, uniform surface and the length of 50-200 mu m for later use, and respectively marking as a graphene A material and a graphene film material B;
(2) Selecting silicon dioxide/Silicon (SiO) 2 The silicon dioxide thermal oxidation layer is 300nm in thickness, the substrate is sequentially placed in acetone, isopropanol and deionized water, is sequentially cleaned for 5 minutes by an ultrasonic cleaning machine, and is dried by a nitrogen gun to serve as a target substrate for later use; transferring the hafnium disulfide film on the PF gel film prepared in the step (1) to a target substrate by using a two-dimensional material transfer system and a matched microscope to serve as a semiconductor conducting channel of a two-dimensional transistor; and (2) respectively transferring the graphene film material A and the graphene film material B on the PF gel film prepared in the step (1) to two ends of the hafnium disulfide film of the target substrate in the step (B) by using a two-dimensional material transfer system and a matched microscope, wherein the graphene film materials A and B and the hafnium disulfide film are horizontally stacked in the maximum length direction, the two ends of the graphene film materials A and B are overlapped by 5-15 micrometers, the graphene film materials A and B are used as two-dimensional source and drain electrodes of a transistor, and the hafnium disulfide film exposed in the middle is used as a semiconductor conducting channel.
(3) Fixing a stainless steel mask on a hafnium disulfide film of a target substrate by using a two-dimensional material transfer system, wherein the hafnium disulfide film is completely covered by the mask part of the mask and two ends of the hafnium disulfide film are exposed out of a graphene film material A and a graphene film material B; performing evaporation plating on the graphene film material A and the graphene film material B by using a stainless steel mask plate by adopting a conventional vacuum thermal evaporation method to obtain gold with the thickness of 50nm as a source and drain metal electrode; and manufacturing the two-dimensional thin film transistor.
Comparative example
The preparation method of the traditional two-dimensional thin film transistor with single-layer metal as the source and drain electrodes comprises the following steps:
(1) And placing the hafnium disulfide crystal block on an England blue adhesive tape, folding the adhesive tape in half, pressing, and then tearing. Naturally adhering a layer of thicker hafnium disulfide sheet on the torn England adhesive tape, tearing the adhesive tape on the surface of a fresh adhesive tape for 3-5 times, attaching the adhesive tape to a Gelpak mechanical peeling special PF gel film attached to a glass slide, slightly lifting the PF gel film, observing the PF gel film by using an optical microscope, judging the thickness of the hafnium disulfide film by color, and selecting a blue semitransparent material with the thickness of 10-15nm, uniform surface and the length of 15-200 mu m for marking for later use.
(2) Selecting silicon dioxide/Silicon (SiO) 2 The silicon dioxide thermal oxidation layer is 300nm in thickness, the substrate is sequentially placed in acetone, isopropanol and deionized water, is sequentially cleaned for 5 minutes by an ultrasonic cleaning machine, and is dried by a nitrogen gun to serve as a target substrate for later use; and (2) transferring the hafnium disulfide film on the PF gel film prepared in the step (1) to a target substrate by using a two-dimensional material transfer system and a matched microscope to serve as a semiconductor conducting channel of a two-dimensional transistor.
(3) Fixing a stainless steel mask on the hafnium disulfide film of the target substrate by using a two-dimensional material transfer system, exposing partial hafnium disulfide film on both sides of the mask part, and finally evaporating and plating the stainless steel mask on the target substrate by using a conventional vacuum thermal evaporation method to obtain gold with the thickness of 50nm as a source and drain metal electrode to obtain the two-dimensional transistor.
The comparison of the electrical parameters of the two-dimensional thin film transistor using graphene as a source and drain electrode prepared in the example and the conventional two-dimensional transistor prepared in the comparative example is as follows: table 1 shows that the two-dimensional thin film transistor using graphene as a source/drain electrode is compared with the conventional two-dimensional transistorComparing the electrical parameters of the tubes; fig. 3 is a graph of transfer characteristics of a two-dimensional thin film transistor in which graphene is used as a source and drain electrode, relative to a conventional two-dimensional transistor. Comparing table 1 and fig. 3, it can be seen that a layer of graphene is inserted between the two-dimensional semiconductor and the metal electrode as the source-drain electrode optimized thin film transistor, the source-drain current is greatly increased, the threshold voltage is reduced to some extent, the current on-off ratio is increased by 1 order of magnitude, and the mobility is increased from 0.01cm 2 V -1 S -1 Increased by an order of magnitude to 0.1cm 2 V -1 S -1 . Therefore, the graphene prepared by the method is used as the source electrode and the drain electrode of the two-dimensional thin film transistor, the structure of the traditional two-dimensional transistor is optimized, the electrical performance of the traditional two-dimensional transistor is obviously improved, and the method has very important significance for the development from the two-dimensional transistor to the full two-dimensional transistor.
The two-dimensional material graphene is inserted between the semiconductor layer and the metal electrode, and the graphene is a zero-band-gap semiconductor and is very easy to transmit current carriers with metal, and the work function of the graphene is 4.6eV, which is less than the work function of hafnium disulfide, of 4.9eV, so that N-type electron doping is formed on the hafnium disulfide to a certain extent, the transportation of the current carriers is promoted, the contact between the semiconductor layer and the metal electrode is improved, the concentration of the current carriers in a channel is increased, and the electrical performance of the traditional two-dimensional transistor is improved.
Therefore, according to the invention, graphene is used as a source electrode and a drain electrode, a complex and expensive electron beam lithography technology is not used, the operation is simple, and the cost is low, so that a semi-full two-dimensional thin film transistor is realized, the contact problem between a two-dimensional material and a metal electrode is improved, the electrical property of the two-dimensional transistor is improved, and the method has great significance for realizing a full two-dimensional transistor later.
TABLE 1
| Electrical parameters of transistor | Graphene-free | With graphene |
| On-off ratio | 10 4 | 10 6 |
| Mobility (cm) 2 V -1 S -1 ) | 0.01 | 0.1 |
| Threshold voltage (V) | 51 | 35 |
Claims (2)
1. A preparation method of a two-dimensional thin film transistor with graphene as a source and drain electrode is characterized by comprising the following specific steps of:
step 1: preparation of two-dimensional material film
A1: preparation of hafnium disulfide semiconductor film
Placing the hafnium disulfide crystal block on an England blue adhesive tape, folding the adhesive tape in half, pressing, and then tearing; naturally adhering a layer of hafnium disulfide sheet on a torn England adhesive tape, oppositely tearing the adhesive tape on the surface of a fresh adhesive tape for 3-5 times, thinning the hafnium disulfide sheet, attaching the thinned hafnium disulfide sheet to a Gelpak mechanical peeling special PF gel film attached to a glass slide, slightly lifting the PF gel film, observing the PF gel film by using an optical microscope, judging the thickness of the hafnium disulfide film by color, and selecting a blue semitransparent material with the thickness of 10-15nm, uniform surface and the length of 15-200 mu m to mark for later use;
a2: preparation of graphene film material
Placing the graphene crystal block on an England blue adhesive tape, folding the adhesive tape in half, pressing, and then tearing; naturally adhering a layer of graphene sheet to a torn England adhesive tape, tearing the adhesive tape on the surface of a fresh adhesive tape for 3-5 times, thinning the graphene sheet, attaching the thinned graphene sheet to a special PF gel film for Gelpak mechanical stripping attached to a glass slide, slightly uncovering the PF gel film, observing the PF gel film by using an optical microscope, judging the thickness of the graphene film through color, selecting two graphene film materials with the thickness of 5-10nm, uniform surface and the length of 50-200 mu m for later use, and respectively marking the two graphene film materials as a graphene film material A and a graphene film material B;
step 2: transfer of hafnium disulfide and graphene two-dimensional thin film materials
B1: cleaning of substrates
Selecting a silicon dioxide/silicon substrate, wherein the thickness of a silicon dioxide thermal oxidation layer is 300nm, sequentially placing the substrate in acetone, isopropanol and deionized water, sequentially cleaning for 5 minutes by using an ultrasonic cleaning machine, and then blow-drying by using a nitrogen gun to serve as a target substrate for later use;
b2: transfer of hafnium disulfide film material
Transferring the hafnium disulfide film on the PF gel film prepared in the step A1 to the target substrate in the step B1 by using a two-dimensional material transfer system and a matched microscope to serve as a semiconductor conducting channel of the two-dimensional transistor;
b3: transfer of graphene film materials A and B
Respectively transferring the graphene film material A and the graphene film material B on the PF gel film prepared in the step A2 to two ends of a hafnium disulfide film of a target substrate in the step B2 by using a two-dimensional material transfer system and a matched microscope, wherein the graphene film materials A and B and the hafnium disulfide film are horizontally stacked in the direction of the maximum length of each material A and B, the two ends of each material A and B are overlapped by 5-15 micrometers, the graphene film materials A and B are used as two-dimensional source and drain electrodes of a transistor, and the hafnium disulfide film exposed in the middle is a semiconductor conducting channel;
and 3, step 3: preparation of source and drain metal electrode
C1: fixed mask
Fixing a stainless steel mask on a hafnium disulfide film of a target substrate by using a two-dimensional material transfer system, wherein the hafnium disulfide film is completely covered by the mask part of the mask and two sides of the hafnium disulfide film are exposed out of a graphene film material A and a graphene film material B;
c2: metal source and drain electrodes evaporated
Performing gold evaporation on the graphene film material A and the graphene film material B by using a stainless steel mask plate by adopting a conventional vacuum thermal evaporation method to obtain gold with the thickness of 50nm as a source and drain metal electrode; manufacturing the two-dimensional thin film transistor;
in step 3, the current of the gold evaporation plating is 80-90A, and the speed is 0.1-0.12nm/s.
2. The two-dimensional thin film transistor with the source electrode and the drain electrode made of the graphene according to the method of claim 1 is characterized in that the thickness of a hafnium disulfide semiconductor layer of the two-dimensional thin film transistor is 10-15nm, the thickness of a graphene layer is 5-10nm, the length of a transistor channel is 15-200 μm, and the thickness of a gold electrode is 50 nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011163303.7A CN112349593B (en) | 2020-10-27 | 2020-10-27 | Two-dimensional thin film transistor with graphene as source and drain electrodes and preparation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011163303.7A CN112349593B (en) | 2020-10-27 | 2020-10-27 | Two-dimensional thin film transistor with graphene as source and drain electrodes and preparation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112349593A CN112349593A (en) | 2021-02-09 |
| CN112349593B true CN112349593B (en) | 2023-02-03 |
Family
ID=74359086
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011163303.7A Active CN112349593B (en) | 2020-10-27 | 2020-10-27 | Two-dimensional thin film transistor with graphene as source and drain electrodes and preparation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112349593B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113097074B (en) * | 2021-04-06 | 2024-02-09 | 南京大学 | Two-dimensional material patterned electrode integration and surface passivation method |
| CN113299558B (en) * | 2021-05-24 | 2023-01-31 | 华东师范大学 | Floating gate structure transistor with hafnium disulfide as channel and preparation method thereof |
| CN113488373B (en) * | 2021-07-07 | 2023-07-25 | 湖南大学 | Method for preparing single-layer two-dimensional semiconductor array by dry method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107634099A (en) * | 2017-08-11 | 2018-01-26 | 上海集成电路研发中心有限公司 | A kind of two dimensional crystal material FET and preparation method thereof |
| WO2018092025A1 (en) * | 2016-11-16 | 2018-05-24 | King Abdullah University Of Science And Technology | Lateral heterojunctions between a first layer and a second layer of transition metal dichalcogenide |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160284811A1 (en) * | 2013-11-04 | 2016-09-29 | Massachusetts Institute Of Technology | Electronics including graphene-based hybrid structures |
| US9577049B1 (en) * | 2016-01-06 | 2017-02-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
| US10388732B1 (en) * | 2018-05-30 | 2019-08-20 | Globalfoundries Inc. | Nanosheet field-effect transistors including a two-dimensional semiconducting material |
| CN111430354A (en) * | 2020-03-12 | 2020-07-17 | 复旦大学 | Low-power-consumption semi-floating gate memory and preparation method thereof |
| CN111490045B (en) * | 2020-04-27 | 2022-10-11 | 复旦大学 | Semi-floating gate memory based on two-dimensional material and preparation method thereof |
-
2020
- 2020-10-27 CN CN202011163303.7A patent/CN112349593B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018092025A1 (en) * | 2016-11-16 | 2018-05-24 | King Abdullah University Of Science And Technology | Lateral heterojunctions between a first layer and a second layer of transition metal dichalcogenide |
| CN107634099A (en) * | 2017-08-11 | 2018-01-26 | 上海集成电路研发中心有限公司 | A kind of two dimensional crystal material FET and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112349593A (en) | 2021-02-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112349593B (en) | Two-dimensional thin film transistor with graphene as source and drain electrodes and preparation method | |
| US8530886B2 (en) | Nitride gate dielectric for graphene MOSFET | |
| CN112582542B (en) | Monomolecular field effect transistor based on two-dimensional van der Waals heterostructure and preparation method thereof | |
| CN111446288B (en) | NS (non-volatile) stacked transistor based on two-dimensional material and preparation method thereof | |
| KR20170098053A (en) | Transition metal dichalcogenide thin film transistor and method of manufacturing the same | |
| CN111063731B (en) | CNT-IGZO thin film heterojunction bipolar transistor and preparation method and application thereof | |
| CN112582541A (en) | Vertical monomolecular film field effect transistor based on two-dimensional laminated heterostructure and preparation method thereof | |
| CN107919396B (en) | Based on WO3/Al2O3Zero-grid-source-spacing diamond field effect transistor with double-layer grid medium and manufacturing method | |
| KR101904383B1 (en) | Method for doping 2d semiconductor using atomic layer deposition and method for fabricating cmos device comprising the same | |
| Han et al. | Indium-Tin-Oxide Thin-Film Transistors with High Field-Effect Mobility (129.5 cm 2/V· s) and Low Thermal Budget (150° C) | |
| CN111430244B (en) | Preparation method of gallium nitride and molybdenum disulfide mixed-scale PN junction | |
| WO2023216852A1 (en) | Method for regulating doping characteristics of two-dimensional material by click chemical reaction, and application | |
| CN111490161A (en) | Organic thin field effect transistor and preparation method thereof | |
| Nourbakhsh et al. | Serially connected monolayer MoS 2 FETs with channel patterned by a 7.5 nm resolution directed self-assembly lithography | |
| CN115632066A (en) | SnS based on double-gate regulation 2 /MoSe 2 Heterojunction tunneling field effect transistor and preparation method and application thereof | |
| Okamoto et al. | Electrical characteristics of Ge-based metal-insulator-semiconductor devices with Ge3N4 dielectrics formed by plasma nitridation | |
| CN112447858B (en) | Junction field effect transistor and preparation method thereof | |
| Wang et al. | Aluminum oxide/fluoride self-assembled monolayer double gate dielectric for solution-processed indium oxide thin-film transistors | |
| CN107768519A (en) | Phase inverter and preparation method thereof | |
| CN112701156A (en) | Back gate transistor and preparation method thereof | |
| CN109301067B (en) | Hexamethyldisilazane modified organic thin film transistor and preparation method thereof | |
| KR20220165488A (en) | Optoelectronic devices and manufacturing method of the optoelectronic device using contact Engineering of Vertically Grown Dendritic Nanomaterials with tunneling insulators | |
| CN117976544B (en) | Cu-doped SnO thin film transistor, complementary logic circuit and preparation method thereof | |
| CN114784130B (en) | Electrostatic self-doping diode and preparation method thereof | |
| CN114497232B (en) | Mutation NN type junction field effect transistor and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |