CN114784130B - Electrostatic self-doping diode and preparation method thereof - Google Patents
Electrostatic self-doping diode and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 48
- 239000000463 material Substances 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000010276 construction Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 51
- 229910052582 BN Inorganic materials 0.000 claims description 36
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 36
- 239000002135 nanosheet Substances 0.000 claims description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 32
- 229910052710 silicon Inorganic materials 0.000 claims description 32
- 239000010703 silicon Substances 0.000 claims description 32
- 230000008569 process Effects 0.000 claims description 28
- ITRNXVSDJBHYNJ-UHFFFAOYSA-N tungsten disulfide Chemical compound S=[W]=S ITRNXVSDJBHYNJ-UHFFFAOYSA-N 0.000 claims description 27
- 238000012546 transfer Methods 0.000 claims description 25
- 238000000151 deposition Methods 0.000 claims description 23
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 20
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 20
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 18
- 238000001035 drying Methods 0.000 claims description 18
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 claims description 14
- 229910052982 molybdenum disulfide Inorganic materials 0.000 claims description 14
- 238000004528 spin coating Methods 0.000 claims description 14
- 239000003292 glue Substances 0.000 claims description 12
- 229910052723 transition metal Inorganic materials 0.000 claims description 9
- -1 transition metal chalcogenide Chemical class 0.000 claims description 9
- 238000010894 electron beam technology Methods 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000002207 thermal evaporation Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910021389 graphene Inorganic materials 0.000 claims description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 2
- 238000000231 atomic layer deposition Methods 0.000 claims description 2
- ROUIDRHELGULJS-UHFFFAOYSA-N bis(selanylidene)tungsten Chemical compound [Se]=[W]=[Se] ROUIDRHELGULJS-UHFFFAOYSA-N 0.000 claims description 2
- HITXEXPSQXNMAN-UHFFFAOYSA-N bis(tellanylidene)molybdenum Chemical compound [Te]=[Mo]=[Te] HITXEXPSQXNMAN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- 239000011651 chromium Substances 0.000 claims description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 2
- MHWZQNGIEIYAQJ-UHFFFAOYSA-N molybdenum diselenide Chemical compound [Se]=[Mo]=[Se] MHWZQNGIEIYAQJ-UHFFFAOYSA-N 0.000 claims description 2
- 239000002064 nanoplatelet Substances 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 8
- 230000007547 defect Effects 0.000 abstract description 7
- 230000002441 reversible effect Effects 0.000 abstract description 5
- 239000000126 substance Substances 0.000 abstract description 4
- 238000012545 processing Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 89
- 239000002390 adhesive tape Substances 0.000 description 28
- 239000000084 colloidal system Substances 0.000 description 12
- 239000002356 single layer Substances 0.000 description 12
- 230000000052 comparative effect Effects 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 230000003287 optical effect Effects 0.000 description 6
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 5
- 238000003825 pressing Methods 0.000 description 5
- 239000008367 deionised water Substances 0.000 description 4
- 229910021641 deionized water Inorganic materials 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 4
- JKQOBWVOAYFWKG-UHFFFAOYSA-N molybdenum trioxide Chemical compound O=[Mo](=O)=O JKQOBWVOAYFWKG-UHFFFAOYSA-N 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004205 dimethyl polysiloxane Substances 0.000 description 2
- 235000013870 dimethyl polysiloxane Nutrition 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- CXQXSVUQTKDNFP-UHFFFAOYSA-N octamethyltrisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)O[Si](C)(C)C CXQXSVUQTKDNFP-UHFFFAOYSA-N 0.000 description 2
- 238000004987 plasma desorption mass spectroscopy Methods 0.000 description 2
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 238000011144 upstream manufacturing Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
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Abstract
The invention discloses an electrostatic self-doping diode and a preparation method thereof, and belongs to the technical field of two-dimensional semiconductor materials. The electrostatic autodoping the structure of the diode includes: the semiconductor device includes an insulating substrate, a drain electrode, a dielectric layer, a two-dimensional semiconductor layer, and a source electrode, which are sequentially stacked, wherein the two-dimensional semiconductor layer is required to be in contact with the drain electrode. The electrostatic self-doping diode prepared by the invention has excellent performances of good service stability, good universality and the like, and meanwhile, the processing technology is simple. The preparation method provided by the invention aims to solve the problem of unstable material polarity caused by means of chemical doping, physical doping, defect regulation and the like, and provides a novel, simple, feasible, lossless and reversible diode construction approach.
Description
Technical Field
The invention relates to the technical field of two-dimensional semiconductor materials, in particular to an electrostatic self-doping diode and a preparation method thereof.
Background
A diode is a crucial circuit element, and many analog and digital circuits need to use a diode to realize corresponding functions, and the key characteristic of the diode is the extremely asymmetric current-voltage characteristic under forward and reverse bias. In conventional silicon-based semiconductor designs, the diode typically utilizes heavily doped techniques to control the semiconductor carrier concentration and polarity such that a homogeneous diode is formed between two regions of the semiconductor. Compared with the three-dimensional bulk structure of a silicon-based material, a two-dimensional material represented by graphene and a transition metal chalcogenide can be used for manufacturing a semiconductor or an electronic chip with smaller specification and higher energy efficiency due to the nanoscale two-dimensional layered structure, and the theoretical research in recent years shows that the two-dimensional material has bright prospect as a new-generation nano electronic device. However, when the channel size is very small, the number of doping atoms will be greatly reduced on the nanometer scale, and achieving stable and controllable doping is a serious challenge. Thus, conventional doping techniques have not been effective in achieving diode structures on the nanometer scale, and other strategies should be sought to modulate and control the characteristics of the semiconductor.
At present, based on two-dimensional materials, some new diode construction schemes have been proposed in succession, which can be classified into homojunction type and heterojunction type according to the type of material. The heterojunction diode needs at least two materials with opposite polarities, and the method considers the matching property and interface contact stability between the two materials. Compared with a heterojunction, the homojunction diode has a perfectly matched energy band structure, which brings smaller interface contact resistance and fewer carrier traps, and the existing main construction schemes can be divided into two types: 1. surface doping, which is based on the principle that charge transfer is achieved by means of a chemical potential difference between the semiconductor material and the dopant, thereby adjusting the carrier concentration in the body. However, the dopant physically adsorbed on the surface of the sample is easily exfoliated by environmental influences, thereby affecting the doping stability. Furthermore, the dopant is liable to react with the surrounding active species, and therefore, the lifetime of the homojunction is also affected. 2. The defect regulation is based on the principle that inevitable defects of materials are controlled, and the characteristics of a defect regulation semiconductor are repaired or manufactured, so that the concentration and polarity of current carriers are changed to realize diode construction. However, the method is difficult to realize large-area defect accurate regulation and control, and other uncontrollable defects are likely to be introduced due to poor controllability to influence the performance of the diode.
Disclosure of Invention
In order to solve the above problems, the present invention provides an electrostatic self-doping diode and a method for manufacturing the same. The electrostatic self-doping diode has excellent performances of good service stability, good universality and the like, and meanwhile, the processing technology is simple. The preparation method provided by the invention aims to avoid the problem of unstable material polarity caused by means of chemical doping, physical doping, defect regulation and the like, and provides a novel way for constructing a simple, convenient and feasible lossless and reversible diode.
In order to achieve the purpose, the invention provides the following technical scheme:
the invention adopts one of the technical schemes: provided is an electrostatic self-doping diode, the structure comprises: an insulating substrate 1, a drain electrode 2, a dielectric layer 3, a two-dimensional semiconductor layer 5 and a source electrode 4; wherein the drain electrode 2 is positioned above the insulating substrate 1, the dielectric layer 3 partially covers the drain electrode 2, the two-dimensional semiconductor layer 5 is positioned above the dielectric layer 3 and is in contact with the drain electrode 2, and the source electrode 4 is positioned above the two-dimensional semiconductor layer 5;
the two-dimensional semiconductor layer 5 is made of two-dimensional transition metal chalcogenide nanosheets.
Preferably, the insulating substrate 1 is selected from: a silicon wafer with an oxide layer, a flexible insulating PET or sapphire substrate.
Preferably, the material of the drain electrode 2 comprises gold, chromium or graphene, and the thickness is 50-80nm; the source electrode 4 is a metal electrode and has a thickness of 1-80nm.
The extended drain 2 of the present invention can also act as a gate electrode at the same time.
The extended drain of the invention can be used as a drain and a gate, namely when the drain is applied with bias voltage, a gate voltage is applied to regulate the carrier concentration of a channel material. When positive voltage is applied, a positive electric field is generated to improve the electron concentration of the channel material and reduce the hole concentration, and when negative voltage is applied, a negative electric field is generated to improve the hole concentration and reduce the electron concentration. Therefore, under positive and negative bias, the carrier concentration participating in conduction is different, an asymmetric carrier transport behavior is shown, and the rectification characteristic is realized.
Preferably, the material of the dielectric layer 3 is selected from: two-dimensional layered boron nitride, silicon oxide, aluminum oxide or hafnium oxide with a thickness of 20-50nm.
Preferably, the semiconductor material having a band gap is a two-dimensional transition metal chalcogenide nanosheet.
More preferably, the two-dimensional transition metal chalcogenide nanoplatelets are selected from: molybdenum disulfide, molybdenum diselenide, tungsten disulfide, tungsten diselenide, or molybdenum ditelluride, with a thickness of 0.7-10nm.
The second technical scheme of the invention is as follows: the preparation method of the electrostatic self-doping diode comprises the following steps:
(1) Depositing the drain electrode 2 on the insulating substrate 1;
(2) Locally growing the dielectric layer 3 on the drain 2;
(3) Assembling the two-dimensional semiconductor layer 5 over the dielectric layer 3 and in contact with the drain electrode 2;
(4) And depositing the source electrode 4 above the two-dimensional semiconductor layer 5 to complete the construction of the electrostatic self-doping diode.
Preferably, the deposition method in step (1) and step (4) is: patterning by using an electron beam exposure process or an ultraviolet exposure process, and completing deposition by using a thermal evaporation process; the growing method in the step (2) comprises the following steps: a dry transfer process or an atomic layer deposition process; the assembly method in step (3) is a wet transfer process.
Preferably, the dry transfer process comprises the following specific steps: spin-coating PPC glue on the substrate with the dielectric layer 3 material, and drying to obtain a PPC film with the dielectric layer 3 material and the thickness of 1-3 μm; and transferring the PPC film with the dielectric layer 3 material from the substrate to the position above the drain electrode 2, drying at 100 ℃ for 30min, immersing in an acetone solution to remove the PPC glue, and finishing the transfer.
Taking the dielectric layer 3 material as boron nitride and the substrate as a silicon wafer as an example, the dry transfer process comprises the following specific steps:
1. firstly, spin-coating a layer of PPC colloid on a silicon wafer with layered boron nitride, and drying to obtain the silicon wafer with boron nitride and a PPC film, wherein the thickness of the PPC film is 1-3 microns;
2. slowly tearing off the PPC film with the boron nitride from the silicon wafer by using a 3M adhesive tape, and fixing the PPC film on a customized carrying plate for later use;
3. stacking the PPC film with the boron nitride obtained in the step 2 on a pre-deposited drain electrode 2 through an accurate transfer platform with an optical microscope;
4. and after the transfer of the PPC film with the boron nitride is finished, drying the PPC film on a hot plate at 100 ℃ for 30min, and then putting the PPC film into an acetone solution to remove PPC glue, thereby finishing the transfer.
Preferably, the wet transfer process comprises the following specific steps: and (3) spin-coating PMMA glue on the substrate with the two-dimensional semiconductor layer 5 material, drying at 120 ℃ for 1-2min to obtain a PMMA film with the two-dimensional semiconductor layer 5 material, transferring the PMMA film with the two-dimensional semiconductor layer 5 material to the position above the dielectric layer 3 by using a wet method, contacting with the drain electrode 2, immersing in an acetone solution to remove the PMMA glue, and finishing the transfer.
Taking a substrate as a silicon wafer as an example, the wet transfer process comprises the following specific steps:
firstly, spin-coating a layer of PMMA glue on a silicon wafer with transition metal chalcogenide nanosheets, and then drying for 1-2min at 120 ℃ by using a hot plate; then immersing the wafer into a solution with the ratio of deionized water to hydrofluoric acid being 5, and etching off a silicon dioxide oxide layer on the surface of the silicon wafer to obtain the PMMA film floating on the surface of the solution and provided with transition metal chalcogenide nanosheets; cleaning a residual hydrofluoric acid solution on the surface of the film in a deionized water solution, and then fishing the film to a customized carrying plate with PDMS; and finally, precisely stacking the transition metal chalcogenide nanosheets on the PMMA film on the upper surface of the dielectric layer 3 by using a precise transfer platform and contacting with the drain electrode 2, and then putting into an acetone solution to remove the PMMA adhesive residues.
The invention has the following beneficial technical effects:
the dielectric layer partially covers the drain electrode, and the extended drain electrode is used as a bias voltage to drive current drift and is also used as a grid voltage to regulate the channel carrier concentration, so that asymmetric carrier transport behavior is realized, and excellent rectification characteristic and ultralow reverse bias saturation current are shown.
The inventive electrostatic self-doping diode based on semiconductor material with band gap has ultra-high light-dark switching ratio (about 10) under illumination condition 7 ) The optical control switch can be used in the field of photoelectric devices as an optical control switch.
The diode constructed by the invention avoids the damage of complex processes such as chemical doping and the like to the structure of the conductive channel material by utilizing the reversibility and nondestructive nature of electrostatic doping, and is beneficial to improving the service life and long-term service stability of the device.
The preparation method provided by the invention is simple, convenient and feasible, and has universality.
Drawings
Fig. 1 is a schematic structural diagram of an electrostatic self-doping diode according to the present invention.
Fig. 2 is a current-voltage curve of a single layer molybdenum disulfide electrostatic autodoped diode in example 1.
Fig. 3 is a current-voltage curve of a single-layer molybdenum disulfide electrostatic self-doped diode in example 1 under a dark light condition.
FIG. 4 is a plot of rectification ratio versus time for a single layer of an electrostatic autodoped diode of example 1.
Fig. 5 is a current-voltage curve of the esd-less diode of example 2.
Fig. 6 is a schematic structural view of a comparative example.
Figure 7 is a current-voltage curve for a tungsten disulfide few layer transistor of a comparative example.
Wherein 1 is an insulating substrate, 2 is a drain electrode, 3 is a dielectric layer, 4 is a source electrode, and 5 is a two-dimensional semiconductor layer.
Detailed Description
Reference will now be made in detail to various exemplary embodiments of the invention, the detailed description should not be construed as limiting the invention but rather as a more detailed description of certain aspects, features and embodiments of the invention. It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Further, for numerical ranges in this disclosure, it is understood that each intervening value, between the upper and lower limit of that range, is also specifically disclosed. Every intervening value, to the extent any stated value or intervening value in a stated range, and any other stated or intervening value in a stated range, is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included or excluded in the range.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although only preferred methods and materials are described herein, any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention.
As used herein, the terms "comprising," "including," "having," "containing," and the like are open-ended terms that mean including, but not limited to.
The structure of the electrostatic self-doping diode is schematically shown in fig. 1, wherein 1 is an insulating substrate, 2 is a drain electrode, 3 is a dielectric layer, 4 is a source electrode, and 5 is a two-dimensional semiconductor layer.
Example 1
Preparing a monolayer molybdenum disulfide electrostatic self-doping diode:
(1) Preparing a two-dimensional semiconductor layer 5 (a single-layer molybdenum disulfide nanosheet) by using a chemical vapor deposition method: molybdenum trioxide powder (10 mg) and sulfur powder (1 g, excessive, sulfur powder placed upstream and capable of being used for multiple times) are used as precursors, and under the conditions of growth temperature of 850 ℃ and oxygen assistance, a single-layer molybdenum disulfide with the thickness of 0.7 nm is generated through reaction. Sulfur powder is placed at the upstream of the vent, and changed into sulfur vapor at 170 ℃ and led to the midstream (where the molybdenum trioxide powder is placed) with the carrier gas (Ar) at the temperature of 850 ℃, and the sulfur vapor reacts to generate MoS 2 。
(2) Preparing a few-layer boron nitride nanosheet by using a mechanical stripping method: and adhering a 3M blue film adhesive tape on the boron nitride crystal, slowly tearing off the adhesive tape, then, leaving a plurality of layers of boron nitride materials on the adhesive tape, pressing the adhesive tape with the boron nitride slice on the silicon wafer, slowly uncovering the silicon wafer to leave a few layers of boron nitride nanosheets on the silicon wafer, and repeating the previous operation for a plurality of times to obtain the boron nitride nanosheets with different thicknesses, wherein the BN prepared by the embodiment has the thickness of 25nm.
(3) Pre-deposition of a drain electrode: and (2) spin-coating a layer of PMMA colloid on the insulating substrate 1, drying for 1min at 180 ℃, carrying out patterning treatment by using an electron beam exposure technology, and depositing a metal electrode by using a thermal evaporation process, wherein the electrode material is pure gold, so that the pre-deposition of the drain electrode 2 is completed, and the thickness is 50nm.
(4) The dielectric layer 3 partially covers the drain 2: spin-coating PPC colloid on a silicon wafer with boron nitride nanosheets, drying at 100 ℃ for 1min to form a PPC film with the thickness of 500nm, slowly peeling off the PPC film with the boron nitride from the silicon wafer by means of a 3M adhesive tape, stacking the PPC film on a pre-deposited drain electrode 2 through an accurate transfer platform with an optical microscope to complete local coverage of a dielectric layer 3, wherein the thickness of the dielectric layer 3 is 25nm.
(5) Assembling of the two-dimensional semiconductor layer 5: spin-coating a layer of PMMA glue on a silicon wafer with a single-layer molybdenum disulfide nanosheet as a carrier layer, drying at 120 ℃ for 1min to form a film, then immersing the film into a solution with a ratio of deionized water to hydrofluoric acid of 5; cleaning a residual hydrofluoric acid solution on the surface of the film in a deionized water solution, and then fishing the film to a customized carrying plate with PDMS; and finally, precisely stacking the molybdenum disulfide nanosheets on the PMMA film on the upper surface of the dielectric layer 3 by using a precise transfer platform and contacting with the drain electrode 2, and then putting the PMMA film into an acetone solution to remove the PMMA residual glue, thereby completing the assembly of the two-dimensional semiconductor layer 5 as a conductive channel material.
(6) And (4) depositing a source electrode: and depositing a metal electrode on one side of the single-layer molybdenum disulfide as a source electrode 4 by using an electron beam exposure technology and a thermal evaporation process, wherein the electrode is made of pure gold and has the thickness of 50nm, and finally completing the single-layer molybdenum disulfide electrostatic self-doping diode.
The current-voltage curve of the single-layer molybdenum disulfide electrostatic self-doped diode prepared in example 1 is shown in fig. 2. As can be seen from the graph of FIG. 2, the device exhibits obvious rectification characteristics under positive and negative bias conditions, which proves that the method successfully constructs an electrostatic self-doping diode. In the device test process, the source 4 is grounded, and the drain 2 is used as a driving voltage end to apply bias voltage.
The current-voltage curve of the single-layer molybdenum disulfide electrostatic self-doped diode prepared in example 1 under the dark condition is shown in fig. 3. As can be seen from the curve of FIG. 3, under the illumination condition, the current is significantly increased, and the current is increased by 7 orders of magnitude when the reverse bias is performed (i.e., the ratio of light to dark current is 10) 7 ) It is shown that the electrostatic self-doping diode can be used as a light-operated switch.
The rectification ratio of the single layer molybdenum disulfide electrostatic self-doped diode prepared in example 1 is shown in the graph of fig. 4 along with time. As can be seen from the graph of fig. 4, the rectifying characteristics of the device hardly degraded within 30 days.
Example 2
Preparing a few-layer tungsten disulfide electrostatic self-doped diode:
(1) Preparing a two-dimensional semiconductor layer 5 (few-layer tungsten disulfide nanosheets) by using a mechanical stripping method: adhering a 3M blue film adhesive tape on a tungsten disulfide block, slowly tearing off the tape, then, leaving a plurality of layers of tungsten disulfide materials on the adhesive tape, then, pressing the adhesive tape with a tungsten disulfide sheet on a silicon wafer, slowly tearing off the adhesive tape, leaving a few layers of tungsten disulfide nanosheets on the silicon wafer, repeating the previous operation for a plurality of times to obtain tungsten disulfide nanosheets with different thicknesses, wherein the tungsten disulfide nanosheets with the thickness of 2 nm are selected as the two-dimensional semiconductor layer.
(2) Preparing a few-layer boron nitride nanosheet by using a mechanical stripping method: adhering a 3M blue film adhesive tape on a boron nitride crystal, slowly tearing off the adhesive tape, then, remaining a plurality of layers of boron nitride materials on the adhesive tape, then, pressing the adhesive tape with a boron nitride sheet on a silicon wafer, slowly tearing off the adhesive tape, leaving a few layers of boron nitride nanosheets on the silicon wafer, repeating the previous operation for multiple times to obtain the boron nitride nanosheets with different thicknesses, wherein the boron nitride nanosheets with the thickness of 25nm are selected as the dielectric layer 3 in the embodiment.
(3) Pre-deposition of a drain electrode: and spin-coating a layer of PMMA colloid on the insulating substrate 1, drying the PMMA colloid for 1min at 180 ℃, carrying out patterning treatment by using an electron beam exposure technology, and depositing a metal electrode by using a thermal evaporation process, wherein the electrode material is pure gold, so that the pre-deposition of the drain electrode 2 is completed, and the thickness is 50nm.
(4) The dielectric layer 3 partially covers the drain 2: spin-coating PPC colloid on a silicon wafer with boron nitride nanosheets, drying at 100 ℃ for 1min to form a PPC film with the thickness of 500nm, slowly peeling off the PPC film with the boron nitride from the silicon wafer by means of a 3M adhesive tape, stacking the PPC film on a pre-deposited drain electrode 2 through an accurate transfer platform with an optical microscope to complete local coverage of a dielectric layer 3, wherein the thickness of the dielectric layer 3 is 25nm.
(5) Assembling of the two-dimensional semiconductor layer 5: spin-coating PPC colloid on a silicon wafer with few layers of tungsten disulfide nano sheets, drying at 100 ℃ for 1min to form a PPC film with the thickness of 500nm, slowly uncovering the PPC film with boron nitride from the silicon wafer by means of a 3M adhesive tape, precisely stacking the tungsten disulfide nano sheets on the PPC film on the upper surface of a dielectric layer 3 and contacting with a drain electrode 2 by using a precise transfer platform, and then putting the dielectric layer into an acetone solution to remove the residual PPC colloid, thereby completing the assembly of a two-dimensional semiconductor layer 5 as a conductive channel material.
(6) And (4) depositing a source electrode: and depositing a metal electrode on one side of the few-layer tungsten disulfide as a source electrode 4 by using an electron beam exposure technology and a thermal evaporation process, wherein the electrode material is pure gold and the thickness is 50nm, and finally completing the few-layer tungsten disulfide electrostatic self-doped diode.
The current-voltage curve of the few-layer tungsten disulfide electrostatic self-doped diode prepared in example 2 is shown in fig. 5. As can be seen from the curve of FIG. 5, the device also exhibits obvious rectification characteristics under the positive and negative bias conditions, which proves that the method is also suitable for the few-layer tungsten disulfide nanosheets. In the device test process, the source 4 is grounded, and the drain 2 is used as a driving voltage end to apply bias voltage.
Comparative example 1
To demonstrate that the implementation of an electrostatically autodoped diode benefits from an extended drain, the present invention devised a comparative experiment without an extended drain.
The schematic structural diagram of the device in this comparative experiment is shown in fig. 6, where 1 is an insulating substrate, 2 is a drain, 3 is a dielectric layer, 4 is a source, and 5 is a two-dimensional semiconductor layer.
Preparation of comparative example device:
(1) Preparing a two-dimensional semiconductor layer 5 (few-layer tungsten disulfide nanosheets) by using a mechanical stripping method: adhering a 3M blue film adhesive tape on a tungsten disulfide block, slowly tearing off the tape, then, leaving a plurality of layers of tungsten disulfide materials on the adhesive tape, then, pressing the adhesive tape with a tungsten disulfide sheet on a silicon wafer, slowly tearing off the adhesive tape, leaving a few layers of tungsten disulfide nanosheets on the silicon wafer, repeating the previous operation for a plurality of times to obtain tungsten disulfide nanosheets with different thicknesses, wherein the tungsten disulfide nanosheets with the thickness of 2 nm are selected as the two-dimensional semiconductor layer 5 in the comparative example.
(2) Preparing a few-layer boron nitride nanosheet by using a mechanical stripping method: and adhering a 3M blue film adhesive tape on the boron nitride crystal, slowly tearing off the adhesive tape, then, remaining a plurality of layers of boron nitride materials on the adhesive tape, pressing the adhesive tape with the boron nitride thin slice on a silicon wafer, slowly tearing off the adhesive tape, remaining a few layers of boron nitride nanosheets on the silicon wafer, repeating the previous step for multiple times to obtain the boron nitride nanosheets with different thicknesses, wherein the boron nitride nanosheets with the thickness of 25nm are selected as the dielectric layer 3 in the comparative example.
(3) Dielectric layer 3 is stacked on insulating substrate 1: spin-coating PPC colloid on a silicon wafer with a boron nitride nanosheet, drying at 100 ℃ for 1min to form a PPC film with the thickness of 500nm, slowly tearing off the PPC film with the boron nitride from the silicon wafer by means of a 3M adhesive tape, and stacking the PPC film on an insulating substrate 1 through an accurate transfer platform with an optical microscope, wherein the thickness of a dielectric layer 3 is 25nm.
(4) Pre-deposition of the drain 2: and (2) spinning and coating a layer of PMMA colloid on an insulating substrate 1 with a dielectric layer 2, drying for 1min at 180 ℃, carrying out patterning treatment by using an electron beam exposure technology, depositing a metal electrode by using a thermal evaporation process, wherein the electrode material is pure gold, and pre-depositing the drain electrode 5 on one side of the edge of the dielectric layer, and the thickness of the drain electrode is 50nm.
(5) Assembling of the two-dimensional semiconductor layer 5: spin-coating PPC colloid on a silicon wafer with few layers of tungsten disulfide nano sheets, drying at 100 ℃ for 1min to form a PPC film with the thickness of 500nm, slowly uncovering the PPC film with boron nitride from the silicon wafer by means of a 3M adhesive tape, precisely stacking the tungsten disulfide nano sheets on the PPC film on the upper surface of a dielectric layer 3 and contacting with a drain electrode 2 by using a precise transfer platform, and then putting the dielectric layer into an acetone solution to remove the residual PPC colloid, thereby completing the assembly of a two-dimensional semiconductor layer 3 as a conductive channel material.
(6) And (4) depositing a source electrode: and depositing a metal electrode on one side of the few-layer tungsten disulfide as a source electrode 4 by using an electron beam exposure technology and a thermal evaporation process, wherein the electrode is made of pure gold and has the thickness of 50nm, and finally, the construction of few-proportion devices is completed.
The current-voltage curve of the device prepared in comparative example 1 is shown in fig. 7. As can be seen from the graph of fig. 7, symmetric output characteristics are exhibited under the positive and negative bias conditions of the device, which proves that the device without the extended drain cannot achieve the diode performance. In the device test process, the source 4 is grounded, and the drain 2 is used as a driving voltage end to apply bias voltage.
The above-described embodiments are merely illustrative of the preferred embodiments of the present invention, and do not limit the scope of the present invention, and various modifications and improvements of the technical solutions of the present invention can be made by those skilled in the art without departing from the spirit of the present invention, and the technical solutions of the present invention are within the scope of the present invention defined by the claims.
Claims (5)
1. An electrostatic self-doping diode, the structure comprising: the transistor comprises an insulating substrate (1), a drain electrode (2), a dielectric layer (3), a two-dimensional semiconductor layer (5) and a source electrode (4); wherein the drain electrode (2) is positioned above the insulating substrate (1), the dielectric layer (3) partially covers the drain electrode (2), the two-dimensional semiconductor layer (5) is positioned above the dielectric layer (3) and is in contact with the drain electrode (2), and the source electrode (4) is positioned above the two-dimensional semiconductor layer (5);
the material of the two-dimensional semiconductor layer (5) is a semiconductor material with a band gap;
the insulating substrate (1) comprises: a silicon wafer with an oxide layer, a flexible insulating PET or sapphire substrate;
the material of the drain electrode (2) comprises: gold, chromium or graphene, with a thickness of 50-80nm; the source electrode (4) is a metal electrode, and the thickness is 1-80nm;
the material of the dielectric layer (3) comprises: two-dimensional layered boron nitride, silicon oxide, aluminum oxide or hafnium oxide with a thickness of 20-50nm;
the semiconductor material with the band gap is a two-dimensional transition metal chalcogenide nanosheet;
the two-dimensional transition metal chalcogenide nanoplatelets comprise: molybdenum disulfide, molybdenum diselenide, tungsten disulfide, tungsten diselenide, or molybdenum ditelluride, with a thickness of 0.7-10nm.
2. A method for preparing an electrostatic self-doping diode according to claim 1, comprising the steps of:
(1) -depositing the drain electrode (2) on the insulating substrate (1);
(2) -locally growing said dielectric layer (3) on said drain (2);
(3) Assembling the two-dimensional semiconductor layer (5) over the dielectric layer (3) and in contact with the drain electrode (2);
(4) And depositing the source electrode (4) above the two-dimensional semiconductor layer (5) to complete the construction of the electrostatic self-doping diode.
3. The method of claim 2, wherein the deposition in step (1) and step (4) is performed by: patterning by using an electron beam exposure process or an ultraviolet exposure process, and then depositing by using a thermal evaporation process; the growing method in the step (2) comprises the following steps: a dry transfer process or an atomic layer deposition process; the assembly method in step (3) is a wet transfer process.
4. The preparation method according to claim 3, wherein the dry transfer process comprises the following specific steps: spin-coating PPC glue on the substrate with the dielectric layer (3) material, and drying to obtain a PPC film with the dielectric layer (3) material and the thickness of 1-3 μm; and transferring the PPC film with the dielectric layer (3) material from the substrate to the position above the drain electrode (2), drying at 100 ℃ for 30min, immersing in an acetone solution to remove the PPC glue, and finishing the transfer.
5. The preparation method according to claim 3, wherein the specific steps of the wet transfer process comprise: and (3) spin-coating PMMA glue on the substrate with the two-dimensional semiconductor layer (5) material, drying at 120 ℃ for 1-2min to obtain a PMMA film with the two-dimensional semiconductor layer (5) material, transferring the PMMA film with the two-dimensional semiconductor layer (5) material to the position above the dielectric layer (3) by using a wet method, contacting with the drain electrode (2), immersing in an acetone solution to remove the PMMA glue, and finishing the transfer.
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