CN107634099A - A kind of two dimensional crystal material FET and preparation method thereof - Google Patents
A kind of two dimensional crystal material FET and preparation method thereof Download PDFInfo
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Abstract
The present invention discloses a kind of two dimensional crystal material FET, including：Semiconductor substrate, dielectric layer, metal gates, gate dielectric layer, channel layer, graphene layer, two dimensional crystal protective layer and source, drain electrode.The invention also discloses a kind of method for manufacturing two dimensional crystal material FET, two dimensional crystal material autoregistration is grown directly upon on gate dielectric layer, using the graphene of doping as source and drain, and connects metal as source, drain electrode to prepare FET.Two dimensional crystal material FET proposed by the present invention and preparation method thereof, utilize conventional cmos processing procedure, the FET with stable two dimensional crystal material film property can be manufactured, realizes and prepares small size, the final purpose of large-scale two dimensional crystal FET array.
Description
Technical field
The invention belongs to semiconductor integrated circuit manufacturing process technology field, in particular it relates to a kind of two dimensional crystal material
FET and preparation method thereof.
Background technology
As feature sizes of semiconductor devices presses Moore's Law Scaling, chip integration is improved constantly, and tradition is based on
Silicon semiconductor device has been difficult to meet the performance and power consumption requirements of device and circuit again due to technological limits and various negative effects.
Domestic and international major scientific research institution and semiconductor maker study various new materials and new device structure one after another, existing to substitute
Silicon semiconductor device.Wherein, two dimensional crystal material can replace silicon raceway groove to prepare semiconductor devices and integrated circuit.In recent years
Two dimensional crystal material prepares transistor technology development rapidly, and two dimensional crystal material refers to individual layer bi-dimensional cellular shape network
(similar graphene), the material for having electronic energy band gap (can switch) and high electron mobility.It includes：Silene, germanium alkene are black
Phosphorus, tin alkene, triazine radical graphite phase carbon nitride etc..These two dimensional crystal materials compare graphene, with electronic energy band gap and well
Switch performance, can directly prepare transistor, its performance is far more than existing silicon transistor, will turn into below 7nm most before
The novel transistor of scape.
The technological difficulties for preparing two-dimensional material FET at present have two：1) because two dimensional crystal material film is in air
Middle unstable chemcial property, it is easy to decomposed by the oxygen in air and aqueous vapor, therefore, needed during scene effect control is standby
Ensure that two dimensional crystal material is not exposed in air.2) preparation of two dimensional crystal material film must be in specific growth substrates
On, the CMOS technology of its technique and routine is incompatible, it is difficult to prepare small size, large-scale two dimensional crystal material FET
Array.
It is, therefore, desirable to provide a kind of two dimensional crystal material FET and preparation method thereof, utilizes conventional cmos processing procedure, system
The FET with stable two dimensional crystal material film property is made, realizes manufacture small size, large-scale two dimensional crystal field
The final purpose of effect pipe array.
The content of the invention
The technical problems to be solved by the invention are to utilize conventional cmos processing procedure, and manufacture is with stable two dimensional crystal material
The FET of property of thin film, realize manufacture small size, the final purpose of large-scale two dimensional crystal FET array.
In order to solve the above technical problems, the present invention proposes a kind of two dimensional crystal material FET, including：Semiconductor serves as a contrast
Bottom；Dielectric layer, in the Semiconductor substrate；Metal gates, in the groove of the dielectric layer；Gate dielectric layer, position
Above the metal gates；Channel layer, above the gate dielectric layer；Graphene layer, positioned at the channel layer both sides,
Source, drain region are formed after graphical and doping；Two dimensional crystal protective layer, above the channel layer and graphene layer；Source, electric leakage
Pole, in the two dimensional crystal protective layer groove of the metal gates both sides, connection source, drain region, it is characterised in that the raceway groove
Layer is made up of two dimensional crystal material film；
Optionally, the metal gates are by a kind of independent or multiple combinations structure in material W, Ag, Cu, Al, TiN, TiAl
Into；
Optionally, the gate dielectric layer is by material h-BN, ZrB2, β-Si3N4, one kind in SiC individually or multiple combinations
Form；
Optionally, the two dimensional crystal protective layer is by material Si3N4、SiO2、Al2O3One of form；
Optionally, the constituent material of channel layer thin film is silene, or germanium alkene, or black phosphorus, or tin alkene, or triazine radical graphite-phase
Carbonitride, or the combination of above-mentioned material；
Preferably, the channel layer can form single thin film by one of described material, can also be formed by different materials
Plural layers；
Preferably, the two dimensional crystal material film of the channel layer is formed, every layer of thickness is the thickness of 3-20 layer atoms.
The invention also provides a kind of preparation method of two dimensional crystal material FET, step includes：
S01：Semiconductor substrate and dielectric layer are provided, groove is formed on the dielectric layer；
S02：Deposited metal gate material in groove, the metal gate electrode outside groove is then removed by glossing
Material；
S03：Semiconductor substrate surface deposits gate dielectric layer, then gate dielectric layer is only retained by photoetching, etching technics
In metal gates upper surface；
S04：Semiconductor substrate surface covers graphene layer；
S05：The graphene layer of metal gate both sides is doped to form source-drain area, chemical wet etching is removed on metal gates
Graphene layer, expose gate dielectric layer；
S06：Autoregistration grows channel layer two dimensional crystal film on gate dielectric layer；
S07：Deposit two dimensional crystal protective layer；
S08：Photoetching, the two dimensional crystal protective layer for etching source-drain area, then deposited metal, source-drain electrode is formed after polishing；
Optionally, the graphene layer doping P of metal gate both sides described in step S05, or B, or Se form source-drain area；
Optionally, the growth channel layer two dimensional crystal film described in step S06 and S07 and deposition two dimensional crystal protective layer exist
Completed in same equipment.
The invention provides a kind of two dimensional crystal material FET and preparation method thereof, the device is as shown in Figure 1.
Etched recesses 103 in dielectric layer 102 in Semiconductor substrate 101, depth is in 40-150nm；By in conventional cmos processing procedure
Metal deposition and glossing are filled in groove with the group of a kind of metal or various metals in W, Ag, Cu, Al TiN, TiAl
104 are closed, as metal gates；Deposited again in wafer surface by material：h-BN、ZrB2, β-Si3N4Or the one or more in SiC
The gate dielectric layer 105 formed is combined, thickness makes gate dielectric layer be only remained in metal gate in 2-10nm, and with photoetching, etching technics
Pole upper surface；The technique for depositing or shifting followed by graphene in the prior art forms graphene layer 106 in wafer surface,
Thickness is in 5-30nm；Then, the graphene layer incorporation P of metal gate both sides, or B, or Se, the source-drain area of N-type or p-type, figure are formed
Etching removes the graphene layer on metal gates after shape, exposes gate dielectric layer；Autoregistration growth two dimension is brilliant on gate dielectric layer
The channel layer 107 of body material film, two dimensional crystal material film can be the silenes of individual layer, germanium alkene, black phosphorus, tin alkene, triazine radical
The multiple-level stack of graphite phase carbon nitride film or above-mentioned material film, then deposited on whole chip by Si3N4、
SiO2Or Al2O3The two dimensional crystal protective layer 108 of composition, thickness range enter to the channel layer of two dimensional crystal material in 50-200nm
Row protection, prevent its exposure in atmosphere；Finally, in the two dimensional crystal protective layer etched recesses 109 of the metal gates both sides
And fill with metal used in conventional cmos processing procedure, form source, drain electrode.
The FET of the present invention, using metal gates, as source-drain area and connected using the graphene of doping with metal shape
Cheng Yuan, drain electrode.There are two effects using graphene：First, graphene is used as source-drain area by doping；Second, graphene is located at two
The both sides of crystal film are tieed up, play a part of isolation protection.The channel layer of device of the present invention is made up of two dimensional crystal material, and it is moved
Shifting rate and performance are better than silicon raceway groove, and the material of two dimensional crystal Material growth substrate can be used as by selection：h-BN、ZrB2, β-
Si3N4Or SiC, as gate dielectric material, enable on two dimensional crystal film autoregistration direct growth gate dielectric layer, and pass through
The process equipment of the conventional cmos processing procedure such as epitaxial diposition, realize in the same apparatus, in order grow two dimensional crystal material and
Two dimensional crystal protective layer.Because the conventional cmos such as epitaxial device equipment needs to vacuumize before technique starts, low pressure work is used again
Skill, can avoid two dimensional crystal material film formed after exposure in atmosphere, solve it and easily decomposed with air contact and caused
Performance it is unstable the problem of, while used preparation technology with routine CMOS technology it is compatible, its preparation method simply may be used
OK, small size, large-scale two dimensional crystal FET array can be prepared.
In summary, two dimensional crystal material FET proposed by the present invention and preparation method thereof, CMOS processing procedures, system are utilized
The FET with stable two dimensional crystal material film property is made, realizes manufacture small size, large-scale two dimensional crystal
The final purpose of FET array.
Brief description of the drawings
Fig. 1 is for the structural representation of two dimensional crystal material FET proposed by the present invention.
Fig. 2 is for the schematic flow sheet of two dimensional crystal material field-effect tube preparation method proposed by the present invention.
Fig. 3~Figure 10 be in the embodiment of the present invention two dimensional crystal material field-effect control for processing step schematic diagram.
Embodiment
To make present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is made into one
Walk explanation.Certainly the invention is not limited in the specific embodiment, the general replacement known to those skilled in the art
Cover within the scope of the present invention.
Secondly, the present invention carries out detailed statement using schematic diagram, when present example is described in detail, for convenience of description,
Schematic diagram, should not be in this, as limitation of the invention not according to general proportion partial enlargement.
The flow of two dimensional crystal material field-effect tube preparation method described in the present embodiment is solved one by one in conjunction with accompanying drawing 2
Analysis.The two dimensional crystal material FET of the present embodiment, including：Semiconductor substrate, the medium in the Semiconductor substrate
Layer；Metal gates in the groove of the dielectric layer；Gate dielectric layer, above the metal gates；Channel layer, position
Above the gate dielectric layer, the channel layer includes one layer of two dimensional crystal material；Graphene layer, positioned at the channel layer two
Side, two dimensional crystal protective layer, above the channel layer and graphene layer；Source, drain electrode, two positioned at the grid both sides
Tie up in crystal protective layer groove, above graphene layer.
The metal gate material of the present embodiment device is Cu, and gate dielectric layer material is ZrB2, and two dimensional crystal material is silicon
Alkene, for its film atomic layer level thickness at 5 layers, two dimensional crystal protective layer material is Si3N4。
S01：Semiconductor substrate and dielectric layer are provided, groove is formed on the dielectric layer.
As shown in Figure 3, there is provided Semiconductor substrate 201 and dielectric layer 202, groove is formed on the dielectric layer 202
203；In the present embodiment, the depth of groove 203 is 60nm.
S02：Deposited metal gate material in groove, the metal gate electrode outside groove is then removed by glossing
Material.
As shown in Figure 4, the deposited metal grid material 204 in groove 203, and removed with glossing outside groove 203
The metal gate material in portion；In the present embodiment, metal gate material Cu.
S03:Semiconductor substrate surface deposits gate dielectric layer, then gate dielectric layer is only retained by photoetching, etching technics
In metal gates upper surface.
As shown in Figure 5, gate dielectric layer 205 is deposited in semiconductor substrate surface, and makes gate medium with photoetching, etching technics
Layer 205 is only remained in the upper surface of metal gates 204；In the present embodiment, metal gates dielectric layer material is ZrB2, thickness is
7nm。
S04:Semiconductor substrate surface covers graphene layer.
As shown in Figure 6, deposit or shift graphene layer 206 ' in semiconductor substrate surface；In the present embodiment, use
Graphene film is covered in the upper surface of chip by the method for graphene transfer, and the thickness of graphene is in 10nm.
S05:The graphene layer of metal gate both sides is doped to form source-drain area, chemical wet etching is removed on metal gates
Graphene layer, expose gate dielectric layer.
As shown in Figure 7, the graphene layer 206 of metal gate both sides is doped to form source-drain area, chemical wet etching removes
Graphene layer on metal gates, expose gate dielectric layer 205；In the present embodiment, graphene can adulterate B.
S06:Autoregistration grows channel layer two dimensional crystal film on gate dielectric layer.
As shown in Figure 8, the autoregistration growth channel layer two dimensional crystal film 207 on gate dielectric layer 205；In the present embodiment
For silene, silylene film is deposited the two dimensional crystal material used using epitaxial growth method, and its atomic layer level thickness is 5 layers.
S07:Deposit two dimensional crystal protective layer.
As shown in Figure 9, two dimensional crystal protective layer 208 is deposited；In the present embodiment, two dimensional crystal protective layer is Si3N4,
Thickness in 100nm, using with deposit protective layer in 207 same epitaxial growth equipment of two dimensional crystal film.
S08:Photoetching, the two dimensional crystal protective layer for etching source-drain area, then deposited metal, source-drain electrode is formed after polishing.
As shown in Figure 10, photoetching, the two dimensional crystal protective layer 208 of etching source-drain area, and formed after deposited metal, polishing
Source-drain electrode 209；In the present embodiment, the material of source-drain electrode is Cu.
It should be noted that：In the present embodiment device：
1. channel layer in actual applications, can be adopted only with one layer of two dimensional crystal film according to the needs of device performance
Stacked by the use of different two dimensional crystal material films and be used as channel layer；
2. metal gates, in actual applications, can be according to device parameters work function only with a kind of metal material Cu
Need that one or more metal materials in W, Ag, Cu, Al, TiN, TiAl can be used；
3. gate dielectric layer is only with h-BN, ZrB2, β-Si3N4, one kind in SiC, in actual applications, can be according to device
The needs of the equivalent oxide thickness (EOT) of part use one or more materials.
Foregoing description is only the description to the embodiment of the present invention, not to any restriction of the scope of the invention, present invention neck
Any change, the modification that the those of ordinary skill in domain does according to the disclosure above content, belong to the protection domain of claims.
Claims (10)
1. a kind of two dimensional crystal material FET, including：Semiconductor substrate；Dielectric layer, in the Semiconductor substrate；Gold
Belong to grid, in the groove of the dielectric layer；Gate dielectric layer, above the metal gates；Channel layer, positioned at described
Above gate dielectric layer；Graphene layer, positioned at the channel layer both sides, source, drain region are formed after graphical and doping；Two dimensional crystal
Protective layer, above the channel layer and graphene layer；Source, drain electrode, the two dimensional crystal positioned at the metal gates both sides
In protective layer groove, connection source, drain region, it is characterised in that the channel layer is made up of two dimensional crystal material film.
2. two dimensional crystal material FET as claimed in claim 1, it is characterised in that the metal gates by material W,
One kind in Ag, Cu, Al, TiN, TiAl is individually or multiple combinations are formed.
3. two dimensional crystal material FET as claimed in claim 1, it is characterised in that the gate dielectric layer is by material h-
BN、ZrB2, β-Si3N4, one kind in SiC individually or multiple combinations are formed.
4. two dimensional crystal material FET as claimed in claim 1, it is characterised in that the two dimensional crystal protective layer is by material
Expect Si3N4、SiO2、Al2O3One of form.
5. two dimensional crystal material FET as claimed in claim 1, it is characterised in that the constituent material of channel layer thin film is
Silene, or germanium alkene, or black phosphorus, or tin alkene, or triazine radical graphite phase carbon nitride, or the combination of above-mentioned material.
6. two dimensional crystal material FET as claimed in claim 5, it is characterised in that the channel layer is by the material
One of form single thin film, or form plural layers by different materials.
7. the two dimensional crystal material FET as described in claim 5 or claim 6, it is characterised in that form the ditch
The two dimensional crystal material film of channel layer, every layer of thickness are the thickness of 3-20 layer atoms.
8. a kind of preparation method of two dimensional crystal material FET, step include：
S1：Semiconductor substrate and dielectric layer are provided, groove is formed on the dielectric layer；
S2：Deposited metal gate material in groove, the metal gate electrode material outside groove is then removed by glossing；
S3：Semiconductor substrate surface deposits gate dielectric layer, then gate dielectric layer is only remained in metal by photoetching, etching technics
Gate upper surface；
S4：Semiconductor substrate surface covers graphene layer；
S5：The graphene layer of metal gate both sides is doped to form source-drain area, chemical wet etching removes the graphite on metal gates
Alkene layer, exposes gate dielectric layer；
S6：Autoregistration grows channel layer two dimensional crystal film on gate dielectric layer；
S7：Deposit two dimensional crystal protective layer；
S8：Photoetching, the two dimensional crystal protective layer for etching source-drain area, then deposited metal, source-drain electrode is formed after polishing.
9. the preparation method of two dimensional crystal material FET as claimed in claim 8, it is characterised in that golden described in step S5
Belong to the graphene layer doping P of grid both sides, or B, or Se forms source-drain area.
10. the preparation method of two dimensional crystal material FET as claimed in claim 8, it is characterised in that step S6 and S7 institutes
The growth channel layer two dimensional crystal film and deposition two dimensional crystal protective layer stated are completed in same equipment.
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