CN111584672B - Indium column of infrared focal plane detector and preparation method thereof - Google Patents
Indium column of infrared focal plane detector and preparation method thereof Download PDFInfo
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- CN111584672B CN111584672B CN202010329369.2A CN202010329369A CN111584672B CN 111584672 B CN111584672 B CN 111584672B CN 202010329369 A CN202010329369 A CN 202010329369A CN 111584672 B CN111584672 B CN 111584672B
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- 229910052738 indium Inorganic materials 0.000 title claims abstract description 114
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 title claims abstract description 114
- 238000002360 preparation method Methods 0.000 title claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 50
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 39
- 238000004528 spin coating Methods 0.000 claims abstract description 27
- BDAGIHXWWSANSR-UHFFFAOYSA-N methanoic acid Natural products OC=O BDAGIHXWWSANSR-UHFFFAOYSA-N 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 14
- OSWFIVFLDKOXQC-UHFFFAOYSA-N 4-(3-methoxyphenyl)aniline Chemical compound COC1=CC=CC(C=2C=CC(N)=CC=2)=C1 OSWFIVFLDKOXQC-UHFFFAOYSA-N 0.000 claims abstract description 11
- 230000008021 deposition Effects 0.000 claims abstract description 11
- 235000019253 formic acid Nutrition 0.000 claims abstract description 11
- 238000002207 thermal evaporation Methods 0.000 claims abstract description 6
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 30
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 30
- 238000004140 cleaning Methods 0.000 claims description 30
- 238000001259 photo etching Methods 0.000 claims description 25
- 239000003292 glue Substances 0.000 claims description 22
- 238000007747 plating Methods 0.000 claims description 20
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 20
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 15
- 230000037452 priming Effects 0.000 claims description 13
- 238000011161 development Methods 0.000 claims description 11
- 238000004026 adhesive bonding Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 10
- 239000010953 base metal Substances 0.000 claims description 9
- 238000002791 soaking Methods 0.000 claims description 8
- 238000001771 vacuum deposition Methods 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 5
- 239000008367 deionised water Substances 0.000 claims description 5
- 229910021641 deionized water Inorganic materials 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 238000009736 wetting Methods 0.000 claims description 5
- 238000005566 electron beam evaporation Methods 0.000 claims description 3
- 238000005406 washing Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 17
- 150000001875 compounds Chemical class 0.000 abstract 1
- 238000010894 electron beam technology Methods 0.000 abstract 1
- 238000001465 metallisation Methods 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 238000003384 imaging method Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
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- 238000010586 diagram Methods 0.000 description 2
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- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
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- 238000001459 lithography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention relates to a method for preparing indium column of infrared focal plane detector and indium column prepared by the method, the method of the invention firstly spin-coats thin photoresist on the surface of the chip, carries on one-time alignment aiming at the center of pixel or reading unit electrode, prepares round bottoming metal deposition hole, evaporates and evaporates the compound metal film through electron beam, adopts wet stripping mode to obtain bottoming metal pattern array; then spin-coating photoresist with medium thickness, aligning the center of the underlying metal pattern, carrying out secondary alignment, preparing a square indium column deposition hole, depositing an indium film by vacuum thermal evaporation, and obtaining an indium column by adopting a wet stripping process; and finally, shrinking the balls in a reflow furnace in a formic acid atmosphere to obtain the indium column array with the large height-to-width ratio. The overall process difficulty of the invention is lower than that of the existing mode, the size of the prepared indium column can meet the requirement, the size uniformity is higher, the surface of the indium column is uniform and smooth, and the consistency requirement of the flip interconnection process can be completely met.
Description
Technical Field
The invention relates to the technical field of infrared detectors, in particular to an indium column of an infrared focal plane detector and a preparation method thereof.
Background
The infrared focal plane array (IRFPA) detector has the functions of radiation sensitivity, charge storage, multiplex transmission and the like, is a plane array detector which is positioned on the focal plane of an optical system and provided with a signal processing circuit and is adopted by a second generation staring type infrared thermal imaging system, the number of detection units of the plane array detector is higher than that of a first generation detector by more than 3 orders of magnitude, the fast electric scanning imaging, the identification and the tracking of a target are realized through a Flip-Chip technology and a CMOS (complementary metal oxide semiconductor) reading circuit technology, and the plane array detector is widely applied to weapon equipment such as infrared guidance, tracking, staring imaging and the like. In recent years, the concept of the third-generation infrared detector with the technical characteristics of high detection rate, large area array, low cost and multispectral is gradually proposed, and the important development trend of the infrared detector is that the specifications of the detector are continuously increased (an ultra-large area array and ultra-small pixels) and the difficulty of the preparation process is reduced based on the flip process and the reading circuit technology of the second generation.
Hybrid focal plane detectors are a core device of modern imaging systems. For the hybrid focal plane detector, the sensitive element chip and the signal reading circuit are respectively developed, and then the units are electrically interconnected one by one. The advantage is that the preparation process is relatively simple and flexible, but also brings about complex interconnection problems. At present, an indium column flip interconnection process is generally adopted in the development of a hybrid focal plane device, indium columns are arranged on the surfaces of a detector array and a reading circuit according to a grid array shape, sensitive elements are directly mounted on the reading circuit in a flip mode, high-density electrical connection is achieved through the indium columns and the indium columns on the reading circuit, and the development requirements of large-scale area array focal planes can be met. At present, the processing of indium columns mainly adopts two modes: one is made by diffusion to form a junction, and the other is obtained by epitaxial growth.
With the increasing of the application end to the detector array scale and the imaging resolution, the pixel center distance is reduced continuously, and the requirement that the transverse size of the indium column is reduced along with the short circuit between pixels caused by the deformation of the indium column is avoided, so that the height of the indium column obtained by direct growth is reduced rapidly. Two problems thus arise: 1) as the height of the indium column is reduced, the interconnection leveling tolerance of the chip is reduced, and a small leveling deviation during interconnection can cause the interconnection failure of a part of the area at one side of the sensitive element, and the unevenness compensation capability of the chip is poor, so that the communication rate of the pixel is deteriorated; 2) the ability of relieving shear deformation caused by thermal mismatch between the sensitive chip and the read-out circuit chip is poor, the reliability of the device for resisting thermal shock is reduced, and the fatigue life is shortened. Therefore, the indium columns with the large height-to-width ratio can obviously reduce the blind pixel rate of the focal plane device and improve the reliability of the device, and the indium columns with the large height-to-width ratio have very important significance for developing larger-scale high-resolution detection devices. However, the conventional method generally adopts a thick photoresist lithography process to increase the height of the indium columns, but the thick photoresist process causes the dimensional uniformity of the indium columns to be poor, and as the area array density increases, the thick photoresist is more difficult to strip.
Disclosure of Invention
The invention provides an indium column of an infrared focal plane detector and a preparation method thereof, aiming at the technical problems in the prior art, the whole process difficulty is lower than that of the existing mode, the size of the prepared indium column can meet the requirement, the size uniformity is higher, the surface of the indium column is uniform and smooth, and the consistency requirement of an inverted interconnection process can be completely met.
The technical scheme for solving the technical problems is as follows: a method for preparing indium columns of an infrared focal plane detector comprises the following steps:
1) gluing the chip: cleaning the surface of the chip, removing residual moisture, and spin-coating a layer of photoresist on the surface of the chip;
2) etching a mask: spacing circular photoetching holes on a mask plate according to the spacing size parameters of the indium columns, then covering the mask plate on the chip coated with the glue in the step 1), carrying out first photoetching exposure, and then developing and fixing;
3) plating a base metal: plating base metal on the surface of the chip treated in the step 2) by adopting a vacuum coating mode, then cleaning the photoresist, and stripping redundant metal;
4) gluing again: spin-coating a layer of photoresist on the surface of the chip treated in the step 3) again;
5) And (5) mask etching again: spacing square photoetching holes on a mask plate according to the spacing size parameters of the indium columns, then covering the mask plate on the chip coated with the glue in the step 4), carrying out secondary photoetching exposure, and then developing and fixing;
6) plating indium columns: plating an indium film on the surface of the chip processed in the step 5) by adopting a vacuum plating mode, then cleaning the photoresist, and stripping redundant indium to obtain a chip with indium columns;
7) and (3) ball backflow and shrinkage: and (3) reflowing the chip with the indium columns obtained in the step 6) in a vacuum reflow furnace to shrink balls so that the indium columns are changed into an ellipsoid from a square shape, and thus obtaining indium column finished products.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, in the step 1), the chip is cleaned by respectively ultrasonically cleaning the chip for 3 minutes by sequentially using acetone and isopropanol, and then washing the chip by using deionized water.
Further, in the step 1), the surface of the chip is spin-coated with AZ5214 type photoresist, a spin coater is adopted for spin coating, the rotation number is 4000 rpm, the spin coating time is 30 seconds, and the chip is placed after being coated with the photoresist and is heated for 90 seconds at the temperature of 95 ℃; in the step 4), the surface of the chip is spin-coated with AZ4620 type photoresist, a spin coater is adopted for spin coating, the rotation speed is 1000 rpm, the spin coating time is 40 seconds, and after the photoresist is coated, the chip is placed and heated for 180 seconds at the temperature of 100 ℃.
Further, in the step 2), the diameter of the circular photoetching hole is 5 μm; in the step 5), the size of the square photoetching hole is 10 microns multiplied by 10 microns.
Preferably, in the step 2), the exposure dose is controlled to be 58.2 to 60.5 mJ per square centimeter, the exposed chip is placed into a tetramethylammonium hydroxide developing solution with the concentration of 2.38 percent for development for 45 to 55 seconds, and then the pure water is used for fixing for 30 to 40 seconds; in the step 5), the exposure dose is controlled to be 396.9-405.7 joules per square centimeter, the exposed chip is placed into a tetramethylammonium hydroxide developing solution with the concentration of 2.38% for development for 100-120 seconds, and then pure water is used for fixing for 30-40 seconds.
Preferably, in the step 3), an electron beam evaporation device is adopted, the priming metal is plated in a vacuum deposition mode, the deposition rate is controlled to be 0.2 nanometer per second, and the working vacuum degree is controlled to be 5 multiplied by 10-6Pascal, in the step 3), the priming metal comprises a 50nm metal titanium adhesion layer, a 30nm metal platinum barrier layer and an 80nm metal gold wetting layer which are deposited in sequence.
Further, in the step 4), the photoresist needs to be soaked in acetone for 30-60 minutes and then washed by isopropanol; in the step 6), the photoresist needs to be soaked in acetone for 90-120 minutes and then washed by isopropanol.
Further, in the step 6), indium is deposited on the indium-plated film by adopting a vacuum thermal evaporation method, and the deposition thickness is 6 μm.
Further, in the step 7), the reflow ball shrinking needs to heat the chip with the indium columns obtained in the step 6) to 80 ℃ in a vacuum reflow furnace, then continuously heat the chip to 200 ℃ under the condition of introducing formic acid, and then stop introducing the formic acid and cool the chip to room temperature.
The invention also claims a technical scheme of the indium column prepared by the preparation method.
The invention has the beneficial effects that: compared with the method for directly growing the indium columns, the method has the advantages that although some process steps are added, the whole process difficulty is greatly reduced, the controllability of the process is high, the operation precision is high, and the quality of the prepared indium columns is excellent; the size uniformity of the indium columns prepared by the method is greatly improved, and the consistency of the flip interconnection process is greatly improved; the reflow ball-shrinking process can increase the height of the indium columns, and meanwhile, the surfaces of the indium columns obtained by reflow ball-shrinking are more uniform and smooth.
Drawings
FIG. 1 is a schematic flow diagram of the preparation of the present invention;
FIG. 2 is a schematic structural diagram of an indium column fabricated according to the present invention;
FIG. 3 is a graph showing a reflux temperature-time curve of a reflux shrinkage ball and a formic acid atmosphere condition;
In the drawings, the components represented by the respective reference numerals are listed below:
1. chip, 2 indium columns, 3, base metal, 4 and photoresist.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 1, the method for preparing an indium column of an infrared focal plane detector, which is designed by the invention, comprises the following steps:
1) gluing the chip 1: cleaning the surface of the chip 1, removing residual moisture, and then spin-coating a layer of photoresist 4 on the surface of the chip 1;
2) etching a mask: spacing circular photoetching holes on a mask plate according to the space size parameters of the indium columns 2, then covering the mask plate on the chip 1 coated with the glue in the step 1), carrying out first photoetching exposure, and then developing and fixing;
3) plating of base metal 3: plating a priming metal 3 on the surface of the chip 1 treated in the step 2) by adopting a vacuum coating mode, then cleaning the photoresist 4, and stripping redundant metal;
4) gluing again: spin-coating a layer of photoresist 4 on the surface of the chip 1 processed in the step 3) again;
5) and (5) mask etching again: spacing square photoetching holes on a mask plate according to the space size parameters of the indium columns 2, then covering the mask plate on the chip 1 coated with the glue in the step 4), carrying out secondary photoetching exposure, and then developing and fixing;
6) And (3) indium-plated columns 2: plating an indium film on the surface of the chip 1 processed in the step 5) by adopting a vacuum plating mode, then cleaning the photoresist 4, and stripping redundant indium to obtain the chip 1 with the indium columns 2;
7) and (3) ball backflow and shrinkage: and (3) reflowing the chip 1 with the indium columns 2 obtained in the step 6) in a vacuum reflow furnace to shrink balls so that the indium columns 2 are changed into an ellipsoid from a square shape, and thus obtaining the indium column 2 finished product.
Preferably, in the step 1) of the invention, the chip 1 is cleaned by respectively ultrasonically cleaning the chip for 3 minutes by sequentially using acetone and isopropanol, and then washing the chip by using deionized water.
Preferably, in the step 1) of the present invention, the surface of the chip 1 is spin-coated with the AZ5214 type photoresist 4, a spin coater is adopted to spin-coat a layer of thin glue layer, the rotation speed is 4000 rpm, the spin coating time is 30 seconds, and after the glue coating, the chip is placed and heated at a temperature of 95 ℃ for 90 seconds.
In the step 4), the surface of the chip 1 is spin-coated with the AZ4620 type photoresist 4, a spin coater is adopted to spin a medium-thickness glue layer, the number of revolutions is 1000 rpm, the spin coating time is 40 seconds, and the chip is placed after being coated with the glue and is heated for 180 seconds at the temperature of 100 ℃.
Preferably, in step 2) of the present invention, the diameter of the circular lithographic hole is 5 μm; in the step 5), the size of the square photoetching hole is 10 microns multiplied by 10 microns. The final indium columns 2 thus processed are small in size and can meet the requirement of compact layout.
Preferably, in the step 2) of the present invention, the exposure dose is controlled to be 58.2 to 60.5 mj per square centimeter, the exposed chip 1 is placed in a tetramethylammonium hydroxide developing solution with a concentration of 2.38% for development for 45 to 55 seconds, and then fixed with pure water for 30 to 40 seconds.
In the step 5), the exposure dose is controlled to be 396.9-405.7 joules per square centimeter, the exposed chip 1 is placed into a tetramethylammonium hydroxide developing solution with the concentration of 2.38% for development for 100-120 seconds, and then pure water is used for fixing for 30-40 seconds.
Preferably, in the step 3) of the invention, the electron beam evaporation equipment is adopted, the priming metal 3 is plated in a vacuum deposition mode, the deposition rate is controlled at 0.2 nanometer per second, and the working vacuum degree is controlled at 5 multiplied by 10-6Pascal. And the deposition of the priming metal 3 is sequentially deposited with a 50nm metal titanium adhesion layer, a 30nm metal platinum barrier layer and an 80nm metal gold wetting layer. Finally, the priming metal 3 with the diameter of 5 μm and the height of 160nm is obtained.
Preferably, in the step 4), the photoresist 4 is cleaned by soaking in acetone for 30-60 minutes and then cleaning with isopropanol. After the photoresist 4 is cleaned, the excess metal is peeled off along with the cleaning of the photoresist 4.
In the step 6), the photoresist 4 is cleaned by soaking in acetone for 90-120 minutes and then cleaning with isopropanol. After the photoresist 4 is cleaned, the excess indium is peeled off along with the cleaning of the photoresist 4.
Preferably, in step 6) of the present invention, the indium plating film is deposited by vacuum thermal evaporation to a thickness of 6 μm. After stripping off the excess indium, indium columns 2 of about 5 μm lateral dimension and about 6 μm height were obtained.
Preferably, in the step 7), the reflow ball shrinking is to heat the chip 1 with the indium columns 2 obtained in the step 6) to 80 ℃ in a vacuum reflow furnace, then to continuously heat the chip to 200 ℃ under the condition of introducing formic acid, and then to stop introducing the formic acid and to cool the chip to room temperature. As shown in fig. 3, a temperature-time curve and a formic acid atmosphere condition curve can be preset to control the process of reflowing the balls.
The structure of the indium column 2 finally manufactured by the invention is shown in figure 2.
Example 1
1) Cleaning a chip 1: the chip 1 is ultrasonically cleaned by acetone and isopropanol for 3 minutes respectively and then is washed clean by deionized water.
2) Gluing the chip 1: spin-coating AZ5214 type photoresist 4 on the surface of a cleaned chip 1, spin-coating a thin layer of glue by a spin coater at 4000 rpm for 30 seconds, and heating at 95 ℃ for 90 seconds after the glue is coated.
3) Etching a mask: circular photoetching holes with the diameter of 5 mu m are spaced on the mask plate according to the space size parameter of the indium columns 2, then the mask plate is covered on the chip 1 after glue coating, and first photoetching exposure is carried out, wherein the exposure dose is controlled to be 58.2 mJ per square centimeter.
4) Developing and fixing: the exposed chip 1 was developed in a tetramethylammonium hydroxide developer having a concentration of 2.38% for 55 seconds, and then fixed with pure water for 30 seconds.
5) Plating of base metal 3: plating a priming metal 3 on the surface of the chip 1 after the fixation treatment by adopting a vacuum coating mode, controlling the deposition rate at 0.2 nanometer per second and the working vacuum degree at 5 multiplied by 10-6Pascal, 50nm metal titanium adhesion layer, 30nm metal platinum barrier layer and 80nm metal gold wetting layer deposited in sequence.
6) Stripping redundant metal: and soaking the chip 1 plated with the metal film in acetone for 60 minutes, cleaning the chip by using isopropanol, and after the photoresist 4 is cleaned, removing the redundant metal along with the cleaning of the photoresist 4 to obtain the priming metal 3 with the diameter of 5 mu m and the height of 160 nm.
7) Gluing again: spin-coating AZ4620 type photoresist 4 on the surface of the chip 1 which is processed by the base metal 3, spin-coating a medium-thickness glue layer by a spin coater, wherein the rotation number is 1000 rpm, the spin-coating time is 40 seconds, and after the glue coating, the chip is placed and heated for 180 seconds at the temperature of 100 ℃.
8) And (5) mask etching again: square photoetching holes with the size of 10 microns multiplied by 10 microns are spaced on the mask plate according to the space size parameters of the indium columns 2, then the mask plate is covered on the chip 1 coated with glue in the step 4), and second photoetching exposure is carried out, wherein the exposure dose is controlled to 396.9 joules per square centimeter.
9) And (3) developing again and fixing: the exposed chip 1 was developed in a tetramethylammonium hydroxide developer having a concentration of 2.38% for 120 seconds, and then fixed with pure water for 30 seconds.
10) Indium plating layer: and depositing an indium layer on the surface of the chip 1 subjected to the re-fixing treatment by adopting a vacuum thermal evaporation method, wherein the deposition thickness is 6 microns.
11) And (3) stripping redundant indium: and soaking the chip 1 plated with the indium layer in acetone for 120 minutes, cleaning the chip by using isopropanol, removing the photoresist 4 by cleaning, stripping off redundant indium along with the cleaning of the photoresist 4, and obtaining the indium columns 2 with the transverse dimension of about 5 microns and the height of about 6 microns after stripping off the redundant indium.
12) And (3) ball backflow and shrinkage: and (3) reflowing and ball-shrinking the chip 1 with the indium columns 2 stripped of the redundant indium in a vacuum reflow furnace, and controlling the technological process of reflowing and ball-shrinking according to a temperature-time curve and a formic acid atmosphere condition curve shown in figure 3 to change the indium columns 2 from a square shape to an ellipsoid shape so as to obtain the indium column 2 finished product.
Example 2
1) Cleaning a chip 1: the chip 1 is ultrasonically cleaned by acetone and isopropanol for 3 minutes respectively and then is washed clean by deionized water.
2) Gluing the chip 1: spin-coating AZ5214 type photoresist 4 on the surface of a cleaned chip 1, spin-coating a thin layer of glue by a spin coater at 4000 rpm for 30 seconds, and heating at 95 ℃ for 90 seconds after the glue is coated.
3) Etching a mask: circular photoetching holes with the diameter of 6 mu m are spaced on the mask plate according to the space size parameter of the indium columns 2, then the mask plate is covered on the chip 1 after glue coating, and first photoetching exposure is carried out, wherein the exposure dose is controlled at 60.5 mJ per square centimeter.
4) Developing and fixing: the exposed chip 1 was developed in a tetramethylammonium hydroxide developer having a concentration of 2.38% for 45 seconds, and then fixed with pure water for 40 seconds.
5) Plating of base metal 3: plating a priming metal 3 on the surface of the chip 1 after the fixation treatment by adopting a vacuum coating mode, controlling the deposition rate at 0.2 nanometer per second and the working vacuum degree at 5 multiplied by 10-6Pascal, 50nm metal titanium adhesion layer deposited in sequenceA 30nm metal platinum barrier layer and an 80nm metal gold wetting layer.
6) Stripping redundant metal: and soaking the chip 1 plated with the metal film in acetone for 30 minutes, cleaning the chip by using isopropanol, and after the photoresist 4 is cleaned, removing the redundant metal along with the cleaning of the photoresist 4 to obtain the priming metal 3 with the diameter of 6 mu m and the height of 160 nm.
7) Gluing again: spin-coating AZ4620 type photoresist 4 on the surface of the chip 1 which is processed by the base metal 3, spin-coating a medium-thickness glue layer by a spin coater, wherein the rotation number is 1000 rpm, the spin-coating time is 40 seconds, and after the glue coating, the chip is placed and heated for 180 seconds at the temperature of 100 ℃.
8) And (5) mask etching again: square photoetching holes with the size of 12 microns multiplied by 12 microns are spaced on the mask plate according to the space size parameters of the indium columns 2, then the mask plate is covered on the chip 1 coated with glue in the step 4), and second photoetching exposure is carried out, wherein the exposure dose is controlled at 405.7 joules per square centimeter.
9) And (3) developing again and fixing: the exposed chip 1 was developed in a tetramethylammonium hydroxide developer having a concentration of 2.38% for 100 seconds, and then fixed with pure water for 40 seconds.
10) Indium plating layer: and depositing an indium layer on the surface of the chip 1 subjected to the re-fixing treatment by adopting a vacuum thermal evaporation method, wherein the deposition thickness is 6 microns.
11) And (3) stripping redundant indium: and soaking the chip 1 plated with the indium layer in acetone for 90 minutes, cleaning the chip by using isopropanol, removing the photoresist 4 by cleaning, stripping off redundant indium along with the cleaning of the photoresist 4, and obtaining the indium columns 2 with the transverse dimension of about 6 mu m and the height of about 6 mu m after stripping off the redundant indium.
12) And (3) ball backflow and shrinkage: and (3) reflowing and ball-shrinking the chip 1 with the indium columns 2 stripped of the redundant indium in a vacuum reflow furnace, and controlling the technological process of reflowing and ball-shrinking according to a temperature-time curve and a formic acid atmosphere condition curve shown in figure 3 to change the indium columns 2 from a square shape to an ellipsoid shape so as to obtain the indium column 2 finished product.
Inventive examples 1 and 2 produced ellipsoidal indium columns 2 having diameters of about 11 μm and 12 μm and a height of about 10 μm, respectively. The parameters of the appearance size, height and the like of the two groups of indium columns 2 of example 1 and example 2 were measured. The plurality of indium columns 2 of example 1 have substantially the same dimensions, and the error can be controlled to be within 0.05%, the heights are substantially the same, and the error can be controlled to be within 0.07%. The plurality of indium columns 2 of example 2 have substantially the same outer dimensions, and the error can be controlled to be within 0.03%, the heights are substantially the same, and the error can be controlled to be within 0.04%. The indium columns prepared by the method have extremely high size uniformity, and can completely meet the requirement of consistency of the flip interconnection process.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A preparation method of an indium column of an infrared focal plane detector is characterized by comprising the following steps:
1) gluing the chip (1): cleaning the surface of the chip (1) and removing residual moisture, and then spin-coating a layer of photoresist (4) on the surface of the chip (1);
2) Etching a mask: round photoetching holes are spaced on a mask plate according to the space size parameters of the indium columns (2), then the mask plate is covered on the chip (1) coated with the glue in the step 1), first photoetching exposure is carried out, and then development and fixation are carried out;
3) plating base metal (3): plating a priming metal (3) on the surface of the chip (1) treated in the step 2) by adopting a vacuum coating mode, then cleaning the photoresist (4), and stripping redundant metal;
4) gluing again: spin-coating a layer of photoresist (4) on the surface of the chip (1) processed in the step 3) again;
5) and (5) mask etching again: square photoetching holes are spaced on the mask plate according to the space size parameters of the indium columns (2), then the mask plate is covered on the chip (1) coated with the glue in the step 4), photoetching exposure is carried out for the second time, and then development and fixation are carried out;
6) indium-plated posts (2): plating an indium film on the surface of the chip (1) processed in the step 5) by adopting a vacuum plating mode, then cleaning the photoresist (4), and stripping redundant indium to obtain the chip (1) with the indium columns (2);
7) and (3) ball backflow and shrinkage: and (3) reflowing the chip (1) with the indium columns (2) obtained in the step 6) in a vacuum reflow furnace to shrink balls, so that the indium columns (2) are changed into an ellipsoid from a square shape, and thus indium column (2) finished products are obtained.
2. The method for preparing indium columns of an infrared focal plane detector as claimed in claim 1, wherein: in the step 1), the chip (1) is cleaned by respectively ultrasonically cleaning the chip for 3 minutes by sequentially adopting acetone and isopropanol and then washing the chip by using deionized water.
3. The method for preparing indium columns of an infrared focal plane detector as claimed in claim 1, wherein: in the step 1), the surface of the chip (1) is spin-coated with an AZ5214 type photoresist (4), a spin coater is adopted for spin coating, the rotation number is 4000 rpm, the spin coating time is 30 seconds, and after the photoresist is coated, the chip is placed and heated for 90 seconds at the temperature of 95 ℃; in the step 4), the surface of the chip (1) is spin-coated with the AZ4620 type photoresist (4), a spin coater is adopted for spin coating, the rotation number is 1000 rpm, the spin coating time is 40 seconds, and after the photoresist is coated, the chip is placed and heated for 180 seconds at the temperature of 100 ℃.
4. The method for preparing indium columns of an infrared focal plane detector as claimed in claim 1, wherein: in the step 2), the diameter of the circular photoetching hole is 5 mu m; in the step 5), the size of the square photoetching hole is 10 microns multiplied by 10 microns.
5. The method for preparing indium columns of an infrared focal plane detector as claimed in claim 3, wherein: in the step 2), the exposure dose is controlled to be 58.2-60.5 mJ per square centimeter, the exposed chip (1) is placed into a tetramethylammonium hydroxide developing solution with the concentration of 2.38% for development for 45-55 seconds, and then the pure water is used for fixing for 30-40 seconds; in the step 5), the exposure dose is controlled to be 396.9-405.7 joules per square centimeter, the exposed chip (1) is placed into a tetramethylammonium hydroxide developing solution with the concentration of 2.38% for development for 100-120 seconds, and then pure water is used for fixing for 30-40 seconds.
6. The method for preparing indium columns of an infrared focal plane detector as claimed in claim 1, wherein: in the step 3), the electron beam evaporation equipment is adopted, the priming metal (3) is plated in a vacuum deposition mode, the deposition rate is controlled to be 0.2 nanometer per second, and the working vacuum degree is controlled to be 5 multiplied by 10-6Pascal, in the step 3), the priming metal (3) comprises a 50nm metal titanium adhesion layer, a 30nm metal platinum barrier layer and an 80nm metal gold wetting layer which are deposited in sequence.
7. The method for preparing indium columns of an infrared focal plane detector as claimed in claim 1, wherein: in the step 4), the photoresist (4) is cleaned by soaking in acetone for 30-60 minutes and then cleaning with isopropanol; in the step 6), the photoresist (4) is cleaned by soaking in acetone for 90-120 minutes and then cleaning with isopropanol.
8. The method for preparing indium columns of an infrared focal plane detector as claimed in claim 1, wherein: in the step 6), indium is deposited on the indium-plated film by adopting a vacuum thermal evaporation method, and the deposition thickness is 6 microns.
9. The method for preparing indium columns of an infrared focal plane detector as claimed in claim 1, wherein: in the step 7), the reflow ball shrinking is to heat the chip (1) with the indium columns (2) obtained in the step 6) to 80 ℃ in a vacuum reflow furnace, then to continuously heat the chip to 200 ℃ under the condition of introducing formic acid, and then to stop introducing the formic acid and to cool the chip to room temperature.
10. An indium column (2) produced by the production method according to claim 1 to 9.
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| CN112490137A (en) * | 2020-11-30 | 2021-03-12 | 安徽光智科技有限公司 | Preparation method of focal plane flip interconnection indium column |
| CN112635433B (en) * | 2020-12-18 | 2023-05-23 | 中国电子科技集团公司第四十四研究所 | Indium column structure for large area array hybrid focal plane and manufacturing method |
| CN112323022B (en) * | 2021-01-04 | 2021-03-19 | 度亘激光技术（苏州）有限公司 | Vapor deposition method for semiconductor device |
| CN114300604B (en) * | 2021-12-27 | 2024-02-20 | 中国电子科技集团公司第五十五研究所 | High-tolerance indium column of high-resolution Micro-LED Micro display device and preparation method thereof |
| CN115036390B (en) * | 2022-04-24 | 2024-03-26 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Preparation method of high-width-ratio increased welding spot column, electronic device and infrared detector |
| CN116949413B (en) * | 2023-03-16 | 2024-04-12 | 无锡中科德芯感知科技有限公司 | Indium column preparation device, preparation method and system, electronic equipment and storage medium |
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