CN102881607A

CN102881607A - Novel focal plane array electrical interconnection process

Info

Publication number: CN102881607A
Application number: CN2012103752909A
Authority: CN
Inventors: 王泰升; 鱼卫星; 卢振武; 孙强
Original assignee: Changchun Institute of Optics Fine Mechanics and Physics of CAS
Current assignee: Changchun Institute of Optics Fine Mechanics and Physics of CAS
Priority date: 2012-09-27
Filing date: 2012-09-27
Publication date: 2013-01-16
Anticipated expiration: 2032-09-27
Also published as: CN102881607B

Abstract

The invention belongs to the technical field of photoelectronic imaging and relates to a novel focal plane array electrical interconnection process which solves the problem of increase of thermal conductance caused by deformation of indium columns during cold welding of a focal plane detector. The focal plane array electrical interconnection process includes the steps: firstly, a photoetching process on a read-out circuit of the focal plane detector; secondly, a metal membrane deposition process, namely depositing a nickel or copper metal membrane and then depositing an indium metal membrane, wherein the nickel or copper metal membrane is thicker than the indium metal membrane; thirdly, a photoresist stripping process on the read-out circuit; fourthly, an indium column reflux balling process on the read-out circuit; fifthly, an electrode manufacturing process on a focal plane chip; and sixthly, a cold welding interconnection process of the focal plane chip and the read-out circuit. Since nickel or copper is used as indium column support and electrical communication metal, the problem of increase of thermal conductance caused by deformation of indium columns during cold welding interconnection is avoided, and performances of the focal plane array detector are improved.

Description

A kind of novel focal plane array electrical interconnection technique

Technical field

The present invention relates to a kind of novel focal plane array electrical interconnection technique, belong to the photoelectric imaging technology field.

Background technology

Focal plane array is widely used in the research and development making of various photoelectric devices, such as focal plane Infrared Detectors, ultraviolet detector etc.Take the focal plane Infrared Detectors as example, it be a kind of at working and room temperature, utilize thermoelectric effect that the LONG WAVE INFRARED radiation is transformed into the signal of telecommunication, realizes the Infrared Detectors of scanning calorimeter imaging.This device mainly is comprised of infrared focal plane detector chip and reading circuit flip-chip interconnection.Be characterized in preparing respectively detector chip and readout circuit chip, make its separately Performance optimization, interconnect again.Detector chip is connected interconnection with readout circuit chip must realize that machinery is connected with electricity, and makes between the two the stress minimum.Usually select the indium post to interconnect, its Main Function is to whole detections unit and reads input completely machinery and electrical connection, the thermal expansion mismatch of simultaneous buffering chip and reading circuit are provided for this reason.This technology mainly comprises indium post growth technique and two aspects of interconnection process.

As shown in Figure 1, the concrete technology flow process is:

At first be the growth of indium post, for realizing face-down bonding, the indium post that plays connection function is had three requirements: general diameter is about 30 μ m, about height 10 μ m; Highly unanimously, neat, the smooth surface of regular shape; Reduce the thickness of surface oxide layer as far as possible.The method of growth indium post has at present: galvanoplastic, evaporation stripping method and evaporation etch.For adhesive force, shape and height, surface oxidation, blind element and the highly consistent problem that solves the indium post, generally more adopt evaporation to peel off.When lift-off technology can be avoided using the chemical reagent wet etching, graph outline and subsurface material are caused damage.It generally is used for replacing ion beam bombardment to be difficult to the metal material of etching.General stripping technology is at first coated photoresist and is formed pattern, then uses metal level of evaporation technique deposit.Next substrate is dipped in the solution that removes photoresist that can dissolve photoresist, directly being deposited on on-chip metallic pattern will be retained, and the metal that is deposited on the photoresist will come off from substrate along with the dissolving of photoresist, only stays metal column at substrate surface at last.In the existing method generally before the plating indium first at chip (perhaps reading circuit) plated surface layer of metal electrode, generally adopt metallic gold, and then plate indium metal, the deposition of two kinds of metals can adopt evaporation stripping means recited above to realize.

The indium post plays electricity and connects in focus planardetector, survey first radiations heat energy that absorbs to the passage of reading circuit direction divergence loss but also consisted of simultaneously.The thermal conductance that reduces the indium post is the important channel of improving device performance, can by reduce the indium column diameter, increase indium post height and realize.Comparatively generally adopting at present diameter is 10 μ m-15 μ m, it highly is the indium post about 10 μ m, and by indium post backflow balling-up technology indium post height is further improved, reduce simultaneously the detector thermal conductance, effectively raise soldering reliability and the responsiveness of detector.

Indium post cold welding technique is adopted in the interconnection of focal plane array, satisfies aligning, firm and three requirements of electrical communication by face-down bonding equipment.But, in the process of cold welding, the indium post can be owing to the pressure that is subject to from detector chip and reading circuit two ends produces deformation, as shown in Figure 1, indium post height is by being reduced to below the 5 μ m more than the 10 original μ m after the pressure welding, simultaneously diameter increases to about 20 μ m about by 15 original μ m, and so the contact area of indium post and detector chip and reading circuit must increase.In this case, indium post thermal conductance can increase thereupon, so that detector performance reduces greatly.

Summary of the invention

In order to solve that focus planardetector indium post in the cold welding process produces deformation and the problem that causes thermal conductance to increase, we propose the novel interconnection process that a kind of, metal that thermal conductance less higher with hardness supports as electrical communication metal and indium post.

The technical scheme that technical solution problem of the present invention adopts is as follows:

A kind of novel focal plane array electrical interconnection technique may further comprise the steps:

Step 1: the photoetching process on the focus planardetector reading circuit, by the UV mask exposure, form figure at photoresist, described pattern side wall and inclination angle, reading circuit surface should be less than or equal to 90 °;

Step 2: the depositing operation of metallic diaphragm, at first carry out the deposition of nickel or copper metal film, then carry out the deposition of indium metal film, and the thickness of nickel or copper metallic diaphragm is greater than the thickness of indium metal rete;

Step 3: the photoresist stripping process on the reading circuit, readout circuit chip is soaked in the solution that removes photoresist of dissolving photoresist, heating is fully dissolved photoresist, finally only has metallic diaphragm to reside in chip surface, forms indium post and nickel or copper metal column interconnecting metal post;

Step 4: the indium post backflow balling technique on the reading circuit, will be soaked in the chip of interconnect indium column in ammonium chloride and the glycerine mixed solution, be heated to the temperature of the fusing point of indium, it is spherical or hemispherical that the backflow of indium post surface is formed, and removes simultaneously surface oxide layer;

Step 5: the Fabrication Technology of Electrode on the focal plane chip, make metal electrode at detector chip, the metal electrode diameter is identical with the indium column diameter;

Step 6: the cold welding interconnection process of focal plane chip and reading circuit, pressure welding method is adopted in the interconnection of detector chip and reading circuit, utilizes face-down bonding equipment to realize aligning, pressure welding, finishes interconnection process.

The invention has the beneficial effects as follows: novel focal plane array electrical interconnection technique of the present invention, utilize the metals that hardness is higher, thermal conductance is less such as nickel or copper to support and the electrical communication metal as the indium post, avoided increasing problem because the indium post is out of shape the thermal conductance that causes in the cold welding interconnection process, thereby improved the performance of focal plane array detector.

Description of drawings

Fig. 1 is focal plane array electrical interconnection artwork in the prior art.

Fig. 2 is a kind of novel focal plane array electrical interconnection artwork of the present invention.

1, indium metal film, 2, gold electrode, 3, photoresist, 4, reading circuit, 5, detector chip, 6, metal electrode, 7, nickel or copper metal film.

Embodiment

Below in conjunction with accompanying drawing the present invention is done and to describe in further detail.

As shown in Figure 2, a kind of novel focal plane array electrical interconnection technique of the present invention.

At first carry out the photoetching process on the reading circuit, this technique forms figure by the ultraviolet mask exposure at photoresist 3.Photoresist 3 thickness should be more than or equal to the metallic diaphragm thickness of deposition, and simultaneously pattern side wall and reading circuit 4 surperficial inclination angles should be less than or equal to 90 °, and namely figure is inverted trapezoidal or rectangle, to be conducive to peeling off of photoresist 3 behind the plated film.

Next be the deposition of metal film, the adoptable method of this technique has a lot, such as electron beam evaporation plating, magnetron sputtering etc.Here illustrate as an example of electron beam evaporation plating example: under vacuum state, the electronics of electron gun emission is under electromagnetic field effect, obtain kinetic energy and bombard the evaporating materials that is in anode, making it become atom or molecule overflows from the surface gasification, form steam flow, incide the readout circuit chip surface, condensing forms the solid metallic film.The deposition of metal film among the present invention is at first carried out the deposition of nickel or copper metal film 7, then carry out the deposition of indium metal film 1, and the thickness of nickel or copper metal film 7 is greater than the thickness of indium metal film 1.

Plated film will carry out peeling off of photoresist 3 after finishing, and readout circuit chip is soaked in the solution that removes photoresist of dissolving photoresist 3, is heated to uniform temperature, and photoresist 3 is fully dissolved, and finally only has metallic film to reside in chip surface, forms the interconnecting metal post.Metal column comprises indium post and the harder metal column two parts such as nickel or copper.

The backflow balling technique of indium post, method such as wet method hot melt, dry method hot melt etc. that this technique realizes, here take the wet method hot melt as example: will be soaked in the chip of interconnect indium column in a certain proportion of ammonium chloride and the glycerine mixed solution, be heated to the temperature about the fusing point of indium, it is spherical or hemispherical that the backflow of indium post surface is formed, and removes simultaneously surface oxide layer.

Be focal plane array detector chip 5 at last and the interconnection process of reading circuit, also need to make the diameters metal electrode 6 close with the indium column diameter at detector chip 5 before this, as with the pad of indium post.The manufacture craft of metal electrode 6 can adopt general photoetching method to add that ion beam etching obtains, and the method that also can adopt metal film deposition to add photoresist lift off obtains.Detector chip 5 adopts pressure welding method with the interconnection of reading circuit 4, utilizes face-down bonding equipment to realize aligning, pressure welding, finishes interconnection process.Under pressure, deformation still can occur in the indium post, but it is higher to be supported on the metal hardnesses such as the nickel of indium post below or copper, can conformal, the metal heat conduction area reduces, and increases simultaneously conducting path, effectively reduce thermal conductance, the performance of focal plane array detector is improved.

Claims

1. a novel focal plane array electrical interconnection technique is characterized in that, may further comprise the steps:

Step 4: the indium post backflow balling technique on the reading circuit, will be soaked in the chip of interconnect indium column in ammonium chloride and the glycerine mixed solution, be heated to the melting temperature of indium, it is spherical or hemispherical that the backflow of indium post surface is formed, and removes simultaneously surface oxide layer;