CN111584635B - 半导体器件 - Google Patents
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Abstract
公开了一种半导体器件,包括衬底、位于衬底上的漂移区、位于漂移区上的阱区、位于阱区中的源端掺杂区、位于漂移区上与源端掺杂区相对的漏端掺杂区,以及位于源端和漏端之间的位于阱区位置的栅结构,栅结构在阱区中形成沟道区,源端掺杂区包括掺杂类型相反的第一掺杂区和第二掺杂区,沟道区连接第一掺杂区和漂移区。其中,本发明的半导体器件源端的第一掺杂区和第二掺杂区等同靠近栅结构,降低了第二掺杂区至漂移区与阱区构成的pn结结面的距离,在半导体器件反向关断时,有效降低了由于碰撞电离产生的空穴在阱区中流通路径,降低了阱区上的压降,防止第一掺杂区—阱区—漂移区构成的寄生三极管的误开启,有效地提升了半导体器件的自防护能力。
Description
技术领域
本发明涉及半导体技术领域,特别涉及一种半导体器件。
背景技术
功率LDMOS(laterally-diffused metal-oxide semiconductor,横向扩散金属氧化物半导体)通常应用在大电流,大电压的情况下。N型LDMOS器件体内通常包括N+掺杂漏区、N型漂移区、P阱区、N+掺杂源区和P+掺杂体接触区,其中N+掺杂源区和P+掺杂体接触区位于P阱区中,在N型LDMOS器件处于反向耐压状态时,由于碰撞电离会产生大量的电子空穴对,进而产生相应的空穴电流,当该空穴电流由P阱区(p_body)流经至p+体接触区时,P阱区上的压降会被抬起,由此会可能导致寄生的NPN(N+源端—P阱区—N型漂移区)误开启,器件出现功能失效。当器件碰撞电离产生空穴越多,寄生的NPN越容易被误开启,所以,对器件的自防护能力要求越高。
发明内容
鉴于上述问题,本发明的目的在于提供一种半导体器件,从而提升器件的自防护能力。
根据本发明的一方面,提供一种半导体器件,其特征在于,包括:
衬底;
漂移区,位于所述衬底上;
漏端掺杂区,位于所述漂移区上表面第一方向的一端;
阱区,位于所述漂移区上表面第一方向与所述漏端掺杂区相反的一端;
源端掺杂区,位于所述阱区中;
栅结构,位于所述阱区位置,在所述阱区至所述漂移区的位置形成沟道区,所述沟道区的沟道方向为所述漂移区的第一方向,所述沟道区位于所述源端掺杂区与所述漏端掺杂区之间,且与所述源端掺杂区接触连接;其中,
所述源端掺杂区包括掺杂类型相反的第一掺杂区和第二掺杂区,所述漂移区的掺杂类型与所述漏端掺杂区的掺杂类型相同,所述第一掺杂区的掺杂类型与所述漏端掺杂区的掺杂类型相同,所述第一掺杂区与所述第二掺杂区按在所述漂移区上表面与所述第一方向垂直的第二方向线性分布且交错连接,所述第一掺杂区与所述沟道区对应。
可选地,所述第一掺杂区和所述第二掺杂区的数量均为至少一个。
可选地,所述第一掺杂区的数量至少为两个。
可选地,所述沟道区的沟道宽度与所述第一掺杂区的尺寸相匹配。
可选地,所述栅结构包括:
槽型栅,位于所述阱区中,数量与所述第二掺杂区的数量相匹配。
可选地,所述栅结构还包括:
平面栅,数量与源端第一掺杂区数量匹配,覆盖在所述沟道区上。
可选地,还包括:
在所述栅结构与所述源端掺杂区的接触面上,所述槽型栅的图案延伸至所述第一掺杂区的图案内。
可选地,在所述栅结构与所述源端掺杂区的接触面上,所述第二掺杂区的图案位于所述槽型栅的图案内,所述第一掺杂区的图案与所述第二掺杂区的图案接触连接。
可选地,所述第一掺杂区为N型掺杂,所述第二掺杂区为P型掺杂。
本发明提供的半导体器件包括衬底、位于衬底上的漂移区、位于漂移区上的阱区、位于阱区中的源端掺杂区、位于漂移区上与源端掺杂区相对的漏端掺杂区,以及位于源端和漏端之间的位于阱区位置的栅结构,栅结构在阱区中形成沟道区,源端掺杂区包括掺杂类型相反的第一掺杂区和第二掺杂区,第一掺杂区的掺杂类型与漏端掺杂区的掺杂类型相同,沟道区连接第一掺杂区和漂移区。其中,源端的第一掺杂区和第二掺杂区等同靠近栅结构,降低了第二掺杂区至漂移区与阱区构成的pn结结面的距离,在本发明提供的半导体器件处于反向耐压状态时,降低了空穴电流在阱区中的从阱区与漂移区形成的pn结结面至源端第二掺杂区的流通路径,有效缓解了阱区压降的提升,防止第二掺杂区—阱区—漂移区构成的寄生三极管的误开启,有效地提升了半导体器件的自防护能力。
设置多个沟道区,可以有效地提升电流至漂移区的均匀性,降低漂移区电阻,从而降低了器件导通压降,提升了器件的电流能力。
槽型栅靠近源端的侧壁完全覆盖源端第二掺杂区侧壁,并与第一掺杂区相接触,保障沟道区与源端掺杂区的连接。
附图说明
通过以下参照附图对本发明实施例的描述,本发明的上述以及其他目的、特征和优点将更为清楚,在附图中:
图1示出了根据本发明实施例的半导体器件的整体结构示意图;
图2示出了根据本发明实施例的半导体器件的部分结构示意图;
图3示出了根据图1所示的半导体器件的沿AA’的纵向剖面结构示意图。
具体实施方式
以下将参照附图更详细地描述本发明的各种实施例。在各个附图中,相同的元件采用相同或类似的附图标记来表示。为了清楚起见,附图中的各个部分没有按比例绘制。
下面结合附图和实施例,对本发明的具体实施方式作进一步详细描述。
图1示出了根据本发明实施例的半导体器件的整体结构示意图,图2示出了根据本发明实施例的半导体器件的部分结构示意图。结合图1和图2,其中以N型LDMOS为例,本发明实施例的半导体器件100包括P衬底110、N漂移区120、P阱区130、N掺杂区141、P掺杂区142、栅结构150和漏端N掺杂区160。其中,P衬底110可以是P型掺杂的硅衬底,N型掺杂和P型掺杂为相反掺杂类型。
N漂移区120位于P衬底110上,P阱区130位于N漂移区120上表面横向方向上的一端,N掺杂区160位于N漂移区横向方向上的另一端,构成漏端D。
N掺杂区141和P掺杂区142沿P阱区130上表面纵向交错分布在P阱区130中,N掺杂区141和P掺杂区142互连构成源端S。
栅结构150设置在源端S与漏端D之间,与构成源端S的N掺杂区141和P掺杂区142的一个侧壁接触连接,包括在俯视面上交错分布平面栅151和槽型栅152,栅结构150的平面栅151的下表面和槽型栅152的下表面与侧面形成沟道区131,整体构成鳍式沟道区。其中,该纵向方向为在漂移区120上表面与前述横向方向垂直的方向,如果该两个方向具有不为九十度的夹角,也可行,以垂直设计为基本设计。
构成源端的N掺杂区141和P掺杂区142与栅结构150的侧壁相接触,且栅结构150的平面栅151覆盖至N掺杂区141,可以保障沟道区131至N掺杂区141的连接。同时,栅结构150与源端掺杂区平行的侧壁和源端掺杂区接触,而槽型栅152的底面与与源端掺杂区垂直的侧壁形成沟道区,与N掺杂区141直接连接,保障了沟道区至N掺杂区141的连接。
将P掺杂区142设置在栅结构150的侧边,且在栅结构150和源端掺杂区的接触面上,P掺杂区142的图案位于槽型栅152的图案内,这样既可以不影响源端掺杂区的引出,又可以有效地降低了P掺杂区142至P阱区130与N漂移区120结面的距离,相比于传统的设置在N掺杂区141的远离栅结构150的侧边可以有效缩短由于碰撞电离产生的空穴在P阱区内的流通路径,降低在器件耐压状态下,P阱区上的压降,防止寄生的NPN(N掺杂区141—P阱区130—N漂移区120)的误开启,有效地增加了本发明实施例的半导体器件100的自防护能力。同时,N掺杂区141与平面栅151对应,P掺杂区与槽型栅152对应,这样可以最大效率地进行N掺杂区141及P掺杂区142引出的折中。
N掺杂区为富含电子的区域,P掺杂区为富含空穴的区域,本实施例为N型LDMOS,针对空穴在阱区的流通路径,如果是P型LDMOS,则是电子在阱区的流通路径,可统一为源端载流子的流通路径。
图3示出了根据图1所示的半导体器件的沿AA’的纵向剖面结构示意图。如图所示,本发明实施例的半导体器件100在栅结构150位置的纵向剖面结构上包括依次堆叠的P衬底110、N漂移区120、P阱区130、槽型栅152和平面栅151。
槽型栅151和平面栅152均包括栅氧化层1和多晶硅层2,槽型栅151间隔分布,平面栅152覆盖在槽型栅151的间隔区域,当器件栅机构150具有一定的开启电压而导通时,在P阱区130中,槽型栅151的侧壁及底面和平面栅151的下表面均会形成沟道,整体形成鳍式的沟道区131。
其中,鳍式的沟道区131可以增加有效沟道宽度(沟道区131在图3所示的纵截面上的总长度即为有效沟道宽度),降低沟道导通电阻,降低半导体器件100的比导通电阻。间隔分布,可以使电流密度在漂移区内更加均匀,可以降低漂移区电阻,从另一方面降低半导体器件100的导通电阻,在相同的导通电阻下可以拥有更高的击穿电压(BV)。
本发明为规避寄生NPN的误开启,主要设计源端的N掺杂区和P掺杂区等同靠近设置在栅结构的一侧,而对于栅结构,可以选择仅包含平面栅和槽型栅中的一种,如果仅选择槽型栅,可以不选择设置平面栅,当然,槽型栅和平面栅均设置为较优选择。
本发明的半导体器件将源端的N掺杂区和P掺杂区沿栅结构远离漏端的侧壁交错分布,源端的N掺杂区和P掺杂区等同靠近栅结构,缩短P掺杂区至漂移区与阱区的结面的距离,可以有效缩短由于碰撞电离产生的空穴在P阱区内的流通路径,在器件耐压状态下,可以降低P阱区上的压降,防止寄生的NPN的误开启,有效地增加了本发明实施例的半导体器件100的自防护能力。同时,N掺杂区141与平面栅151对应,P掺杂区与槽型栅152对应,最大效率地进行N掺杂区141及P掺杂区142引出的折中。
栅结构为槽型栅和平面栅的组合,同时起到栅功能,与平面栅组合形成鳍式的沟道区,可以增加有效沟道宽度,降低沟道导通电阻,降低本发明的半导体器件的比导通电阻;鳍式的沟道区具有多个间隔开来的沟道区,可以使电流在漂移区中的分布密度更加均匀,降低漂移区电阻,并提升器件的击穿电压。
平面栅与源端的N掺杂区相匹配,槽型栅与源端的P掺杂区相匹配,确保源端的N掺杂区到沟道区的引出。栅结构的平面栅延伸至源端N掺杂区,可以确保N掺杂区至沟道区的引出。
依照本发明的实施例如上文所述,这些实施例并没有详尽叙述所有的细节,也不限制该发明仅为所述的具体实施例。显然,根据以上描述,可作很多的修改和变化。本说明书选取并具体描述这些实施例,是为了更好地解释本发明的原理和实际应用,从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。
Claims (7)
1.一种半导体器件,其特征在于,包括:
衬底;
漂移区,位于所述衬底上;
漏端掺杂区,位于所述漂移区上表面第一方向的一端;
阱区,位于所述漂移区上表面第一方向与所述漏端掺杂区相反的一端;
源端掺杂区,位于所述阱区中;
栅结构,位于所述阱区位置,在所述阱区至所述漂移区的位置形成沟道区,所述沟道区的沟道方向为所述漂移区的第一方向,所述沟道区位于所述源端掺杂区与所述漏端掺杂区之间,且与所述源端掺杂区接触连接;其中,
所述源端掺杂区包括掺杂类型相反的第一掺杂区和第二掺杂区,所述漂移区的掺杂类型与所述漏端掺杂区的掺杂类型相同,所述第一掺杂区的掺杂类型与所述漏端掺杂区的掺杂类型相同,所述第一掺杂区与所述第二掺杂区按在所述漂移区上表面与所述第一方向垂直的第二方向线性分布且交错连接,所述第一掺杂区与所述沟道区对应;
所述栅结构包括槽型栅,所述槽型栅位于所述阱区内,在所述栅结构与所述源端掺杂区的接触面上,所述槽型栅的图案延伸至所述第一掺杂区的图案内;在所述栅结构与所述源端掺杂区的接触面上,所述第二掺杂区的图案位于所述槽型栅的图案内,所述第一掺杂区的图案与所述第二掺杂区的图案接触连接。
2.根据权利要求1所述的半导体器件,其特征在于,
所述第一掺杂区和所述第二掺杂区的数量均为至少一个。
3.根据权利要求2所述的半导体器件,其特征在于,
所述第一掺杂区的数量至少为两个。
4.根据权利要求2所述的半导体器件,其特征在于,
所述沟道区的沟道宽度与所述第一掺杂区的尺寸相匹配。
5.根据权利要求1至4任一项所述的半导体器件,其特征在于,所述槽型栅的数量与所述第二掺杂区的数量相匹配。
6.根据权利要求5所述的半导体器件,其特征在于,所述栅结构还包括:
平面栅,数量与源端第一掺杂区数量匹配,覆盖在所述沟道区上。
7.根据权利要求1所述的半导体器件,其特征在于,
所述第一掺杂区为N型掺杂,所述第二掺杂区为P型掺杂。
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