CN111564491A - GaN HEMT semiconductor device and preparation method thereof - Google Patents

GaN HEMT semiconductor device and preparation method thereof Download PDF

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CN111564491A
CN111564491A CN202010672036.XA CN202010672036A CN111564491A CN 111564491 A CN111564491 A CN 111564491A CN 202010672036 A CN202010672036 A CN 202010672036A CN 111564491 A CN111564491 A CN 111564491A
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layer
electrode
semiconductor device
metal gate
gate electrode
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马飞
冯光建
程明芳
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Zhejiang Jimaike Microelectronics Co Ltd
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Zhejiang Jimaike Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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Abstract

The invention provides a GaN HEMT semiconductor device and a preparation method thereof, wherein the method comprises the following steps: providing a GaN HEMT semiconductor device thin film structure; forming a source electrode and a drain electrode on the thin film structure of the GaN HEMT semiconductor device and depositing a SiN passivation layer; forming a metal gate electrode gradually increasing from bottom to top in the SiN passivation layer; removing at least part of the SiN passivation layer; and depositing an electrode supplementary layer on the surface of the structure formed in the previous step. The gate-last process is adopted, the metal gate electrode which is gradually increased from bottom to top is formed, and the electrode supplement layers of the source electrode and the drain electrode or the electrode supplement layers of the source electrode and the gate field plate are formed by secondary deposition, so that the distances between the source electrode and the metal gate electrode and between the drain electrode and the metal gate electrode are shortened, the access resistances of the source electrode and the drain electrode are reduced, the voltage resistance of the device is improved, and meanwhile, the metal gate electrode is prepared behind the source electrode and the drain electrode, so that the metal gate electrode is prevented from being damaged by the source electrode and drain electrode preparation process, and the device performance is improved.

Description

GaN HEMT semiconductor device and preparation method thereof
Technical Field
The invention belongs to the field of semiconductor device manufacturing, and particularly relates to a GaN HEMT semiconductor device and a preparation method thereof.
Background
The third generation Semiconductor material, i.e. the Wide Band Gap Semiconductor (WBGS) Semiconductor material, is developed following the first generation silicon, germanium, the second generation gallium arsenide, indium phosphide, etc. Among the third generation semiconductor materials, gallium nitride (GaN) has superior properties such as wide band gap, direct band gap, high breakdown electric field, lower dielectric constant, high electron saturation drift velocity, strong radiation resistance, and good chemical stability, and becomes a key semiconductor material for manufacturing a new generation of microelectronic devices and circuits following germanium, silicon, and gallium arsenide. Especially, the material has the advantages of unique thickness in the aspects of high-temperature, high-power, high-frequency and anti-radiation electronic devices and full-wavelength and short-wavelength photoelectric devices, and is an ideal material for realizing the high-temperature, high-power, high-frequency, anti-radiation and full-wavelength photoelectric devices.
The High Electron Mobility Transistor (HEMT) based on the AlGaN/GaN heterojunction has the advantages of low on resistance, High breakdown voltage, High switching frequency and the like, so that the HEMT can be used as a core device in various power conversion systems, and has an important application prospect in the aspects of energy conservation and consumption reduction. The self-alignment mode in the existing GaN HEMT semiconductor device preparation process is an effective mode for reducing the access resistance of a source electrode and a drain electrode (the access resistance is the resistance generated by a non-doped part which is not covered by metal between the source electrode and/or the drain electrode and a metal gate electrode, as shown in figure 1), meanwhile, the self-alignment mode omits the requirement of photoetching alignment, and the preparation of a source metal electrode and a drain metal electrode is realized by taking the existing gate electrode as a mask, but the self-alignment process is generally combined with a gate-first process (gate-first), namely, the preparation of the metal gate electrode is firstly completed, and then the subsequent source metal electrode and drain metal electrode processes are carried out, which means that the gate needs to bear the high-temperature process in the preparation process of the source metal electrode and the drain metal electrode, such as high-temperature annealing after ion implantation, the temperature is generally as high as 800-900 ℃, while the metal material of the currently and commonly adopted, high temperatures >800 ℃ cannot be tolerated and therefore conventional self-aligned processes cannot be realized.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a GaN HEMT semiconductor device and a method for manufacturing the same, which are used to solve the problem in the prior art that the performance of a metal gate electrode is damaged when the access resistance of the GaN HEMT semiconductor device is reduced by combining a self-aligned process with a metal gate electrode advanced process.
In order to achieve the above and other related objects, the present invention provides a method for manufacturing a GaN HEMT semiconductor device, the method comprising:
providing a GaN HEMT semiconductor device thin film structure, wherein the GaN HEMT semiconductor device thin film structure sequentially comprises a semiconductor substrate layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer along the growth direction of the GaN HEMT semiconductor device thin film structure;
defining a source electrode area and a drain electrode area on the GaN HEMT semiconductor device thin film structure by using a photoetching mask, and forming a source electrode and a drain electrode which are in ohmic contact with each other in the source electrode area and the drain electrode area;
depositing a SiN passivation layer on the GaN HEMT semiconductor device thin film structure, and forming a metal gate electrode region in the SiN passivation layer, wherein the opening of the metal gate electrode region is gradually increased from bottom to top;
forming a metal gate electrode in the metal gate electrode region;
removing at least the SiN passivation layer from the source electrode to the metal gate electrode region;
and depositing an electrode supplement layer on the surface of the structure formed in the step, wherein the electrode supplement layer extends into a projection region corresponding to the top of the metal gate electrode so as to reduce the access resistance of the GaN HEMT semiconductor device.
Optionally, the GaN HEMT semiconductor device thin film structure further comprises a GaN cap layer formed on the AlGaN barrier layer; and forming the source electrode and the drain electrode which are in ohmic contact by adopting an annealing process, wherein the annealing temperature is between 800 and 900 ℃, and the annealing time is between 20 and 90 seconds.
Optionally, after forming the electrode supplementary layer, depositing a protective layer on the surface of the structure formed in the above step, wherein the material of the protective layer includes at least one of the group consisting of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, and zirconium oxide.
Optionally, when the electrode supplement layer is formed by deposition, the structure formed by the above steps is inclined and the rotation deposition is kept, and the inclination angle is between 0 ° and 30 °.
Optionally, the SiN passivation layer from the source electrode to the metal gate electrode region is removed, the SiN passivation layer from the drain electrode to the metal gate electrode region is remained, and the electrode supplement layer is formed on the GaN HEMT semiconductor device thin film structure extending from the surface of the source electrode to the projection region corresponding to the top of the metal gate electrode, on the metal gate electrode and on the SiN passivation layer from the drain electrode to the metal gate electrode region.
Optionally, all the SiN passivation layer is removed, and the electrode supplement layer is formed on the GaN HEMT semiconductor device thin film structure extending from the surface of the source electrode to a position close to the metal gate electrode, on the GaN HEMT semiconductor device thin film structure extending from the surface of the drain electrode to a projection area corresponding to the top of the metal gate electrode, and on the metal gate electrode.
Optionally, the lowest layer of the SiN passivation layer is a SiN barrier protection layer with the thickness of 5 nm-20 nm, and the SiN barrier protection layer is formed by adopting an LPCVD process.
Optionally, the density of the SiN passivation layer gradually decreases from bottom to top, and the density of the SiN passivation layer is between 2g/cm3~3g/cm3The step of forming the metal gate electrode region in the SiN passivation layer may comprise: and forming a metal gate electrode region opening by using a photoetching mask, removing the SiN passivation layer by adopting dry etching, and gradually reducing the density of the SiN passivation layer from bottom to top so as to form the metal gate electrode region with the gradually increased opening from bottom to top.
Optionally, the SiN passivation layer is formed by a PECVD process, and the method includes: gradually reducing the deposition temperature of the PECVD process from bottom to top and/or gradually increasing the proportion of a nitrogen ion gas source from bottom to top; and removing the SiN passivation layer by adopting a reactive ion etching process.
Optionally, the density of the SiN passivation layer is uniform from bottom to top, and the step of forming the metal gate electrode region in the SiN passivation layer includes: and forming an opening of a metal gate electrode region by using a photoetching mask, then anisotropically etching the SiN passivation layer with partial thickness by using a fluorine-based etching gas dry method, and finally isotropically etching the SiN passivation layer with the residual thickness by using a phosphoric acid wet method, thereby forming the metal gate electrode region with gradually increased opening from bottom to top.
The present invention also provides a GaN HEMT semiconductor device, the device comprising:
the GaN HEMT semiconductor device thin film structure comprises a semiconductor substrate layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer which are sequentially stacked;
the source electrode, the drain electrode and the metal gate electrode are formed on the GaN HEMT semiconductor device thin film structure and are in ohmic contact, and the source electrode and the drain electrode are respectively arranged at two ends of the metal gate electrode;
and the electrode supplement layer is at least formed on the GaN HEMT semiconductor device thin film structure extending from the surface of the source electrode to the projection region corresponding to the top of the metal gate electrode and on the metal gate electrode.
Optionally, the GaN HEMT semiconductor device thin film structure further comprises a GaN cap layer formed on the AlGaN barrier layer, and a protective layer is further formed on the GaN HEMT semiconductor device thin film structure, wherein the protective layer is made of at least one material selected from the group consisting of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, and zirconium oxide.
Optionally, the GaN HEMT semiconductor device further comprises a SiN passivation layer formed in a region from the drain electrode to the metal gate electrode, and the electrode supplement layer is further formed on the SiN passivation layer and electrically connected with the metal gate electrode.
Optionally, the electrode supplement layer is further formed on the GaN HEMT semiconductor device thin film structure extending from the surface of the drain electrode to the projection region corresponding to the top of the metal gate electrode.
Optionally, the thickness of the electrode supplementary layer is between 10nm and 50 nm.
As described above, according to the GaN HEMT semiconductor device and the preparation method thereof, the gate-last process is adopted, the metal gate electrode gradually increasing from bottom to top is formed, the metal gate electrode in the shape is used as a mask, and the electrode supplement layers of the source electrode and the drain electrode or the electrode supplement layers of the source electrode and the gate field plate are formed by secondary deposition, so that the distances between the source electrode and the metal gate electrode and between the drain electrode and the metal gate electrode are shortened, the access resistances of the source electrode and the drain electrode are reduced, the voltage resistance of the device is improved, and meanwhile, the metal gate electrode is prepared behind the source electrode and the drain electrode, so that the metal gate electrode is prevented from being damaged by the source and drain electrode preparation process, and the performance of; in addition, the whole structure is inclined at a certain angle and keeps rotating deposition in the process of secondary deposition of the electrode supplement layer, the distance between the electrode supplement layer subjected to secondary deposition and the metal gate electrode is further shortened, and the access resistance of the source and drain electrodes is further reduced.
Drawings
Fig. 1 is a schematic view showing the access resistance of a conventional GaN HEMT semiconductor device.
Fig. 2 is a process flow chart of a method for manufacturing a GaN HEMT semiconductor device according to a first embodiment of the present invention.
Fig. 3 is a schematic structural view of the GaN HEMT semiconductor device according to the first embodiment of the present invention in the step S1.
Fig. 4 is a schematic structural view illustrating the formation of the source electrode region and the drain electrode region in step S2 of the method for manufacturing a GaN HEMT semiconductor device according to the first embodiment of the present invention.
Fig. 5 is a schematic structural view illustrating the formation of the source electrode and the drain electrode in step S2 of the method for manufacturing a GaN HEMT semiconductor device according to the first embodiment of the present invention.
Fig. 6 is a schematic structural view of a SiN passivation layer deposited and formed in step S3 of the method for manufacturing a GaN HEMT semiconductor device according to the first embodiment of the present invention.
Fig. 7 is a schematic structural view of an opening in a metal gate electrode region formed in step S3 of the method for manufacturing a GaN HEMT semiconductor device according to the first embodiment of the present invention.
Fig. 8 is a schematic structural view of a metal gate electrode region formed in step S3 of the method for manufacturing a GaN HEMT semiconductor device according to the first embodiment of the present invention.
Fig. 9 is a schematic structural view of the GaN HEMT semiconductor device in the first embodiment of the present invention in the step S4.
Fig. 10 is a schematic structural view of the GaN HEMT semiconductor device in the first embodiment of the present invention in the step S5.
Fig. 11 is a schematic structural view showing the GaN HEMT semiconductor device according to the first embodiment of the present invention, in which the entire structure is tilted at a certain angle in step S6.
Fig. 12 is a schematic structural view of an electrode supplement layer formed in step S6 of the method for manufacturing a GaN HEMT semiconductor device according to the first embodiment of the present invention, wherein fig. 12 is a schematic structural view of a third GaN HEMT semiconductor device according to the first embodiment of the present invention.
Fig. 13 is a schematic structural view of the GaN HEMT semiconductor device of the second embodiment of the present invention in the step S5.
Fig. 14 is a schematic structural view of an electrode supplement layer formed in step S6 of the method for manufacturing a GaN HEMT semiconductor device according to the second embodiment of the present invention, wherein fig. 14 is a schematic structural view of a GaN HEMT semiconductor device according to the third embodiment of the present invention.
Description of the element reference numerals
The HEMT semiconductor device comprises a 100 GaN HEMT semiconductor device thin film structure, a 101 semiconductor substrate, a 102 AlGaN buffer layer, a 103 GaN channel layer, a 104 AlGaN barrier layer, a 105 source electrode region, a 106 drain electrode region, a 107 source electrode, a 108 drain electrode, a 109SiN passivation layer, a 109a SiN barrier protection layer, a 110 metal gate electrode region, a 111 metal gate electrode region opening, a 112 metal gate electrode, a 113a source electrode supplement layer, a 113b drain electrode supplement layer, a 113c metal gate electrode supplement layer, a 113d gate field plate, 114 graphical photoresist, 115 supporting tables, a beta inclination angle and steps S1-S6.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 2 to 14. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed according to specific needs, and the layout of the components may be more complicated.
Example one
The embodiment provides a preparation method of a GaN HEMT semiconductor device, which adopts a gate-last process (i.e. preparing a source electrode and a drain electrode firstly and then preparing a metal gate electrode), forms a metal gate electrode gradually increasing from bottom to top, and takes the metal gate electrode in the shape as a mask plate to form an electrode supplement layer of the source electrode and the drain electrode by secondary deposition, thereby shortening the distance between the source electrode and the metal gate electrode as well as between the drain electrode and the metal gate electrode, reducing the access resistance of the source electrode and the drain electrode, and simultaneously avoiding the damage of the preparation process of the source electrode and the drain electrode to the metal gate electrode and improving the performance of the device because the metal gate electrode is prepared behind the source electrode and the drain electrode; in addition, the whole structure is inclined at a certain angle and keeps rotating deposition in the process of secondary deposition of the electrode supplement layer, the distance between the electrode supplement layer subjected to secondary deposition and the metal gate electrode is further shortened, and the access resistance of the source and drain electrodes is further reduced.
As shown in fig. 2 to 12, the preparation method includes the steps of:
as shown in fig. 2 and 3, step S1 is performed to provide a GaN HEMT semiconductor device thin film structure 100, where the GaN HEMT semiconductor device thin film structure 100 includes a semiconductor substrate layer 101, an AlGaN buffer layer 102, a GaN channel layer 103, and an AlGaN barrier layer 104 in this order along the growth direction.
By way of example, the semiconductor substrate layer 101 may be any suitable semiconductor substrate, for example, the semiconductor substrate layer 101 may be a Si substrate, a SiC substrate, an aluminum nitride substrate, an aluminum oxide substrate, or a sapphire substrate, and in this embodiment, the semiconductor substrate layer 101 is preferably selected to be a SiC substrate.
The AlGaN buffer layer 102 is used to release stress generated between the epitaxially grown heterostructure and the substrate due to lattice mismatch and thermal mismatch, and may be, for example, a composite material layer in which an Al composition gradually decreases along a growth direction of the AlGaN buffer layer.
It should be noted here that the GaN HEMT semiconductor device thin film structure 100 may be grown by using an epitaxial technique, or may be obtained by outsourcing, as long as the structure can realize the subsequent GaN HEMT semiconductor device of the present embodiment.
As an example, the GaN HEMT semiconductor device thin film structure 100 may further include a GaN cap layer (not shown in the figure) formed on the AlGaN barrier layer 104, and the GaN cap layer may protect the AlGaN barrier layer 104, prevent the surface thereof from generating dangling bonds, effectively increase the barrier height, and facilitate the preparation of metal ohmic contacts of the source electrode and the drain electrode.
As shown in fig. 2, 4 and 5, step S2 is performed to define a source electrode region 105 and a drain electrode region 106 on the GaN HEMT semiconductor device thin film structure 100 by using a photolithography mask (as shown in fig. 4), and form a source electrode 107 and a drain electrode 108 (as shown in fig. 5) in ohmic contact with the source electrode region 105 and the drain electrode region 106.
As shown in fig. 4, as an example, a photoresist layer is formed on the GaN HEMT semiconductor device thin film structure 100; and photoetching and etching the photoresist layer by using a photoetching mask to form a patterned photoresist layer 114, wherein the windowing regions on the patterned photoresist layer 114 are the source electrode region 105 and the drain electrode region 106.
As shown in fig. 5, as an example, a metal layer is deposited on the patterned photoresist layer 114, and then the patterned photoresist layer 114 is removed to form a source electrode 107 and a drain electrode 108 on the source electrode region 105 and the drain electrode region 106. Preferably, the metal layer may be deposited by an electron beam evaporation process, and the metal layer is a stacked structure of Ti/Al/Ni/Au, and the thickness of each layer of metal material in the stacked structure may be set according to specific requirements, and in this embodiment, the thickness of each layer of metal material in the stacked structure is selected to be 30nm/120 nm/40 nm/60nm in sequence.
As a further preferred example, after the source electrode 107 and the drain electrode 108 of the ohmic contact are formed by using a rapid thermal annealing process (RTA), parameters of the rapid thermal annealing process are set according to actual conditions, and in this embodiment, the parameters of the rapid thermal annealing process are selected to be a rapid thermal annealing in an N2 environment with a temperature between 800 ℃ and 900 ℃ for 20 seconds to 90 seconds.
As an example, after the source electrode 107 and the drain electrode 108 are formed, an ion implantation process is further used to form a local passive region, so as to achieve electrical isolation between two adjacent GaN HEMT semiconductor devices. Preferably, the ion to be implanted may be hydrogen ion, helium ion, nitrogen ion, fluorine ion, magnesium ion, argon ion, zinc ion, etc., and nitrogen ion is preferred in this embodiment.
As shown in fig. 2, 6 and 8, step S3 is performed to deposit a SiN passivation layer 109 on the GaN HEMT semiconductor device thin film structure 100 (as shown in fig. 6), and form a metal gate electrode region 110 in the SiN passivation layer 109 (as shown in fig. 8), wherein the opening of the metal gate electrode region 110 gradually increases from bottom to top.
As shown in fig. 6, as an example, the lowermost layer of the SiN passivation layer 109 may be a SiN barrier protection layer 109a, that is, a layer directly contacting with the surface of the GaN HEMT semiconductor device thin film structure 100, the SiN barrier protection layer 109a has high density and is thin, the thickness is generally between 5nm and 20nm, and the SiN barrier protection layer has a main function of improving the interface quality through its high density, so as to protect the barrier layer. Preferably, the SiN barrier protection layer 109a may be deposited by LPCVD (low pressure chemical vapor deposition) process, and the deposition temperature is between 700 ℃ and 800 ℃.
As an example, a specific method for forming the metal gate electrode region 110 in the SiN passivation layer 109 includes: firstly, a SiN passivation layer 109 with a density gradually decreasing from bottom to top is formed on the GaN HEMT semiconductor device thin film structure 100 (as shown in fig. 6), wherein the density of the SiN passivation layer 109 is gradually decreasing from bottom to top and the density range is set according to specific situations, for example, the density of the SiN passivation layer 109 is gradually decreasing from bottom to top in the range of 2g/cm3~3g/cm3Meanwhile, any suitable deposition process may be adopted to form the SiN passivation layer 109, for example, in this embodiment, a PECVD (plasma enhanced chemical vapor deposition) process is selected to form the SiN passivation layer 109, and the density may be formed in the following manner and gradually decreases from bottom to top: firstly, the deposition temperature is gradually reduced in the bottom-up deposition process of PECVD, for example, the deposition temperature can be gradually reduced from 400 ℃ to 200 ℃, the influence of the pressure on the density is not great, and can be selected to be between 0.3Torr and 0.5Torr, so that the SiN passivation layer 109 with the density gradually reduced from bottom to top is formed, and secondly, the mixture ratio of a nitrogen ion gas source is gradually increased in the bottom-up deposition process of PECVD, for example, SiH is selected in the embodiment4And NH3As a deposition gas source, NH is sequentially increased in the PECVD bottom-up deposition process3The mixture ratio of (A) and (B) can be selected from SiH4:NH3The ratio of the density of the SiN passivation layer 109 is increased from 1:1 to 1:2 to 1:4 to 1:8 in sequence, or other increasing modes can be selected, specifically, the density of the SiN passivation layer 109 is gradually reduced from bottom to top according to actual needs, and the first mode and the second mode are combined together for use, wherein the setting of parameters is set according to the actual needs, so that the SiN passivation layer 109 with the density gradually reduced from bottom to top is formed; then, a photoresist layer is formed on the SiN passivation layer 109, and is etched by using a photolithography mask to form a patternPatterning the photoresist layer 114, wherein the open window region on the patterned photoresist layer 114 is a metal gate electrode region opening 111 (as shown in fig. 7); finally, the SiN passivation layer 109 is removed by the opening 111 of the metal gate electrode region through dry etching, because the density of the SiN passivation layer 109 is gradually reduced from bottom to top, while the dry etching rates of SiN materials with different densities (or called bulkiness) are different, the denser SiN material is etched more slowly, and the looser SiN material is etched more quickly, so the etching rate and the difficulty level are gradually increased from top to bottom, thereby forming the metal gate electrode region 110 (as shown in fig. 8) with gradually increased openings from bottom to top in the SiN passivation layer 109, the metal gate electrode region 110 is similar to an inverted trapezoid shape, in this embodiment, the SiN passivation layer 109 is removed by selectively adopting a reactive ion etching process (RIE), and the etching gas source is 90% -95% CF, and the etching gas source is selected from the group consisting of4And 5% -10% of O2The etching power is 500W-700W, and the etching gas source can be other fluorine-based etching gas and protective gas, such as SF6Ar, and the like.
As another example, a specific method for forming the metal gate electrode region 110 in the SiN passivation layer 109 includes: firstly, forming a SiN passivation layer 109 with uniform density from bottom to top on the GaN HEMT semiconductor device thin film structure 100 (as shown in fig. 6), wherein the density of the SiN passivation layer 109 is set according to specific conditions, and in addition, the SiN passivation layer 109 with uniform density can be formed by any existing suitable deposition process, for example, an LPCVD process or a PECVD process, in this embodiment, a PECVD (plasma enhanced chemical vapor deposition process) process is selected to form the SiN passivation layer 109 with uniform density; then, forming a photoresist layer on the SiN passivation layer 109, and performing photolithography by using a photolithography mask and etching the photoresist layer to form a patterned photoresist layer 114, wherein the open window region on the patterned photoresist layer 114 is a metal gate electrode region opening 111 (as shown in fig. 7); finally, the SiN passivation layer 109 with a part of the thickness is etched anisotropically by using a fluorine-based etching gas through the metal gate electrode region opening 111 by a dry method, and then the SiN passivation layer 109 with the remaining thickness is etched isotropically by using a phosphoric acid wet method, so that the metal gate electrode region 110 with the gradually increasing opening from bottom to top is formed.
As an example, the thickness of the SiN passivation layer 109 is between 100nm and 300 nm. It should be noted here that, when the SiN barrier protection layer 109a is disposed on the bottom layer of the SiN passivation layer 109, the shape of the etched metal gate electrode region 110 is similar to a funnel shape, and a column section with a short bottom of the funnel is formed when the SiN barrier protection layer 109a is etched, and the shape thereof does not have a great influence on a subsequently deposited electrode supplementary layer, so that the shape can be ignored, but the SiN barrier protection layer 109a may have a positive influence on the performance of the entire device.
As shown in fig. 2 and 9, step S4 is performed to form a metal gate electrode 112 in the metal gate electrode region 110. It should be noted that the metal gate electrode 112 may be filled in the metal gate electrode region 110, may be filled in and higher than the metal gate electrode region 110, and may also be filled in a part of the height of the metal gate electrode region 110 (as shown in fig. 9), which is set according to specific situations, and is not limited herein.
As an example, a photoresist layer is formed on the GaN HEMT semiconductor device thin film structure 100; then, photoetching and etching the photoresist layer by adopting a photoetching mask plate to form a graphical photoresist layer, wherein a windowing area on the graphical photoresist layer is a metal gate electrode deposition area window; a metal layer is deposited on the patterned photoresist layer based on the above, and then the patterned photoresist layer is removed, thereby forming a metal gate electrode 112 in the metal gate electrode region 110. Preferably, the metal layer may be formed by a thermal evaporation deposition process, and the metal layer is a Ni/Au stacked structure, the thickness of each metal material in the stacked structure may be set according to specific needs, and in this embodiment, the thickness of each metal material in the stacked structure is selected to be 30nm/120nm in sequence.
As shown in fig. 2 and 10, step S5 is performed to remove at least the SiN passivation layer 109 from the source electrode 107 to the metal gate electrode 112.
As shown in FIG. 10, this embodiment selectively removes all of the SiN passivation layer109, exposing the source electrode 107, the drain electrode 108, the metal gate electrode 112 and the area between the source electrode and the drain electrode, and protecting the rest by using a patterned photoresist 114. The SiN passivation layer 109 may be removed using any suitable method, such as, for example, wet BHF or H3PO4Or dry SF6Or CF4And (5) removing.
As shown in fig. 2 and 11 to 12, step S6 is finally performed to deposit an electrode supplement layer on the surface of the structure formed in the above steps, wherein the electrode supplement layer extends to a position close to the metal gate electrode 112 to reduce the access resistance of the GaN HEMT semiconductor device.
As shown in fig. 12, as an example, in the present embodiment, all the SiN passivation layer 109 is selectively removed, so the electrode supplement layers include a source electrode supplement layer 113a formed on the GaN HEMT semiconductor device thin film structure 100 in the projected area extending from the surface of the source electrode 107 to the top of the metal gate electrode 112, a drain electrode supplement layer 113b formed on the GaN HEMT semiconductor device thin film structure 100 in the projected area extending from the surface of the drain electrode 108 to the top of the metal gate electrode 112, and a metal gate electrode supplement layer 113c formed on the metal gate electrode 112. Preferably, the electrode supplement layer is a laminated structure of Ni/Au, and the thickness of each layer of metal material in the laminated structure can be set according to specific needs.
The metal gate electrode is used as a mask, a self-alignment process is utilized, an electrode supplement layer is deposited for the second time, and the electrode supplement layer covers the metal gate electrode and an access area of the source and drain electrodes at the same time, so that the access resistance of the source and drain electrodes is effectively reduced, meanwhile, due to the post-preparation of the metal gate electrode, the damage of the source and drain electrode preparation process to the metal gate electrode is avoided, the performance of a device is improved, and the gate width process of the metal gate electrode is simple, convenient and controllable; in addition, the electrode supplement layer can be realized only by one-step deposition process, and the process is simple and easy for batch production.
As shown in fig. 11, as an example, when the electrode supplement layer is deposited, the structure formed in the above step is tilted and the rotational deposition is maintained, and the tilt angle β is between 0 ° -30 °. Specifically, the structure formed in the above step is placed on the support table 115, and the support table 115 is tilted at an angle β while the entire structure is kept rotating during the deposition process to form the electrode supplement layer. The method can further shorten the distance between the electrode supplement layer of the secondary deposition and the metal gate electrode, and further reduce the access resistance of the source electrode and the drain electrode.
As an example, the thickness of the electrode supplementary layer is between 10nm and 50 nm.
As an example, after the forming of the electrode supplement layer, depositing a protective layer on the surface of the structure formed in the above step, where the material of the protective layer includes at least one of the group consisting of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, and zirconium oxide.
Example two
As shown in fig. 13 to 14, this embodiment provides another method for manufacturing a GaN HEMT semiconductor device, which is substantially the same as the method for manufacturing the GaN HEMT semiconductor device of the first embodiment except for steps S5 and S6, specifically:
as shown in fig. 13, in step S5, the SiN passivation layer 109 in the region from the source electrode 107 to the metal gate electrode 112 is selectively removed, the SiN passivation layer 109 in the region from the drain electrode 108 to the metal gate electrode 112 is remained, the source electrode 107, the metal gate electrode 112 and the region therebetween are exposed, and a patterned photoresist 114 is used for protection on the remaining portion of the SiN passivation layer 109 and on the side of the source electrode 107. The SiN passivation layer 109 may be removed using any suitable method, such as, for example, wet BHF or H3PO4Or dry SF6Or CF4And (5) removing.
As shown in fig. 14, in step S6, an electrode supplement layer is deposited on the surface of the structure formed in the above step, and the electrode supplement layer extends into the projection region corresponding to the top of the metal gate electrode 112 to reduce the access resistance of the GaN HEMT semiconductor device. Since the SiN passivation layer 109 is partially removed in step S5 and the remaining SiN passivation layer 109 is remained, after step S6, the electrode supplement layer includes a source electrode supplement layer 113a formed on the GaN HEMT semiconductor device thin film structure 100 in the projection region extending from the surface of the source electrode 107 to the top of the metal gate electrode 112, a metal gate electrode supplement layer 113c on the metal gate electrode 112, and a gate field plate 113d formed on the SiN passivation layer 109 in the region from the drain electrode 108 to the metal gate electrode 112, and the gate field plate 113d is electrically connected to the metal gate electrode supplement layer 113c to form a bias field plate.
For example, when the electrode supplement layer is formed in step S6 of this embodiment, the structure formed in the above step may be tilted and the rotational deposition is maintained, and the tilt angle β is between 0 ° and 30 °. The method can further shorten the distance between the electrode supplement layer of the secondary deposition and the metal gate electrode, and further reduce the access resistance of the source electrode.
In the step, a metal gate electrode is used as a mask, and a self-alignment process is utilized to deposit an electrode supplement layer for the second time, wherein the electrode supplement layer covers the metal gate electrode and the access region of the source electrode at the same time, and covers the SiN passivation layer of the drain electrode access region, so that a gate bias field plate connected with the gate electrode is formed. The preparation method has the advantages that the preparation of the source electrode self-aligned contact resistor and the gate field plate is realized simultaneously through one-step process, the access resistance of the device is effectively reduced, the voltage resistance of the device is improved, the process is simple, and the batch production is easy.
EXAMPLE III
This embodiment provides a GaN HEMT semiconductor device that can be fabricated using the fabrication method of the first or second embodiment, but is not limited to the fabrication method described in the first and second embodiments, as long as the GaN HEMT semiconductor device can be fabricated. For the beneficial effects of the GaN HEMT semiconductor device, please refer to the first embodiment and the second embodiment, which will not be described in detail below.
As shown in fig. 12 and 14, the GaN HEMT semiconductor device includes:
the GaN HEMT semiconductor device thin film structure 100 comprises a semiconductor substrate layer 101, an AlGaN buffer layer 102, a GaN channel layer 103 and an AlGaN barrier layer 104 which are sequentially stacked;
a source electrode 107, a drain electrode 108 and a metal gate electrode 112 which are formed on the GaN HEMT semiconductor device thin film structure 100 and are in ohmic contact with each other, wherein the source electrode 107 and the drain electrode 108 are respectively arranged at two ends of the metal gate electrode 112;
and an electrode supplement layer at least formed on the thin film structure 100 of the GaN HEMT semiconductor device and the metal gate electrode 112 in a projection region extending from the surface of the source electrode 107 to the top of the metal gate electrode 112.
As an example, the GaN HEMT semiconductor device thin film structure 100 further comprises a GaN cap layer formed on the AlGaN barrier layer 104, and a protective layer is further formed on the GaN HEMT semiconductor device thin film structure 100, wherein the material of the protective layer comprises at least one of the group consisting of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, and zirconium oxide.
As shown in fig. 12, the electrode supplement layer includes, as an example, a source electrode supplement layer 113a formed on the GaN HEMT semiconductor device thin film structure 100 extending from the surface of the source electrode 107 to the projected area corresponding to the top of the metal gate electrode 112, a drain electrode supplement layer 113b formed on the GaN HEMT semiconductor device thin film structure 100 extending from the surface of the drain electrode 108 to the projected area corresponding to the top of the metal gate electrode 112, and a metal gate electrode supplement layer 113c formed on the metal gate electrode 112.
As shown in fig. 14, as an example, the electrode supplement layer includes a source electrode supplement layer 113a formed on the GaN HEMT semiconductor device thin film structure 100 extending from the surface of the source electrode 107 to the projection region corresponding to the top of the metal gate electrode 112, a metal gate electrode supplement layer 113c on the metal gate electrode 112, and a gate field plate 113d formed on the SiN passivation layer 109 from the drain electrode 108 to the metal gate electrode 112, and the gate field plate 113d is electrically connected to the metal gate electrode supplement layer 113c to form a bias field plate.
As an example, the thickness of the electrode supplementary layer is between 10nm and 50 nm.
In summary, the invention provides a GaN HEMT semiconductor device and a preparation method thereof, wherein a gate-last process is adopted, a metal gate electrode gradually increasing from bottom to top is formed, the metal gate electrode in the shape is used as a mask, and an electrode supplement layer of a source electrode and a drain electrode or an electrode supplement layer of a source electrode and a gate field plate are formed by secondary deposition, so that the distances between the source electrode and the metal gate electrode and between the drain electrode and the metal gate electrode are shortened, the access resistances of the source electrode and the drain electrode are reduced, and the voltage resistance of the device is improved; in addition, the whole structure is inclined at a certain angle and keeps rotating deposition in the process of secondary deposition of the electrode supplement layer, the distance between the electrode supplement layer subjected to secondary deposition and the metal gate electrode is further shortened, and the access resistance of the source and drain electrodes is further reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (15)

1. A preparation method of a GaN HEMT semiconductor device is characterized by comprising the following steps:
providing a GaN HEMT semiconductor device thin film structure, wherein the GaN HEMT semiconductor device thin film structure sequentially comprises a semiconductor substrate layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer along the growth direction of the GaN HEMT semiconductor device thin film structure;
defining a source electrode area and a drain electrode area on the GaN HEMT semiconductor device thin film structure by using a photoetching mask, and forming a source electrode and a drain electrode which are in ohmic contact with each other in the source electrode area and the drain electrode area;
depositing a SiN passivation layer on the GaN HEMT semiconductor device thin film structure, and forming a metal gate electrode region in the SiN passivation layer, wherein the opening of the metal gate electrode region is gradually increased from bottom to top;
forming a metal gate electrode in the metal gate electrode region;
removing at least the SiN passivation layer from the source electrode to the metal gate electrode region;
and depositing an electrode supplement layer on the surface of the structure formed in the step, wherein the electrode supplement layer extends into a projection region corresponding to the top of the metal gate electrode so as to reduce the access resistance of the GaN HEMT semiconductor device.
2. The method for manufacturing a GaN HEMT semiconductor device according to claim 1, wherein: the GaN HEMT semiconductor device thin film structure also comprises a GaN cap layer formed on the AlGaN barrier layer; and forming the source electrode and the drain electrode which are in ohmic contact by adopting an annealing process, wherein the annealing temperature is between 800 and 900 ℃, and the annealing time is between 20 and 90 seconds.
3. The method for manufacturing a GaN HEMT semiconductor device according to claim 1, wherein: the forming of the electrode supplementary layer further comprises depositing a protective layer on the surface of the structure formed in the above step, wherein the material of the protective layer comprises at least one of the group consisting of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide and zirconium oxide.
4. The method for manufacturing a GaN HEMT semiconductor device according to claim 1, wherein: and when the electrode supplement layer is formed by deposition, inclining the structure formed in the step and keeping the structure in rotary deposition, wherein the inclination angle is between 0 and 30 degrees.
5. The method for manufacturing a GaN HEMT semiconductor device according to claim 1, wherein: and removing the SiN passivation layer from the source electrode to the metal gate electrode region, reserving the SiN passivation layer from the drain electrode to the metal gate electrode region, and forming the electrode supplement layer on the GaN HEMT semiconductor device thin film structure extending from the surface of the source electrode to the projection region corresponding to the top of the metal gate electrode, on the metal gate electrode and on the SiN passivation layer from the drain electrode to the metal gate electrode region.
6. The method for manufacturing a GaN HEMT semiconductor device according to claim 1, wherein: and removing all the SiN passivation layer, wherein the electrode supplement layer is formed on the GaN HEMT semiconductor device thin film structure extending from the surface of the source electrode to the projection region corresponding to the top of the metal gate electrode, the GaN HEMT semiconductor device thin film structure extending from the surface of the drain electrode to the position close to the metal gate electrode and the metal gate electrode.
7. The method for manufacturing a GaN HEMT semiconductor device according to claim 1, wherein: the lowest layer of the SiN passivation layer is a SiN barrier protection layer with the thickness of 5 nm-20 nm, and the SiN barrier protection layer is formed by an LPCVD process.
8. The method for manufacturing the GaN HEMT semiconductor device according to claim 1, wherein the density of the SiN passivation layer is gradually reduced from bottom to top, and is between 2g/cm3~3g/cm3The step of forming the metal gate electrode region in the SiN passivation layer may comprise: and forming a metal gate electrode region opening by using a photoetching mask, removing the SiN passivation layer by adopting dry etching, and gradually reducing the density of the SiN passivation layer from bottom to top so as to form the metal gate electrode region with the gradually increased opening from bottom to top.
9. The method of manufacturing a GaN HEMT semiconductor device according to claim 8, wherein said SiN passivation layer is formed by a PECVD process comprising: gradually reducing the deposition temperature of the PECVD process from bottom to top and/or gradually increasing the proportion of a nitrogen ion gas source from bottom to top; and removing the SiN passivation layer by adopting a reactive ion etching process.
10. The method for manufacturing a GaN HEMT semiconductor device according to claim 1, wherein: the density of the SiN passivation layer is uniform from bottom to top, and the step of forming the metal gate electrode region in the SiN passivation layer comprises the following steps: and forming an opening of a metal gate electrode region by using a photoetching mask, then anisotropically etching the SiN passivation layer with partial thickness by using a fluorine-based etching gas dry method, and finally isotropically etching the SiN passivation layer with the residual thickness by using a phosphoric acid wet method, thereby forming the metal gate electrode region with gradually increased opening from bottom to top.
11. A GaN HEMT semiconductor device, characterized in that said device comprises:
the GaN HEMT semiconductor device thin film structure comprises a semiconductor substrate layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer which are sequentially stacked;
the source electrode, the drain electrode and the metal gate electrode are formed on the GaN HEMT semiconductor device thin film structure and are in ohmic contact, and the source electrode and the drain electrode are respectively arranged at two ends of the metal gate electrode;
and the electrode supplement layer is at least formed on the GaN HEMT semiconductor device thin film structure extending from the surface of the source electrode to the projection region corresponding to the top of the metal gate electrode and on the metal gate electrode.
12. The GaN HEMT semiconductor device of claim 11, wherein: the GaN HEMT semiconductor device thin film structure further comprises a GaN cap layer formed on the AlGaN barrier layer, a protective layer is further formed on the GaN HEMT semiconductor device thin film structure, and the protective layer is made of at least one of the group consisting of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide and zirconium oxide.
13. The GaN HEMT semiconductor device of claim 11, wherein: the GaN HEMT semiconductor device further comprises a SiN passivation layer formed in the region from the drain electrode to the metal gate electrode, and the electrode supplement layer is further formed on the SiN passivation layer and electrically connected with the metal gate electrode.
14. The GaN HEMT semiconductor device of claim 11, wherein: the electrode supplement layer is also formed on the GaN HEMT semiconductor device thin film structure which extends from the surface of the drain electrode to the projection area corresponding to the top of the metal gate electrode.
15. The GaN HEMT semiconductor device of claim 11, wherein: the thickness of the electrode supplementary layer is between 10nm and 50 nm.
CN202010672036.XA 2020-07-14 2020-07-14 GaN HEMT semiconductor device and preparation method thereof Pending CN111564491A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0591646A2 (en) * 1992-08-29 1994-04-13 Daimler-Benz Aktiengesellschaft Process for manufacturing a self-aligned field effect transistor
US7804114B1 (en) * 2006-09-08 2010-09-28 Hrl Laboratories, Llc Tiered gate device with source and drain extensions
US20100276698A1 (en) * 2009-04-29 2010-11-04 Cree, Inc. Gate electrodes for millimeter-wave operation and methods of fabrication
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Application publication date: 20200821