CN113035935A - GaN device and preparation method - Google Patents
GaN device and preparation method Download PDFInfo
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- CN113035935A CN113035935A CN202110269231.2A CN202110269231A CN113035935A CN 113035935 A CN113035935 A CN 113035935A CN 202110269231 A CN202110269231 A CN 202110269231A CN 113035935 A CN113035935 A CN 113035935A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 154
- 239000002184 metal Substances 0.000 claims abstract description 154
- 230000004888 barrier function Effects 0.000 claims abstract description 113
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 85
- 239000000758 substrate Substances 0.000 claims description 19
- 238000003475 lamination Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000004891 communication Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 21
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 19
- 230000017525 heat dissipation Effects 0.000 abstract description 9
- 229910002601 GaN Inorganic materials 0.000 description 82
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 73
- 238000010586 diagram Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
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- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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Abstract
The invention provides a GaN device and a preparation method thereof.A structure of an AlGaN barrier layer with gradually changed thickness from a metal gate to a metal drain is used for gradually changing the two-dimensional electron gas concentration from the metal gate to the metal drain in a GaN channel, so that the electric field peak value of the GaN device is relieved, and the pressure resistance of the GaN device is improved; furthermore, the metal drain electrode positioned on the inclined side wall of the first groove can be used as a field plate of a drain end at the same time so as to adjust the electric field intensity and improve the withstand voltage; furthermore, when the metal drain electrode is filled in the first groove and the second groove, a double-grid GaN device can be manufactured, and the metal drain electrode can be used as a field plate to adjust an electric field and can also be used as a metal heat dissipation column to improve the heat dissipation capacity of the GaN device.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a GaN device and a preparation method thereof.
Background
In semiconductor devices, the surface and interface characteristics of the material are very important. Although the surface and interface are only a small fraction compared to bulk materials, they can be critical points in determining device characteristics. For example, very common problems in power semiconductor devices are: the junction surface of the PN junction has a curved surface, and the device is easy to break down at the curved surface junction because the electric field at the curved surface junction is large. In order to improve the breakdown voltage of the device, the electric field distribution of the device on the surface or the interface can be adjusted and controlled by changing the appearance of the edge surface of the device or finely adjusting the structure of the device. Common methods for changing the edge topography include mesa etching and wafer bevel polishing; the structure of the trimming device is commonly added with a field plate and an empty field ring.
As a representative of the third generation semiconductor materials, gallium nitride (GaN) has many excellent characteristics such as a high critical breakdown electric field, high electron mobility, a high two-dimensional electron gas concentration, and good high-temperature operation ability. Therefore, the third generation semiconductor device based on GaN is now widely used in base stations, communication, radar, satellite, navigation system, etc. due to its high voltage endurance and high power.
For the GaN device, in order to improve the withstand voltage of the GaN device, the withstand voltage of the GaN device is generally improved by adding field plates, that is, adding field plates in the source electrode, the gate electrode and the drain electrode to relieve the peak value of the electric field, but adding the field plates will undoubtedly increase the process of the GaN device, and will also introduce additional parasitics, thereby affecting the frequency performance of the GaN device.
Therefore, it is necessary to provide a novel GaN device and a method for manufacturing the same.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a GaN device and a fabrication method thereof, which are used to solve the problem of voltage endurance of the GaN device in the prior art.
To achieve the above and other related objects, the present invention provides a GaN device and a method for fabricating the same, comprising the steps of:
providing a substrate;
forming an epitaxial lamination on the substrate, wherein the epitaxial lamination comprises a GaN channel layer and an AlGaN barrier layer which are stacked from bottom to top;
patterning the AlGaN barrier layer, and forming a first groove in the AlGaN barrier layer, wherein the first groove penetrates through the AlGaN barrier layer to expose part of the GaN channel layer, the opening width of the first groove is greater than the bottom width, and a preset included angle is formed between the inclined side wall of the first groove and the horizontal direction;
patterning the exposed GaN channel layer from the first groove to form a second groove, wherein the second groove penetrates through the 2DEG region;
forming a metal source electrode and a metal drain electrode on the AlGaN barrier layer, wherein the metal drain electrode is contacted with the inclined side wall of the first groove, the AlGaN barrier layer adjacent to the metal source electrode has a first thickness, the AlGaN barrier layer adjacent to the metal drain electrode has a second thickness, and the first thickness is larger than the second thickness;
and forming a metal gate between the metal source and the metal drain on the AlGaN barrier layer.
Optionally, the preset included angle between the inclined side wall of the first groove and the horizontal direction is in a range of 45 ° to 60 °.
Optionally, the metal drain is formed to completely cover the inclined sidewall of the first groove or partially cover the inclined sidewall of the first groove; the metal drain is formed with a trench therein, the trench penetrating the metal drain or the metal drain being formed filling the first and second recesses.
Optionally, after the second groove is formed and before the metal drain is formed, a step of forming an n-GaN ohmic contact auxiliary layer by in-situ deposition at the bottom of the second groove is further included.
Optionally, the AlGaN barrier layer is Al stacked from bottom to top in sequence0.1Ga0.9N/Al0.2Ga0.8N/Al0.3Ga0.7The N barrier lamination layer or the AlGaN barrier layer is Al laminated from bottom to top in sequence0.1Ga0.9N/Al0.2Ga0.8N/Al0.3Ga0.7N/AlN/Al0.3Ga0.7An N-barrier stack.
The present invention also provides a GaN device, comprising:
a substrate;
the epitaxial lamination comprises a GaN channel layer and an AlGaN barrier layer which are stacked from bottom to top;
the first groove penetrates through the AlGaN barrier layer to expose part of the GaN channel layer, the opening width of the first groove is larger than the bottom width, and a preset included angle is formed between the inclined side wall of the first groove and the horizontal direction;
a second groove in the GaN channel layer and in communication with the first groove, the second groove penetrating the 2DEG region;
the metal source electrode and the metal drain electrode are positioned on the AlGaN barrier layer, the metal drain electrode is contacted with the inclined side wall of the first groove, the AlGaN barrier layer close to the metal source electrode has a first thickness, the AlGaN barrier layer close to the metal drain electrode has a second thickness, and the first thickness is larger than the second thickness;
a metal gate on the AlGaN barrier layer and between the metal source and the metal drain.
Optionally, the preset included angle between the inclined side wall of the first groove and the horizontal direction is in a range of 45 ° to 60 °.
Optionally, the metal drain completely covers the inclined sidewall of the first groove or partially covers the inclined sidewall of the first groove; the metal drain electrode is provided with a groove which penetrates through the metal drain electrode or fills the first groove and the second groove.
Optionally, the bottom of the second groove further comprises an n-GaN ohmic contact auxiliary layer.
Optionally, the AlGaN barrier layer is Al stacked from bottom to top in sequence0.1Ga0.9N/Al0.2Ga0.8N/Al0.3Ga0.7The N barrier lamination layer or the AlGaN barrier layer is Al laminated from bottom to top in sequence0.1Ga0.9N/Al0.2Ga0.8N/Al0.3Ga0.7N/AlN/Al0.3Ga0.7An N-barrier stack.
As described above, according to the GaN device and the preparation method of the GaN device of the present invention, the thickness of the AlGaN barrier layer gradually changes from the metal gate to the metal drain, that is, the barrier in the direction from the metal gate to the metal drain gradually becomes thinner, so that the two-dimensional electron gas concentration in the channel gradually decreases, and the two-dimensional electron gas concentration from the metal gate to the metal drain in the GaN channel is gradually changed, thereby alleviating the electric field peak of the GaN device and improving the voltage withstanding performance of the GaN device; furthermore, the metal drain electrode positioned on the inclined side wall of the first groove can be used as a field plate of a drain end at the same time so as to adjust the electric field intensity and improve the withstand voltage; furthermore, when the metal drain electrode is filled in the first groove and the second groove, a double-grid GaN device can be manufactured, and the metal drain electrode can be used as a field plate to adjust an electric field and can also be used as a metal heat dissipation column to improve the heat dissipation capacity of the GaN device.
Drawings
FIG. 1 is a flow chart of a process for fabricating a GaN device according to an embodiment of the invention.
Fig. 2a and 2b are schematic structural diagrams illustrating the formation of an epitaxial stack according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of the structure of fig. 2a after a patterned mask is formed on the epitaxial stack.
Fig. 4 is a schematic structural diagram illustrating a patterned AlGaN barrier layer after a first groove is formed in the AlGaN barrier layer according to the embodiment of the present invention.
Fig. 5 is a schematic structural view after a second recess is formed in the GaN channel layer in the embodiment of the present invention.
Fig. 6a to 6d are schematic structural diagrams illustrating a metal source and a metal drain formed according to an embodiment of the invention.
Fig. 7a to 7d are schematic structural views illustrating the formation of a metal gate and a passivation layer corresponding to fig. 6a to 6d, respectively.
FIG. 8 is a schematic structural diagram of a GaN device with an n-GaN ohmic contact auxiliary layer formed in an embodiment of the invention.
Description of the element reference numerals
A 100-GaN channel layer; a 200-AlGaN barrier layer; 201-Al0.1Ga0.9An N barrier layer; 202-Al0.2Ga0.8An N barrier layer; 203-Al0.3Ga0.7An N barrier layer; 204-AlN layer; 205-Al0.3Ga0.7An N barrier layer; 300-masking; 401 — a first groove; 402-a second groove; 403-trenches; 404-n-GaN ohmic contact auxiliary layer; 501-metal source; 502-metal drain; 503-metal gate; 600-a passivation layer; an A-2DEG region; a-opening width; b-bottom width; c-an inclined side wall; theta-a preset included angle.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1, the present embodiment provides a method for fabricating a GaN device, and referring to fig. 2a to 8, the steps for fabricating the GaN device are described below with reference to the accompanying drawings.
In the embodiment, the AlGaN barrier layer has a structure in which the thickness gradually changes from the metal gate to the metal drain, that is, the barrier in the direction from the metal gate to the metal drain gradually becomes thinner, so that the concentration of the two-dimensional electron gas in the channel gradually decreases, and the concentration of the 2DEG (two-dimensional electron gas) from the metal gate to the metal drain in the GaN channel is gradually changed, thereby alleviating the electric field peak value of the GaN device and improving the voltage resistance of the GaN device; furthermore, the metal drain electrode positioned on the inclined side wall of the first groove can be used as a field plate of a drain end at the same time so as to adjust the electric field intensity and improve the withstand voltage; furthermore, when the metal drain electrode is filled in the first groove and the second groove, a double-grid GaN device can be manufactured, and the metal drain electrode can be used as a field plate to adjust an electric field and can also be used as a metal heat dissipation column to improve the heat dissipation capacity of the GaN device.
The specific steps for preparing the GaN device comprise:
first, a substrate (not shown) is provided, and an epitaxial stack including a GaN channel layer 100 and an AlGaN barrier layer 200 stacked from bottom to top is formed on the substrate.
Specifically, the substrate may include one of a Si substrate, a SiC substrate, a GaN substrate, and a sapphire substrate, but the material selected for the substrate is not limited thereto. In this embodiment, the substrate may be a Si (111) substrate to meet the requirement of cost saving, and the (111) oriented Si substrate is favorable for the growth of the subsequent GaN material based on the lattice adaptability, wherein the size of the substrate may be 8 inch wafer, 12 inch wafer, etc., without being limited too much. Next, the epitaxial stack is formed on the substrate, and the epitaxial stack includes the GaN channel layer 100 and the AlGaN barrier layer.
As an example, the AlGaN barrier layer 200 may be Al stacked in sequence from bottom to top0.1Ga0.9N/Al0.2Ga0.8N/Al0.3Ga0.7The N barrier lamination layer or the AlGaN barrier layer is Al laminated from bottom to top in sequence0.1Ga0.9N/Al0.2Ga0.8N/Al0.3Ga0.7N/AlN/Al0.3Ga0.7An N-barrier stack.
Specifically, referring to fig. 2a, the AlGaN barrier layer 200 is Al stacked in sequence0.1Ga0.9 N barrier layer 201, Al0.2Ga0.8 N barrier layer 202 and Al0.3Ga0.7An N barrier layer 203 to form a barrier stack on the surface of the GaN channel layer 100, wherein the Al is0.1Ga0.9 N barrier layer 201, Al0.2Ga0.8 N barrier layer 202 and Al0.3Ga0.7N potential barrierThe thickness of the layer 203 can be 5nm, but the structure and thickness of the AlGaN barrier layer 200 are not limited thereto, and the AlGaN barrier layer 200 can also be Al stacked in sequence, as shown in FIG. 2b0.1Ga0.9 N barrier layer 201, Al0.2Ga0.8 N barrier layer 202 and Al0.3Ga0.7 N barrier layer 203, AlN layer 204, and Al0.3Ga0.7An N barrier layer 205 to form a barrier stack on the surface of the GaN channel layer 100, wherein the Al is0.1Ga0.9 N barrier layer 201, Al0.2Ga0.8 N barrier layer 202 and Al0.3Ga0.7 N barrier layer 203 and Al0.3Ga0.7The N-barrier layers 205 may each be 5nm thick, and the AlN layer 204 may be 1nm thick. In this embodiment, the following fabrication steps are described by taking the barrier stack structure in fig. 2a as an example, but the structure and thickness of the AlGaN barrier layer 200 are not limited thereto.
Next, referring to fig. 3 to 4, the AlGaN barrier layer 200 is patterned, a first groove 401 is formed in the AlGaN barrier layer 200, the first groove 401 penetrates through the AlGaN barrier layer 200 to expose a portion of the GaN channel layer 100, an opening width a of the first groove 401 is greater than a bottom width b, and a preset included angle θ is formed between an inclined sidewall c of the first groove and the horizontal direction.
As an example, the preset included angle θ between the inclined sidewall c of the first groove 401 and the horizontal direction ranges from 45 ° to 60 °.
Specifically, referring to fig. 3, a mask 300, such as a photoresist, may be formed on the AlGaN barrier layer, or the mask 300 may also be a photoresist stack including silicon nitride and covering the silicon nitride, so as to form the inclined sidewall c of the first groove 401 through exposure, development, high temperature reflow, etc., and the type of the mask 300 is not limited herein. Then, the mask 300 is patterned, and the AlGaN barrier layer 200 is etched by, for example, ICP dry etching, to form the first groove 401 having a slope of 45 ° to 60 °, that is, the preset included angle θ between the inclined sidewall c of the first groove 401 and the horizontal direction is 45 ° to 60 °, such as 45 °, 50 °, (e.g., n-y,60 DEG, etc., so that the thickness of the AlGaN barrier layer 200 near the source side is 15nm to 25nm, such as 15nm, 20nm, 25nm, etc., and the thickness of the AlGaN barrier layer 200 near the drain side is a gradually changing structure of 5nm to 15nm, such as 5nm, 10nm, 15nm, etc., so as to form the first groove 401 having an inverted trapezoidal profile in the AlGaN barrier layer 200, wherein the etching conditions may be a pressure of 2.5mT, an ICP power of 1000W, a bias power of 220W, and Cl2The flow rate was 20sccm, N2The flow rate was 45 sccm.
Because the AlGaN barrier layer 200 controls the density of the two-dimensional electron gas in the GaN channel layer 100, when the Al composition in the AlGaN barrier layer 200 is higher, the higher the electron density can be polarized in the GaN channel layer 100, and when the AlGaN barrier layer 200 is thicker, the higher the electron density can be polarized, so that the 2DEG concentration from the gate to the drain in the GaN channel layer 100 can be gradually changed through the structure in which the thickness of the AlGaN barrier layer 200 is gradually changed from the gate to the drain, and the stacked structure in which the Al composition in the AlGaN barrier layer 200 is gradually changed, thereby alleviating the electric field peak of the GaN device and improving the voltage endurance of the GaN device.
Next, referring to fig. 5, the GaN channel layer 100 exposed from the first recess 401 is patterned to form a second recess 402, and the second recess 402 penetrates through the 2DEG region a.
Specifically, the etching depth of the second groove 402 exceeds the 2DEG region a, and stops in the GaN channel layer 100, so as to be applied as an isolation structure through the second groove 402.
Next, referring to fig. 6a to 6d, a metal source 501 and a metal drain 502 are formed on the AlGaN barrier 200, the metal drain 502 is in contact with the inclined sidewall c of the first groove 401, the AlGaN barrier 200 adjacent to the metal source 501 has a first thickness, the AlGaN barrier 200 adjacent to the metal drain 502 has a second thickness, and the first thickness is greater than the second thickness.
Specifically, the method for forming the metal source 501 and the metal drain 502 may include:
defining the regions of the metal source 501 and the metal drain 502 by photolithography through a mask;
depositing metal Ti/Al/Ni/Au, and stripping a mask;
annealing at 850 ℃ for 30s forms the metal source 501 and the metal drain 502 with ohmic contacts.
The method for forming the metal source 501 and the metal drain 502 is not limited thereto. Because the first groove 401 has the inclined sidewall c, and the preset included angle θ is formed between the inclined sidewall c and the horizontal direction, the first thickness of the AlGaN barrier layer 200 adjacent to the metal source 501 is greater than the second thickness of the AlGaN barrier layer 200 adjacent to the metal drain 502, so that the 2DEG concentration in the GaN channel layer 100 from the gate to the drain can be gradually changed through the structure in which the thickness of the AlGaN barrier layer 200 gradually changes from the gate to the drain and the stacked structure in which the Al composition of the AlGaN barrier layer 200 gradually changes, thereby alleviating the electric field peak of the GaN device and improving the voltage withstanding performance of the GaN device.
As an example, the metal drain 502 may be formed to completely cover the inclined sidewall c of the first recess 401 or the metal drain 502 may partially cover the inclined sidewall c of the first recess 401.
Specifically, referring to fig. 6a, the metal drain 502 is formed to completely cover the inclined sidewall c of the first recess 401, and fig. 6b illustrates the metal drain 502 is formed to partially cover the inclined sidewall c of the first recess 401.
Further, the metal drain 502 may be formed with a trench 403 therein, the trench 403 penetrating the metal drain 502 or the metal drain 502 being formed filling the first recess 401 and the second recess 402.
Specifically, referring to fig. 6a and 6b, the metal drain 502 is formed with the trench 403 therein, and the trench 403 penetrates the metal drain 502 so that the trench 403 can be used as an isolation structure. Fig. 6c and 6d illustrate the metal drain 502 formed to fill the first recess 401 and the second recess 402, and the metal drain 502 formed in fig. 6c completely covers the inclined sidewall c of the first recess 401, and fig. 6d illustrates the metal drain 502 formed to partially cover the inclined sidewall c of the first recess 401. When the metal drain 502 fills the first groove 401 and the second groove 402, the metal drain can be used as a common drain for preparing a dual-gate GaN device, and the metal drain extending into the second groove 402 can be used as a longitudinal field plate for adjusting a drain electric field, so that the withstand voltage of the device is improved, and the heat dissipation of the GaN device can be enhanced through the metal drain 502.
Next, referring to fig. 7a to 7d, a metal gate 503 is formed on the AlGaN barrier layer 200 between the metal source 501 and the metal drain 502.
Specifically, the gate region may be defined by photolithography through a mask, and then the metal Ni/Au is deposited, and then the mask is stripped off to form the metal gate 503. The metal gate 503 is deposited on the surface of the AlGaN barrier layer 200, and the AlGaN barrier layer 200 is etched, so that a shape in which the thickness gradually changes from the metal gate 503 to the metal drain 502 can be formed, and thus two-dimensional electron gas from the gate leg to the drain direction is less than two-dimensional electron gas from the gate leg to the source direction, thereby relieving the concentration density of an electric field and improving the withstand voltage of the GaN device.
Further, after the metal gate 503 is formed, a passivation layer 600 may be further formed to protect the metal electrode and the AlGaN barrier layer 200 through the passivation layer 600, wherein the passivation layer 600 may be made of, but is not limited to, silicon nitride. Fig. 7a to 7d are schematic structural diagrams corresponding to fig. 6a to 6d after the metal gate 503 and the passivation layer 600 are formed.
Further, after the second groove 402 is formed and before the metal drain 502 is formed, a step of forming an n-GaN ohmic contact auxiliary layer 404 at the bottom of the second groove 402 is further included.
Specifically, referring to fig. 8, after etching away the AlGaN barrier layer 200, it can be native to MOCVDThe GaN channel layer 100 is etched in place, wherein the etching temperature can be 700-1000 deg.C, such as 700 deg.C, 800 deg.C, 1000 deg.C, etc., and the etching gas source can be NH with a flow rate of 10-20 sccm3Such as 10sccm, 15sccm and 20sccm, and TBCl with a flow rate of 1sccm to 5sccm, such as 1sccm, 2sccm and 5sccm, and the pressure can be 50mbar to 100mbar, such as 50mbar, 80mbar and 100 mbar. The TBCl containing Cl gas source can etch the GaN channel layer 100, and can eliminate the damage in the plasma etching process in the previous process, so as to provide a good interface for forming the n-GaN ohmic contact auxiliary layer 404. Thereafter, the n-GaN ohmic contact auxiliary layer 404 may be deposited in situ on the GaN channel layer 100 in the same MOCVD chamber to avoid contamination of the sample from exposure to air. The thickness of the n-GaN ohmic contact auxiliary layer 404 deposited in situ may be 5nm to 50nm, such as 5nm, 10nm, 25nm, 50nm, etc., so as to form a highly doped layer through the n-GaN ohmic contact auxiliary layer 404 to optimize ohmic contact, and then the metal drain 502 is filled in the second groove 402 to form a dual gate structure as a common drain.
Further, when the formed metal drain 502 is laid on the AlGaN barrier layer 200, the metal drain 502 can also be used as a field plate at a drain end to further adjust the electric field strength and improve the withstand voltage.
Referring to fig. 2a and fig. 8, the present embodiment further provides a GaN device, which can be prepared by the above-mentioned preparation method, but is not limited thereto, and details about the material and the preparation method of the GaN device are not described herein.
Specifically, the GaN device includes:
a substrate (not shown);
an epitaxial stack comprising a GaN channel layer 100 and an AlGaN barrier layer 200 stacked from bottom to top;
a first groove 401, wherein the first groove 401 penetrates through the AlGaN barrier layer 200 to expose a portion of the GaN channel layer 100, an opening width a of the first groove 401 is greater than a bottom width b, and a preset included angle θ is formed between an inclined sidewall of the first groove 401 and a horizontal direction;
a second groove 402, the second groove 402 being located in the GaN channel layer 100 and communicating with the first groove 401, and the second groove 402 penetrating the 2DEG region a;
a metal source 501 and a metal drain 502, wherein the metal source 501 and the metal drain 502 are located on the AlGaN barrier 200, the metal drain 502 is in contact with the inclined sidewall c of the first groove 401, the AlGaN barrier 200 adjacent to the metal source 501 has a first thickness, the AlGaN barrier 200 adjacent to the metal drain 502 has a second thickness, and the first thickness is greater than the second thickness;
a metal gate 503, the metal gate 503 being located on the AlGaN barrier layer 200 and between the metal source 501 and the metal drain 502.
As an example, the preset included angle θ between the inclined sidewall c of the first groove 401 and the horizontal direction ranges from 45 ° to 60 °.
As an example, the metal drain 502 completely covers the inclined sidewall c of the first groove 401 or partially covers the inclined sidewall c of the first groove 401; the metal drain 502 has a trench 403 therein, the trench 403 penetrates the metal drain 502 and communicates with the second recess 402 or the metal drain 502 fills the first recess 401 and the second recess 402.
As an example, an n-GaN ohmic contact auxiliary layer 404 is further included at the bottom of the second groove 402.
As an example, the AlGaN barrier layer 200 is Al stacked in sequence from bottom to top0.1Ga0.9N/Al0.2Ga0.8N/Al0.3Ga0.7The N barrier lamination layer or the AlGaN barrier layer 200 is Al laminated from bottom to top in sequence0.1Ga0.9N/Al0.2Ga0.8N/Al0.3Ga0.7N/AlN/Al0.3Ga0.7An N-barrier stack.
In summary, the GaN device and the preparation method of the invention gradually change the two-dimensional electron gas concentration from the metal gate to the metal drain in the GaN channel by the structure that the thickness of the AlGaN barrier layer gradually changes from the metal gate to the metal drain, that is, the barrier of the metal gate gradually becomes thinner toward the metal drain, so that the two-dimensional electron gas concentration in the channel gradually decreases, thereby alleviating the electric field peak value of the GaN device and improving the pressure resistance of the GaN device; furthermore, the metal drain electrode positioned on the inclined side wall of the first groove can be used as a field plate of a drain end at the same time so as to adjust the electric field intensity and improve the withstand voltage; furthermore, when the metal drain electrode is filled in the first groove and the second groove, a double-grid GaN device can be manufactured, and the metal drain electrode can be used as a field plate to adjust an electric field and can also be used as a metal heat dissipation column to improve the heat dissipation capacity of the GaN device.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A preparation method of a GaN device is characterized by comprising the following steps:
providing a substrate;
forming an epitaxial lamination on the substrate, wherein the epitaxial lamination comprises a GaN channel layer and an AlGaN barrier layer which are stacked from bottom to top;
patterning the AlGaN barrier layer, and forming a first groove in the AlGaN barrier layer, wherein the first groove penetrates through the AlGaN barrier layer to expose part of the GaN channel layer, the opening width of the first groove is greater than the bottom width, and a preset included angle is formed between the inclined side wall of the first groove and the horizontal direction;
patterning the exposed GaN channel layer from the first groove to form a second groove, wherein the second groove penetrates through the 2DEG region;
forming a metal source electrode and a metal drain electrode on the AlGaN barrier layer, wherein the metal drain electrode is contacted with the inclined side wall of the first groove, the AlGaN barrier layer adjacent to the metal source electrode has a first thickness, the AlGaN barrier layer adjacent to the metal drain electrode has a second thickness, and the first thickness is larger than the second thickness;
and forming a metal gate between the metal source and the metal drain on the AlGaN barrier layer.
2. The method of manufacturing a GaN device according to claim 1, wherein: the range of the preset included angle between the inclined side wall of the first groove and the horizontal direction comprises 45-60 degrees.
3. The method of manufacturing a GaN device according to claim 1, wherein: the metal drain electrode is formed to completely cover the inclined side wall of the first groove or partially cover the inclined side wall of the first groove; the metal drain is formed with a trench therein, the trench penetrating the metal drain or the metal drain being formed filling the first and second recesses.
4. The method of manufacturing a GaN device according to claim 1, wherein: after the second groove is formed and before the metal drain electrode is formed, the method further comprises the step of forming an n-GaN ohmic contact auxiliary layer on the bottom of the second groove in an in-situ deposition mode.
5. The method of manufacturing a GaN device according to claim 1, wherein: the AlGaN barrier layer is Al which is overlapped from bottom to top in sequence0.1Ga0.9N/Al0.2Ga0.8N/Al0.3Ga0.7The N barrier lamination layer or the AlGaN barrier layer is Al laminated from bottom to top in sequence0.1Ga0.9N/Al0.2Ga0.8N/Al0.3Ga0.7N/AlN/Al0.3Ga0.7An N-barrier stack.
6. A GaN device, characterized in that the GaN device comprises:
a substrate;
the epitaxial lamination comprises a GaN channel layer and an AlGaN barrier layer which are stacked from bottom to top;
the first groove penetrates through the AlGaN barrier layer to expose part of the GaN channel layer, the opening width of the first groove is larger than the bottom width, and a preset included angle is formed between the inclined side wall of the first groove and the horizontal direction;
a second groove in the GaN channel layer and in communication with the first groove, the second groove penetrating the 2DEG region;
the metal source electrode and the metal drain electrode are positioned on the AlGaN barrier layer, the metal drain electrode is contacted with the inclined side wall of the first groove, the AlGaN barrier layer close to the metal source electrode has a first thickness, the AlGaN barrier layer close to the metal drain electrode has a second thickness, and the first thickness is larger than the second thickness;
a metal gate on the AlGaN barrier layer and between the metal source and the metal drain.
7. The GaN device of claim 6, wherein: the range of the preset included angle between the inclined side wall of the first groove and the horizontal direction comprises 45-60 degrees.
8. The GaN device of claim 6, wherein: the metal drain electrode completely covers the inclined side wall of the first groove or partially covers the inclined side wall of the first groove; the metal drain electrode is provided with a groove which penetrates through the metal drain electrode or fills the first groove and the second groove.
9. The GaN device of claim 6, wherein: and the bottom of the second groove also comprises an n-GaN ohmic contact auxiliary layer.
10. The GaN device of claim 6, wherein: the AlGaN barrier layer is Al which is overlapped from bottom to top in sequence0.1Ga0.9N/Al0.2Ga0.8N/Al0.3Ga0.7The N barrier lamination layer or the AlGaN barrier layer is Al laminated from bottom to top in sequence0.1Ga0.9N/Al0.2Ga0.8N/Al0.3Ga0.7N/AlN/Al0.3Ga0.7An N-barrier stack.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114373805A (en) * | 2022-01-13 | 2022-04-19 | 河北工业大学 | Schottky barrier diode structure with polarized p-type doped [0001] crystal orientation aluminum gallium nitrogen field ring terminal |
| CN115841952A (en) * | 2023-02-21 | 2023-03-24 | 湖北九峰山实验室 | Asymmetric SiC groove structure, manufacturing method thereof and electronic device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05190576A (en) * | 1992-01-16 | 1993-07-30 | Fujitsu Ltd | Semiconductor device |
| JP2006128646A (en) * | 2004-09-28 | 2006-05-18 | Sharp Corp | Electronic device and heterojunction fet |
| JP2011091200A (en) * | 2009-10-22 | 2011-05-06 | Sanken Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| CN103489897A (en) * | 2013-08-21 | 2014-01-01 | 中国电子科技集团公司第十三研究所 | Quasi-linear doped device structure based on group III nitride material |
| CN104471713A (en) * | 2012-07-13 | 2015-03-25 | 雷声公司 | Gallium nitride devices having low ohmic contact resistance |
| CN106252403A (en) * | 2016-08-29 | 2016-12-21 | 中国科学院半导体研究所 | A kind of HEMT epitaxial structure and preparation method |
| CN107431021A (en) * | 2015-03-31 | 2017-12-01 | 夏普株式会社 | Nitride-based semiconductor field-effect transistor |
-
2021
- 2021-03-12 CN CN202110269231.2A patent/CN113035935B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05190576A (en) * | 1992-01-16 | 1993-07-30 | Fujitsu Ltd | Semiconductor device |
| JP2006128646A (en) * | 2004-09-28 | 2006-05-18 | Sharp Corp | Electronic device and heterojunction fet |
| JP2011091200A (en) * | 2009-10-22 | 2011-05-06 | Sanken Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| CN104471713A (en) * | 2012-07-13 | 2015-03-25 | 雷声公司 | Gallium nitride devices having low ohmic contact resistance |
| CN103489897A (en) * | 2013-08-21 | 2014-01-01 | 中国电子科技集团公司第十三研究所 | Quasi-linear doped device structure based on group III nitride material |
| CN107431021A (en) * | 2015-03-31 | 2017-12-01 | 夏普株式会社 | Nitride-based semiconductor field-effect transistor |
| CN106252403A (en) * | 2016-08-29 | 2016-12-21 | 中国科学院半导体研究所 | A kind of HEMT epitaxial structure and preparation method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114373805A (en) * | 2022-01-13 | 2022-04-19 | 河北工业大学 | Schottky barrier diode structure with polarized p-type doped [0001] crystal orientation aluminum gallium nitrogen field ring terminal |
| CN115841952A (en) * | 2023-02-21 | 2023-03-24 | 湖北九峰山实验室 | Asymmetric SiC groove structure, manufacturing method thereof and electronic device |
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