CN111512435A - 包含不同半导体裸片的多重堆叠的半导体装置组合件 - Google Patents

包含不同半导体裸片的多重堆叠的半导体装置组合件 Download PDF

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CN111512435A
CN111512435A CN201880083503.6A CN201880083503A CN111512435A CN 111512435 A CN111512435 A CN 111512435A CN 201880083503 A CN201880083503 A CN 201880083503A CN 111512435 A CN111512435 A CN 111512435A
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stack
semiconductor
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device assembly
semiconductor device
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CN111512435B (zh
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B·J·瑟古德
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Micron Technology Inc
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Abstract

本发明提供一种半导体装置组合件。所述组合件包括：封装衬底；第一半导体裸片堆叠，所述半导体裸片具有第一组平面尺寸，所述第一堆叠安置在所述衬底上的第一位置上方；第二半导体裸片堆叠，所述半导体裸片具有与所述第一组不同的第二组平面尺寸，所述第二堆叠安置在所述衬底上的第二位置上方；及囊封剂，其至少部分囊封所述衬底、所述第一堆叠及所述第二堆叠。所述第一半导体裸片堆叠具有第一平面面积，所述第二半导体裸片堆叠具有第二平面面积，且所述第一平面面积及所述第二平面面积的总和可为所述封装衬底的面积的至少50％、67％、75％或甚至更多。

Description

包含不同半导体裸片的多重堆叠的半导体装置组合件
技术领域
本发明大体上涉及半导体装置，且更特定来说，涉及包含不同半导体裸片的多重堆叠的半导体装置组合件。
背景技术
封装式半导体裸片(包含存储器芯片、微处理器芯片及成像器芯片)通常包含安装在衬底上且围封在塑料保护罩中或由导热盖覆盖的一或多个半导体裸片。裸片可包含有源电路(例如，提供例如存储器单元、处理器电路及/或成像器装置的功能特征)及/或无源特征(例如，电容器、电阻器等)，以及电连接到所述电路的接合焊盘。接合焊盘可电连接到保护罩外部的端子以容许将裸片连接到较高级电路。
为提供额外功能性，可将额外半导体裸片添加到半导体装置组合件。一种包含额外半导体裸片的方法涉及将裸片堆叠在衬底上方。为促进裸片与衬底的电连接，可将裸片布置成叠瓦式堆叠，其中每一裸片从下方的裸片水平地偏移而留下可接合(例如，用接合线)到衬底上的对应接合指(bondfinger)的裸片的暴露接触焊盘。在这方面，图1说明半导体装置组合件100，其中由粘合层连接的裸片103的叠瓦式堆叠102堆叠在衬底101上且通过接合线106电连接到衬底101上的接合指105。堆叠102、衬底101及接合线106由例如模制材料105囊封。
半导体装置组合件通常以数种广泛采用的物理规格(physical format)中的一者提供以用于电子装置中。这些规格可指定例如组合件的总尺寸(即，宽度、长度及高度)、连接机构(例如，焊球阵列、焊盘、引脚(pin out)等)及组合件的其它特征。当半导体裸片或其堆叠具有利用给定规格所需的衬底上的绝大部分可用空间的平面面积时(如图2中)，封装中几乎不存在浪费空间。如参考图2可见，在组合件200中，具有覆盖衬底201的面积的大部分(例如，一半以上、三分之二以上、四分之三以上等)的平面面积的半导体裸片203的堆叠202几乎未留下浪费的空间。然而，随着半导体裸片由于工艺及技术进步而继续缩小，较小裸片可能无法良好地利用给定组合件规格可用的面积。
例如，图3说明半导体装置组合件，其中在组合件300中，具有覆盖少于衬底301的面积的大部分(例如，少于一半、少于三分之二、少于四分之三等)的平面面积的半导体裸片303的堆叠302留下大量浪费空间。为解决这个低效率，一种方法涉及使用较小半导体裸片的多重堆叠，如图4中展示，但这种方法在甚至通过较小半导体裸片的多重堆叠仍未有效率地使用装置组合件的所需规格时也可为低效的。如参考图4中说明的半导体装置组合件400可见，在组合件400中，甚至较小半导体裸片403的两个堆叠402及412可能仍覆盖少于给定组合件规格的衬底401的面积的大部分(例如，少于一半、少于三分之二、少于四分之三等)而留下大量浪费空间。
附图说明
图1说明包含半导体裸片堆叠的半导体装置组合件。
图2说明包含半导体裸片堆叠的半导体装置组合件。
图3说明包含半导体裸片堆叠的半导体装置组合件。
图4说明包含半导体裸片的多重堆叠的半导体装置组合件。
图5说明根据本技术的实施例的包含不同半导体裸片的多重堆叠的半导体装置组合件。
图6说明根据本技术的实施例的包含不同半导体裸片的多重堆叠的半导体装置组合件。
图7说明根据本技术的实施例的包含不同半导体裸片的多重堆叠的半导体装置组合件。
图8是说明根据本技术的一个实施例的制作半导体装置组合件的方法的流程图。
图9是展示根据本技术的实施例配置的包含半导体装置组合件的系统的示意图。
具体实施方式
在以下描述中，论述众多特定细节以提供对本技术的实施例的透彻且详尽的(enabling)描述。然而，所属领域技术人员将认识到，本发明可在没有一或多个特定细节的情况下实践。在其它情况下，未展示或未详细描述通常与半导体装置相关联的熟知结构或操作以避免使本技术的其它方面不清楚。一般来说，应了解，除本文中揭示的那些特定实施例之外的各种其它装置、系统及方法也可在本技术的范围内。
如上文论述，半导体装置组合件，例如半导体存储器封装，可以具有预定大小的数个不同物理规格提供。当半导体裸片未经定大小以有效率地利用特定物理规格中的可用空间时，封装中的未使用空间的低效率可增加组所述合件的相对成本(例如，与其中较大裸片的较短堆叠可提供相同存储器容量或较大裸片的等效堆叠可提供较大存储器容量的组合件相比)。因此，期望提供对半导体装置组合件中的可用空间的更有效率使用。
在这方面，本技术的若干实施例涉及一种半导体装置组合件，其包含：封装衬底；第一半导体裸片堆叠，所述半导体裸片具有第一组平面尺寸，所述第一堆叠安置在所述衬底上的第一位置上方；第二半导体裸片堆叠，所述半导体裸片具有与所述第一组不同的第二组平面尺寸，所述第二堆叠安置在所述衬底上的第二位置上方；及囊封剂，其至少部分囊封所述衬底、所述第一堆叠及所述第二堆叠。第一半导体裸片堆叠具有第一平面面积，第二半导体裸片堆叠具有第二平面面积，且第一平面面积及第二平面面积的总和可为封装衬底的面积的至少50％、67％、75％、90％或甚至更多。
下文描述半导体装置的若干实施例的特定细节。术语“半导体装置”大体上是指包含半导体材料的固态装置。半导体装置可包含例如半导体衬底、晶片或从晶片或衬底单粒化的裸片。贯穿本发明，大体上在半导体裸片的背景中描述半导体装置；然而，半导体装置不限于半导体裸片。
术语“半导体装置封装”可指具有并入到共同封装中的一或多个半导体装置的布置。半导体封装可包含部分或完全囊封至少一个半导体装置的外壳或壳体(casing)。半导体装置封装还可包含承载一或多个半导体装置且附接到或以其它方式并入到壳体中的中介衬底(interposer substrate)。术语“半导体装置组合件”可指一或多个半导体装置、半导体装置封装及/或衬底(例如，中介衬底、支撑衬底或其它适合衬底)的组合件。半导体装置组合件可制造为例如离散封装形式、条带或矩阵形式及/或晶片面板形式。如本文中使用，术语“垂直”、“横向”、“上”及“下”可指半导体装置或装置组合件中的特征依据图中所展示的定向的相对方向或位置。例如，“上”或“最上”可分别指定位成比另一特征或同一特征的部分更靠近或最靠近页面的顶部的特征。然而，这些术语应广泛解释为包含具有其它定向(例如倒转或倾斜定向)的半导体装置，其中顶部/底部、上方/下方、上面/下面、向上/向下及左/右可取决于定向而互换。
图5是根据本技术的实施例的包含不同半导体裸片的多重堆叠的半导体装置组合件的简化横截面视图。半导体装置组合件500包含衬底501、第一半导体裸片503的第一堆叠502及第二半导体裸片513的第二堆叠512，第二半导体裸片513具有与第一半导体裸片503不同的一组平面尺寸(例如，长度及/或宽度)。在这方面，第一堆叠502的第一半导体裸片503具有第一长度L1及第一宽度W1，且第二堆叠512的第二半导体裸片513具有第二长度L2及第二宽度W2，其中L1≠L2及/或W1≠W2。通过利用具有不同组平面尺寸的半导体裸片的堆叠，与运用单个半导体裸片堆叠或具有相同尺寸的半导体裸片的多重堆叠相比，可更有效率地利用具预定大小的装置组合件规格中的可用空间。在这方面，第一堆叠502具有第一面积A1，第二堆叠512具有第二面积A2，且第一面积及第二面积的总和可为衬底501的面积的至少50％、67％、75％、90％或甚至更多。
根据本技术的一个方面，第一堆叠502及第二堆叠512的半导体裸片503及513可为存储器裸片(例如，NAND快闪存储器、NOR快闪存储器、DRAM、PCM、FeRAM、MRAM等)，且装置组合件500可为封装式存储器装置。半导体裸片503及513可为相同种类的存储器(例如，两者均为NAND快闪存储器、两者均为NOR快闪存储器、两者均为DRAM等)，以在与具有较低利用效率的物理空间(例如，由于使用单个堆叠或相同尺寸的多重堆叠)的装置组合件相比时提供装置组合件500中的增加的存储器容量。
尽管在前述实例实施例中，已说明具有八个半导体裸片的两个堆叠的半导体装置组合件，但在其它实施例中，堆叠中的半导体裸片的数目及装置组合件中的堆叠的数目可变化。例如，图6是根据本技术的实施例的包含两个不同半导体裸片(例如，具有两组不同平面尺寸的半导体裸片)的三个堆叠的半导体装置组合件的简化平面视图。如参考图6可见，半导体装置组合件600包含衬底601及三个半导体裸片堆叠602到604，其具有与上文参考图5更详细论述特征类似的特征。堆叠602到604中的每一者安置在衬底601上的不同位置(例如，邻近、非重叠位置)中。第一堆叠602是具有第一组平面尺寸的八个第一类型的半导体裸片的堆叠，且第二堆叠603及第三堆叠604是具有与第一组不同的第二组平面尺寸的四个第二类型的半导体裸片的堆叠。通过利用具有不同组平面尺寸的半导体裸片的堆叠，与运用单个半导体裸片堆叠或具有相同尺寸的半导体裸片的多重堆叠相比，可更有效率地利用具预定大小的装置组合件规格中的可用空间。在这方面，第一堆叠602具有第一面积，第二堆叠603具有第二面积，第三堆叠604具有第三面积，且第一面积、第二面积及第三面积的总和可为衬底601的面积的至少50％、67％、75％、90％或甚至更多。
此外，尽管在前述实例实施例中，已说明具有两种不同类型的半导体裸片(例如，具有两组不同平面尺寸的半导体裸片)的半导体装置组合件，然在其它实施例中，半导体装置组合件可具有三种、四种或甚至更多不同类型的半导体裸片。在这方面，图7是根据本技术的实施例的包含三种不同半导体裸片(例如，具有三组不同平面尺寸的半导体裸片)的三个堆叠的半导体装置组合件的简化平面视图。如参考图7可见，半导体装置组合件700包含衬底701及三个半导体裸片堆叠702到704，其具有与上文参考图5及6更详细论述的特征类似的特征。堆叠702到704中的每一者安置在衬底701上的不同位置(例如，邻近、非重叠位置)中。第一堆叠702是具有第一组平面尺寸的八个第一类型的半导体裸片的堆叠，第二堆叠703是具有第二组平面尺寸的四个第二类型的半导体裸片的堆叠，且第三堆叠704是具有与第一组及第二组不同的第三组平面尺寸的四个第三类型的半导体裸片的堆叠。通过利用具有不同组平面尺寸的半导体裸片的堆叠，与运用单个半导体裸片堆叠或具有相同尺寸的半导体裸片的多重堆叠相比，可更有效率地利用具预定大小的装置组合件规格中的可用空间。在这方面，第一堆叠702具有第一面积，第二堆叠703具有第二面积，第三堆叠704具有第三面积，且第一面积、第二面积及第三面积的总和可为衬底701的面积的至少50％、67％、75％、90％或甚至更多。
尽管在前述实例中，已将半导体装置组合件说明且描述为包含半导体裸片的叠瓦式堆叠，然在本技术的其它实施例中，半导体装置组合件可包含利用不同拓扑(例如，垂直堆叠、部分叠瓦式堆叠等)及互连技术(例如，TSV、光学互连、感应互连等)的半导体裸片的多重堆叠。
根据本技术的一个方面，在半导体装置组合件中包含不同半导体裸片(例如，具有不同组平面尺寸的半导体裸片)的两个或更多个堆叠的优点是在组合件的布局中提供的额外灵活性，这可允许有效率地使用给定装置组合件规格的可用空间(例如，为存储器装置组合件提供较大位密度)。根据本技术的一个方面，在半导体装置组合件中提供不同半导体裸片的多重堆叠的另一优点是可实现封装高度的减小(例如，通过使用较少裸片的多重堆叠而非单个较高裸片堆叠)。又一优点可包含使用较厚半导体裸片(例如，其可比较薄裸片更容易制造)而维持与使用具有较大数目个较薄裸片的单个堆叠的半导体装置组合件类似的封装高度。
图8是说明制作半导体装置组合件的方法的流程图。所述方法包含：提供衬底(框810)；将具有第一组平面尺寸的第一多个半导体裸片堆叠在衬底上的第一堆叠中(框820)；及将具有与第一组不同的第二组平面尺寸的第二多个半导体裸片堆叠在衬底上的第二堆叠中(框830)。在这方面，第一多个半导体裸片可直接堆叠在衬底上的第一位置上方，且第二多个半导体裸片可直接堆叠在衬底的第二位置上方。所述方法可进一步包含将第一多个及第二多个半导体裸片线接合或以其它方式连接到衬底，且提供囊封剂以至少部分囊封衬底、第一堆叠及第二堆叠(框840)。
上文参考图5到8描述的半导体装置组合件中的任一者可并入到无数更大及/或更复杂系统中的任一者中，所述系统的代表性实例是图9中示意性地展示的系统900。系统900可包含半导体装置组合件902、电源904、驱动器906、处理器908及/或其它子系统或组件910。半导体装置组合件902可包含大体上与上文参考图5到8描述的半导体装置的特征类似的特征。所得系统900可执行各种各样功能中的任一者，例如存储器存储、数据处理及/或其它适合功能。因此，代表性系统900可包含但不限于手持装置(例如，移动电话、平板计算机、数字阅读器及数字音频播放器)、计算机、车辆、电器及其它产品。系统900的组件可容置在单个单元中或(例如，通过通信网络)分布在多个互连单元上。系统900的组件还可包含远程装置及各种各样计算机可读媒体中的任一者。
从前文，将明白，本文中已出于说明目的描述本发明的特定实施例，但可在不脱离本发明的范围的情况下进行各种修改。因此，本发明除所附权利要求书以外不受限制。

Claims (21)

1.一种半导体装置组合件，其包括：
封装衬底；
第一半导体裸片堆叠，所述半导体裸片具有第一组平面尺寸，所述第一堆叠安置在所述衬底上的第一位置上方；
第二半导体裸片堆叠，所述半导体裸片具有与所述第一组不同的第二组平面尺寸，所述第二堆叠安置在所述衬底上的第二位置上方；及
囊封剂，其至少部分囊封所述衬底、所述第一堆叠及所述第二堆叠。
2.根据权利要求1所述的半导体装置组合件，其中所述第一组平面尺寸包含第一长度及第一宽度，且其中所述第二组平面尺寸包含第二长度及第二宽度，且其中所述第一长度与所述第二长度及所述第二宽度不同。
3.根据权利要求2所述的半导体装置组合件，其中所述第一宽度与所述第二长度及所述第二宽度不同。
4.根据权利要求1所述的半导体装置组合件，其中所述第一半导体裸片堆叠具有第一平面面积，所述第二半导体裸片堆叠具有第二平面面积，且所述第一平面面积及所述第二平面面积的总和是所述封装衬底的面积的至少50％。
5.根据权利要求4所述的半导体装置组合件，其中所述总和是所述封装衬底的所述面积的至少67％。
6.根据权利要求4所述的半导体装置组合件，其中所述总和是所述封装衬底的所述面积的至少75％。
7.根据权利要求4所述的半导体装置组合件，其中所述总和是所述封装衬底的所述面积的至少90％。
8.根据权利要求1所述的半导体装置组合件，其中所述第一半导体裸片堆叠通过第一多个接合线连接到所述封装衬底，且所述第二半导体裸片堆叠通过第二多个接合线连接到所述封装衬底。
9.根据权利要求1所述的半导体装置组合件，其中所述第一半导体裸片堆叠包含贯穿衬底通孔。
10.根据权利要求9所述的半导体装置组合件，其中所述第二半导体裸片堆叠包含贯穿衬底通孔。
11.根据权利要求1所述的半导体装置组合件，其中所述第一半导体裸片堆叠包括第一多个存储器裸片，且其中所述第二半导体裸片堆叠包括第二多个存储器裸片。
12.根据权利要求11所述的半导体装置组合件，其中所述第一多个存储器裸片及所述第二多个存储器裸片包括单个存储器类型。
13.根据权利要求12所述的半导体装置组合件，其中所述单个存储器类型是NAND快闪存储器、NOR快闪存储器、DRAM、PCM、FeRAM或MRAM中的一者。
14.根据权利要求1所述的半导体装置组合件，其中所述封装衬底包含可操作地连接到所述第一半导体裸片堆叠及所述第二半导体裸片堆叠的多个外部连接器。
15.根据权利要求1所述的半导体装置组合件，其进一步包括：
第三半导体裸片堆叠，所述半导体裸片具有与所述第一组不同的第三组平面尺寸，所述第三堆叠安置在所述衬底上的第三位置上方。
16.一种制作存储器装置的方法，其包括：
提供衬底；
将具有第一组平面尺寸的第一多个半导体裸片堆叠在所述衬底上的第一堆叠中；
将具有与所述第一组不同的第二组平面尺寸的第二多个半导体裸片堆叠在所述衬底上的第二堆叠中；及
提供囊封剂以至少部分囊封所述衬底、所述第一堆叠及所述第二堆叠。
17.根据权利要求16所述的方法，其中所述第一组平面尺寸包含第一长度及第一宽度，且其中所述第二组平面尺寸包含第二长度及第二宽度，且其中所述第一长度与所述第二长度及所述第二宽度不同。
18.根据权利要求17所述的方法，其中所述第一宽度与所述第二长度及所述第二宽度不同。
19.根据权利要求16所述的方法，其中所述第一半导体裸片堆叠具有第一平面面积，所述第二半导体裸片堆叠具有第二平面面积，且所述第一平面面积及所述第二平面面积的总和是所述封装衬底的面积的至少50％。
20.根据权利要求16所述的方法，其中所述第一半导体裸片堆叠包括第一多个存储器裸片，且其中所述第二半导体裸片堆叠包括第二多个存储器裸片。
21.根据权利要求20所述的方法，其中所述第一多个存储器裸片及所述第二多个存储器裸片包括单个存储器类型。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10797020B2 (en) * 2017-12-29 2020-10-06 Micron Technology, Inc. Semiconductor device assemblies including multiple stacks of different semiconductor dies
US11989141B2 (en) * 2019-12-27 2024-05-21 Micron Technology, Inc. Neuromorphic memory device and method
US11830849B2 (en) 2021-11-04 2023-11-28 Western Digital Technologies, Inc. Semiconductor device with unbalanced die stackup

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101228628A (zh) * 2005-05-26 2008-07-23 桑迪士克股份有限公司 具有堆叠的集成电路的集成电路封装及其方法
US20150279828A1 (en) * 2014-03-31 2015-10-01 Micron Technology, Inc. Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods
CN106463469A (zh) * 2014-04-01 2017-02-22 美光科技公司 具有经分割逻辑的堆叠式半导体裸片组合件以及相关联系统及方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6680219B2 (en) 2001-08-17 2004-01-20 Qualcomm Incorporated Method and apparatus for die stacking
US7253511B2 (en) 2004-07-13 2007-08-07 Chippac, Inc. Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
US7994622B2 (en) * 2007-04-16 2011-08-09 Tessera, Inc. Microelectronic packages having cavities for receiving microelectric elements
US7868431B2 (en) 2007-11-23 2011-01-11 Alpha And Omega Semiconductor Incorporated Compact power semiconductor package and method with stacked inductor and integrated circuit die
US8062932B2 (en) 2008-12-01 2011-11-22 Alpha & Omega Semiconductor, Inc. Compact semiconductor package with integrated bypass capacitor and method
US8456856B2 (en) * 2009-03-30 2013-06-04 Megica Corporation Integrated circuit chip using top post-passivation technology and bottom structure technology
JP5289484B2 (ja) 2011-03-04 2013-09-11 株式会社東芝 積層型半導体装置の製造方法
US8823165B2 (en) * 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
KR101950976B1 (ko) * 2012-10-25 2019-02-25 에스케이하이닉스 주식회사 반도체 패키지
KR20150005113A (ko) * 2013-07-04 2015-01-14 에스케이하이닉스 주식회사 광학 신호 경로를 포함하는 반도체 패키지
US9263370B2 (en) 2013-09-27 2016-02-16 Qualcomm Mems Technologies, Inc. Semiconductor device with via bar
US9735082B2 (en) * 2013-12-04 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC packaging with hot spot thermal management features
KR102247916B1 (ko) * 2014-01-16 2021-05-04 삼성전자주식회사 계단식 적층 구조를 갖는 반도체 패키지
KR20160014475A (ko) * 2014-07-29 2016-02-11 삼성전자주식회사 스택 패키지
ITUA20164724A1 (it) 2016-06-28 2017-12-28 St Microelectronics Srl Dispositivo elettronico a semiconduttori con migliorate caratteristiche di testabilita' e relativo metodo di incapsulamento
KR102576764B1 (ko) * 2016-10-28 2023-09-12 에스케이하이닉스 주식회사 비대칭 칩 스택들을 가지는 반도체 패키지
US10163750B2 (en) * 2016-12-05 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure for heat dissipation
KR20180094667A (ko) * 2017-02-16 2018-08-24 에스케이하이닉스 주식회사 제한된 언더필 필릿을 가지는 적층 패키지 및 제조 방법
US10797020B2 (en) 2017-12-29 2020-10-06 Micron Technology, Inc. Semiconductor device assemblies including multiple stacks of different semiconductor dies

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101228628A (zh) * 2005-05-26 2008-07-23 桑迪士克股份有限公司 具有堆叠的集成电路的集成电路封装及其方法
US20150279828A1 (en) * 2014-03-31 2015-10-01 Micron Technology, Inc. Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods
CN106463469A (zh) * 2014-04-01 2017-02-22 美光科技公司 具有经分割逻辑的堆叠式半导体裸片组合件以及相关联系统及方法

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