TW201941401A - 包含不同半導體晶粒之多重堆疊的半導體裝置總成 - Google Patents

包含不同半導體晶粒之多重堆疊的半導體裝置總成 Download PDF

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TW201941401A
TW201941401A TW107141583A TW107141583A TW201941401A TW 201941401 A TW201941401 A TW 201941401A TW 107141583 A TW107141583 A TW 107141583A TW 107141583 A TW107141583 A TW 107141583A TW 201941401 A TW201941401 A TW 201941401A
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布萊 Ｊ 蘇葛
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美商美光科技公司
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Abstract

本發明提供一種半導體裝置總成。該總成包括：一封裝基板；一第一半導體晶粒堆疊，該等半導體晶粒具有一第一組平面尺寸，該第一堆疊安置於該基板上之一第一位置上方；一第二半導體晶粒堆疊，該等半導體晶粒具有不同於該第一組之一第二組平面尺寸，該第二堆疊安置於該基板上之一第二位置上方；及一囊封劑，其至少部分囊封該基板、該第一堆疊及該第二堆疊。該第一半導體晶粒堆疊具有一第一平面面積，該第二半導體晶粒堆疊具有一第二平面面積，且該第一平面面積及該第二平面面積之一總和可為該封裝基板之一面積之至少50%、67%、75%或甚至更多。

Description

包含不同半導體晶粒之多重堆疊的半導體裝置總成
本發明大體上係關於半導體裝置，且更特定言之係關於包含不同半導體晶粒之多重堆疊的半導體裝置總成。
封裝半導體晶粒(包含記憶體晶片、微處理器晶片及成像器晶片)通常包含安裝於一基板上且圍封於一塑膠保護罩中或由一導熱蓋覆蓋的一或多個半導體晶粒。晶粒可包含主動電路(例如，其等提供諸如記憶體胞、處理器電路及/或成像器裝置之功能構件)及/或被動構件(例如，電容器、電阻器等)，以及電連接至該等電路之接合墊。接合墊可電連接至保護罩外部之端子以容許將晶粒連接至較高層級電路。
為提供額外功能性，可將額外半導體晶粒添加至一半導體裝置總成。包含額外半導體晶粒之一個方法涉及將晶粒堆疊於基板上方。為促進晶粒與基板之電連接，可將晶粒配置成一疊瓦式堆疊，其中各晶粒自下方之一晶粒水平偏移而留下可接合(例如，用一線接合)至基板上之一對應接合指(bondfinger)的晶粒之暴露接觸墊。在此方面，圖1繪示一半導體裝置總成100，其中由黏著層連接之晶粒103之一疊瓦式堆疊102堆疊於一基板101上且藉由線接合106電連接至基板101上之接合指105。堆疊102、基板101及線接合106由例如一模具材料105囊封。
半導體裝置總成通常以若干廣泛採用的實體規格(physical format)之一者提供以用於電子裝置中。此等規格可指定例如總成之總尺寸(即，寬度、長度及高度)、連接機制(例如，焊球陣列、墊、引腳(pin out)等)及總成之其他特徵。當一半導體晶粒或其之一堆疊具有利用一給定規格所需之一基板上之絕大部分可用空間的一平面面積時(如圖2中)，封裝中幾乎不存在浪費空間。如參考圖2可見，在總成200中，具有覆蓋基板201之面積之大部分(例如，一半以上、三分之二以上、四分之三以上等)之一平面面積的半導體晶粒203之一堆疊202幾乎未留下浪費空間。然而，隨著半導體晶粒歸因於製程及技術進步而繼續縮小，較小晶粒可能無法良好利用一給定總成規格可用之面積。
例如，圖3繪示一半導體裝置總成，其中在總成300中，具有覆蓋少於基板301之面積之大部分(例如，少於一半、少於三分之二、少於四分之三等)之一平面面積的半導體晶粒303之一堆疊302留下大量浪費空間。為解決此低效率，一個方法涉及使用較小半導體晶粒之多重堆疊，如圖4中展示，但此方法在甚至藉由較小半導體晶粒之多重堆疊仍未有效率地使用一裝置總成之所需規格時亦可為低效的。如參考圖4中繪示之半導體裝置總成400可見，在總成400中，甚至較小半導體晶粒403之兩個堆疊402及412可能仍覆蓋少於一給定總成規格之一基板401之面積的大部分(例如，少於一半、少於三分之二、少於四分之三等)而留下大量浪費空間。
根據本發明技術之若干實施例，提供一種半導體裝置總成。該半導體裝置總成包括：一封裝基板；一第一半導體晶粒堆疊，該等半導體晶粒具有一第一組平面尺寸，該第一堆疊安置於該基板上之一第一位置上方；一第二半導體晶粒堆疊，該等半導體晶粒具有不同於該第一組之一第二組平面尺寸，該第二堆疊安置於該基板上之一第二位置上方；及一囊封劑，其至少部分囊封該基板、該第一堆疊及該第二堆疊。
根據本發明技術之若干實施例，提供一種製作一記憶體裝置之方法。該方法包括：提供一基板；將具有一第一組平面尺寸之第一複數個半導體晶粒堆疊於該基板上之一第一堆疊中；將具有不同於該第一組之一第二組平面尺寸的第二複數個半導體晶粒堆疊於該基板上之一第二堆疊中；及提供一囊封劑以至少部分囊封該基板、該第一堆疊及該第二堆疊。
在以下描述中，論述許多具體細節以提供對本發明技術之實施例之一透徹的且詳盡的(enabling)描述。然而，熟習相關技術者將認識到，本發明可在無該等具體細節之一或多者之情況下實踐。在其他例項中，未展示或未詳細描述通常與半導體裝置相關聯之熟知結構或操作以避免使本發明技術之其他態樣不清楚。一般而言，應瞭解，除本文中揭示之該等特定實施例之外，各種其他裝置、系統及方法亦可在本發明技術之範疇內。
如上文論述，半導體裝置總成(諸如半導體記憶體封裝)可以具有預定大小之若干不同實體規格提供。當一半導體晶粒未經設計大小以有效率地利用一特定實體規格中之可用空間時，封裝中之未使用空間的低效率可增加總成之相對成本(例如，與一其中較大晶粒之一較短堆疊可提供相同記憶體容量或較大晶粒之一等量堆疊可提供較大記憶體容量的總成相比)。因此，期望提供對半導體裝置總成中之可用空間的更有效率使用。
在此方面，本發明技術之若干實施例係關於半導體裝置總成，其包含：一封裝基板；一第一半導體晶粒堆疊，該等半導體晶粒具有一第一組平面尺寸，該第一堆疊安置於該基板上之一第一位置上方；一第二半導體晶粒堆疊，該等半導體晶粒具有不同於該第一組之一第二組平面尺寸，該第二堆疊安置於該基板上之一第二位置上方；及一囊封劑，其至少部分囊封該基板、該第一堆疊及該第二堆疊。第一半導體晶粒堆疊具有一第一平面面積，第二半導體晶粒堆疊具有一第二平面面積，且第一平面面積及第二平面面積之一總和可為封裝基板之一面積之至少50%、67%、75%、90%或甚至更多。
下文描述半導體裝置之若干實施例之具體細節。術語「半導體裝置」大體上指代包含一半導體材料之一固態裝置。一半導體裝置可包含例如一半導體基板、晶圓或自一晶圓或基板單粒化之晶粒。在本發明各處，大體上在半導體晶粒之內容背景中描述半導體裝置；然而，半導體裝置不限於半導體晶粒。
術語「半導體裝置封裝」可指代具有併入至一共同封裝中之一或多個半導體裝置的一配置。一半導體封裝可包含部分或完全囊封至少一個半導體裝置之一外殼或殼體(casing)。一半導體裝置封裝亦可包含承載一或多個半導體裝置且附接至或以其他方式併入至殼體中之一中介基板(interposer substrate)。術語「半導體裝置總成」可指代一或多個半導體裝置、半導體裝置封裝及/或基板(例如，中介基板、支撐基板或其他適合基板)之一總成。半導體裝置總成可製造為例如離散封裝形式、條帶或矩陣形式及/或晶圓面板形式。如本文中使用，術語「垂直」、「橫向」、「上」及「下」可指代半導體裝置或裝置總成中之構件依據圖中所示之定向的相對方向或位置。例如，「上」或「最上」可分別指代定位成比另一構件或相同構件之部分更靠近或最靠近一頁面之頂部的一構件。然而，此等術語應廣泛解釋為包含具有其他定向(諸如倒轉或傾斜定向)之半導體裝置，其中頂部/底部、上方/下方、上面/下面、向上/向下及左/右可取決於定向而互換。
圖5係根據本發明技術之一實施例之包含不同半導體晶粒之多重堆疊的一半導體裝置總成之一簡化橫截面視圖。半導體裝置總成500包含一基板501、第一半導體晶粒503之一第一堆疊502及第二半導體晶粒513之一第二堆疊512，第二半導體晶粒513具有不同於第一半導體晶粒503之一組平面尺寸(例如，長度及/或寬度)。在此方面，第一堆疊502之第一半導體晶粒503具有一第一長度L1 及一第一寬度W1 ，且第二堆疊512之第二半導體晶粒513具有一第二長度L2 及一第二寬度W2 ，其中L1 ≠ L2 及/或W1 ≠ W2 。藉由利用具有不同組平面尺寸之半導體晶粒之堆疊，與運用一單一半導體晶粒堆疊或具有相同尺寸之半導體晶粒之多重堆疊相比，可更有效率地利用具一預定大小之一裝置總成規格中的可用空間。在此方面，第一堆疊502具有一第一面積A1 ，第二堆疊512具有一第二面積A2 ，且第一面積及第二面積之一總和可為基板501之一面積之至少50%、67%、75%、90%或甚至更多。
根據本發明技術之一個態樣，第一堆疊502及第二堆疊512之半導體晶粒503及513可為記憶體晶粒(例如，NAND快閃記憶體、NOR快閃記憶體、DRAM、PCM、FeRAM、MRAM等)，且裝置總成500可為一封裝記憶體裝置。半導體晶粒503及513可為相同種類之記憶體(例如，兩者皆為NAND快閃記憶體、兩者皆為NOR快閃記憶體、兩者皆為DRAM等)，以在與具有較低利用效率的實體空間(例如，歸因於使用一單一堆疊或相同尺寸之多重堆疊)之一裝置總成相比時提供裝置總成500中之增加的記憶體容量。
儘管在前述實例實施例中，已繪示具有八個半導體晶粒之兩個堆疊的一半導體裝置總成，然在其他實施例中，一堆疊中之半導體晶粒之數目及一裝置總成中之堆疊之數目可變化。例如，圖6係根據本發明技術之一實施例之包含兩個不同半導體晶粒(例如，具有兩組不同平面尺寸之半導體晶粒)之三個堆疊的一半導體裝置總成之一簡化平面圖。如參考圖6可見，半導體裝置總成600包含一基板601及三個半導體晶粒堆疊602至604，其具有類似於上文關於圖5更詳細論述特徵的特徵。堆疊602至604之各者安置於基板601上之一不同位置(例如，鄰近、非重疊位置)中。第一堆疊602係具有一第一組平面尺寸之八個第一類型之半導體晶粒的一堆疊，且第二堆疊603及第三堆疊604係具有不同於第一組之一第二組平面尺寸之四個第二類型之半導體晶粒的堆疊。藉由利用具有不同組平面尺寸之半導體晶粒之堆疊，與運用一單一半導體晶粒堆疊或具有相同尺寸之半導體晶粒之多重堆疊相比，可更有效率地利用具一預定大小之一裝置總成規格中的可用空間。在此方面，第一堆疊602具有一第一面積，第二堆疊603具有一第二面積，第三堆疊604具有一第三面積，且第一面積、第二面積及第三面積之一總和可為基板601之一面積之至少50%、67%、75%、90%或甚至更多。
此外，儘管在前述實例實施例中，已繪示具有兩種不同類型之半導體晶粒(例如，具有兩組不同平面尺寸之半導體晶粒)之半導體裝置總成，然在其他實施例中，一半導體裝置總成可具有三種、四種或甚至更多不同類型之半導體晶粒。在此方面，圖7係根據本發明技術之一實施例之包含三種不同半導體晶粒(例如，具有三組不同平面尺寸之半導體晶粒)之三個堆疊的一半導體裝置總成之一簡化平面圖。如參考圖7可見，半導體裝置總成700包含一基板701及三個半導體晶粒堆疊702至704，其具有類似於上文關於圖5及圖6更詳細論述之特徵的特徵。堆疊702至704之各者安置於基板701上之一不同位置(例如，鄰近、非重疊位置)中。第一堆疊702係具有一第一組平面尺寸之八個第一類型之半導體晶粒的一堆疊，第二堆疊703係具有一第二組平面尺寸之四個第二類型之半導體晶粒的一堆疊，且第三堆疊704係具有不同於第一組及第二組之一第三組平面尺寸之四個第三類型之半導體晶粒的一堆疊。藉由利用具有不同組平面尺寸之半導體晶粒之堆疊，與運用一單一半導體晶粒堆疊或具有相同尺寸之半導體晶粒之多重堆疊相比，可更有效率地利用具一預定大小之一裝置總成規格中的可用空間。在此方面，第一堆疊702具有一第一面積，第二堆疊703具有一第二面積，第三堆疊704具有一第三面積，且第一面積、第二面積及第三面積之一總和可為基板701之一面積之至少50%、67%、75%、90%或甚至更多。
儘管在前述實例中，已將半導體裝置總成繪示且描述為包含半導體晶粒之疊瓦式堆疊，然在本發明技術之其他實施例中，半導體裝置總成可包含利用不同拓撲(例如，垂直堆疊、部分疊瓦式堆疊等)及互連技術(例如，TSV、光學互連、感應互連等)之半導體晶粒之多重堆疊。
根據本發明技術之一個態樣，在一半導體裝置總成中包含不同半導體晶粒(例如，具有不同組平面尺寸之半導體晶粒)之兩個或更多個堆疊之一優點係在總成之佈局中提供的額外靈活性，此可允許有效率地使用一給定裝置總成規格之可用空間(例如，為一記憶體裝置總成提供一較大位元密度)。根據本發明技術之一個態樣，在一半導體裝置總成中提供不同半導體晶粒之多重堆疊之另一優點係可達成封裝高度之減小(例如，藉由使用較少個晶粒之多重堆疊而非一單一較高晶粒堆疊)。另一優點可包含使用較厚半導體晶粒(例如，其等可比較薄晶粒更容易製造)而維持與使用具有較大數目個較薄晶粒之一單一堆疊的一半導體裝置總成類似之一封裝高度。
圖8係繪示製作一半導體裝置總成之一方法之一流程圖。方法包含：提供一基板(框810)；將具有一第一組平面尺寸之第一複數個半導體晶粒堆疊於基板上之一第一堆疊中(框820)；及將具有不同於第一組之一第二組平面尺寸的第二複數個半導體晶粒堆疊於基板上之一第二堆疊中(框830)。在此方面，第一複數個半導體晶粒可直接堆疊於基板上之一第一位置上方，且第二複數個半導體晶粒可直接堆疊於基板之一第二位置上方。方法可進一步包含將第一複數個及第二複數個半導體晶粒線接合或以其他方式連接至該基板，且提供一囊封劑以至少部分囊封基板、第一堆疊及第二堆疊(框840)。
上文關於圖5至圖8描述之半導體裝置總成之任一者可併入至無數較大及/或更複雜系統之任一者中，該等系統之一代表性實例係圖9中示意性地展示之系統900。系統900可包含一半導體裝置總成902、一電源904、一驅動器906、一處理器908及/或其他子系統或組件910。半導體裝置總成902可包含大體上類似於上文關於圖5至圖8描述之半導體裝置之特徵的特徵。所得系統900可執行多種功能之任一者，諸如記憶體儲存、資料處理及/或其他適合功能。因此，代表性系統900可包含但不限於手持式裝置(例如，行動電話、平板電腦、數位閱讀器及數位音訊播放器)、電腦、車輛、電器及其他產品。系統900之組件可容置於一單一單元中或(例如，透過一通信網路)分佈於多個互連單元上。系統900之組件亦可包含遠端裝置及多種電腦可讀媒體之任一者。
從前文，將瞭解本文中已出於繪示之目的描述本發明之特定實施例，但可在不脫離本發明之範疇之情況下進行各種修改。因此，本發明除如藉由隨附發明申請專利範圍限制外不受限制。
100‧‧‧半導體裝置總成
101‧‧‧基板
102‧‧‧堆疊
103‧‧‧晶粒
105‧‧‧接合指/模具材料
106‧‧‧線接合
200‧‧‧總成
201‧‧‧基板
202‧‧‧堆疊
203‧‧‧半導體晶粒
300‧‧‧總成
301‧‧‧基板
302‧‧‧堆疊
303‧‧‧半導體晶粒
400‧‧‧半導體裝置總成
401‧‧‧基板
402‧‧‧堆疊
403‧‧‧半導體晶粒
412‧‧‧堆疊
500‧‧‧半導體裝置總成
501‧‧‧基板
502‧‧‧第一堆疊
503‧‧‧第一半導體晶粒
512‧‧‧第二堆疊
513‧‧‧第二半導體晶粒
600‧‧‧半導體裝置總成
601‧‧‧基板
602‧‧‧半導體晶粒堆疊/第一堆疊
603‧‧‧半導體晶粒堆疊/第二堆疊
604‧‧‧半導體晶粒堆疊/第三堆疊
700‧‧‧半導體裝置總成
701‧‧‧基板
702‧‧‧半導體晶粒堆疊/第一堆疊
703‧‧‧半導體晶粒堆疊/第二堆疊
704‧‧‧半導體晶粒堆疊/第三堆疊
810‧‧‧框
820‧‧‧框
830‧‧‧框
840‧‧‧框
900‧‧‧系統
902‧‧‧半導體裝置總成
904‧‧‧電源
906‧‧‧驅動器
908‧‧‧處理器
910‧‧‧其他子系統或組件
A1‧‧‧第一面積
A2‧‧‧第二面積
L1‧‧‧第一長度
L2‧‧‧第二長度
W1‧‧‧第一寬度
W2‧‧‧第二寬度
圖1繪示包含一半導體晶粒堆疊之一半導體裝置總成。
圖2繪示包含一半導體晶粒堆疊之一半導體裝置總成。
圖3繪示包含一半導體晶粒堆疊之一半導體裝置總成。
圖4繪示包含半導體晶粒之多重堆疊之一半導體裝置總成。
圖5繪示根據本發明技術之一實施例之包含不同半導體晶粒之多重堆疊的一半導體裝置總成。
圖6繪示根據本發明技術之一實施例之包含不同半導體晶粒之多重堆疊的一半導體裝置總成。
圖7繪示根據本發明技術之一實施例之包含不同半導體晶粒之多重堆疊的一半導體裝置總成。
圖8係繪示根據本發明技術之一項實施例之製作一半導體裝置總成的一方法之一流程圖。
圖9係展示根據本發明技術之一實施例組態之包含一半導體裝置總成的一系統之一示意圖。

Claims (21)

  1. 一種半導體裝置總成，其包括： 一封裝基板； 一第一半導體晶粒堆疊，該等半導體晶粒具有一第一組平面尺寸，該第一堆疊安置於該基板上之一第一位置上方； 一第二半導體晶粒堆疊，該等半導體晶粒具有不同於該第一組之一第二組平面尺寸，該第二堆疊安置於該基板上之一第二位置上方；及 一囊封劑，其至少部分囊封該基板、該第一堆疊及該第二堆疊。
  2. 如請求項1之半導體裝置總成，其中該第一組平面尺寸包含一第一長度及一第一寬度，且其中該第二組平面尺寸包含一第二長度及一第二寬度，且其中該第一長度不同於該第二長度及該第二寬度。
  3. 如請求項2之半導體裝置總成，其中該第一寬度不同於該第二長度及該第二寬度。
  4. 如請求項1之半導體裝置總成，其中該第一半導體晶粒堆疊具有一第一平面面積，該第二半導體晶粒堆疊具有一第二平面面積，且該第一平面面積及該第二平面面積之一總和係該封裝基板之一面積之至少50%。
  5. 如請求項4之半導體裝置總成，其中該總和係該封裝基板之該面積之至少67%。
  6. 如請求項4之半導體裝置總成，其中該總和係該封裝基板之該面積之至少75%。
  7. 如請求項4之半導體裝置總成，其中該總和係該封裝基板之該面積之至少90%。
  8. 如請求項1之半導體裝置總成，其中該第一半導體晶粒堆疊藉由第一複數個線接合連接至該封裝基板，且該第二半導體晶粒堆疊藉由第二複數個線接合連接至該封裝基板。
  9. 如請求項1之半導體裝置總成，其中該第一半導體晶粒堆疊包含貫穿基板通孔。
  10. 如請求項9之半導體裝置總成，其中該第二半導體晶粒堆疊包含貫穿基板通孔。
  11. 如請求項1之半導體裝置總成，其中該第一半導體晶粒堆疊包括第一複數個記憶體晶粒，且其中該第二半導體晶粒堆疊包括第二複數個記憶體晶粒。
  12. 如請求項11之半導體裝置總成，其中該第一複數個記憶體晶粒及該第二複數個記憶體晶粒包括一單一記憶體類型。
  13. 如請求項12之半導體裝置總成，其中該單一記憶體類型係NAND快閃記憶體、NOR快閃記憶體、DRAM、PCM、FeRAM或MRAM之一者。
  14. 如請求項1之半導體裝置總成，其中該封裝基板包含可操作地連接至該第一半導體晶粒堆疊及該第二半導體晶粒堆疊之複數個外部連接器。
  15. 如請求項1之半導體裝置總成，其進一步包括： 一第三半導體晶粒堆疊，該等半導體晶粒具有不同於該第一組之一第三組平面尺寸，該第三堆疊安置於該基板上之一第三位置上方。
  16. 一種製作一記憶體裝置之方法，其包括： 提供一基板； 將具有一第一組平面尺寸之第一複數個半導體晶粒堆疊於該基板上之一第一堆疊中； 將具有不同於該第一組之一第二組平面尺寸的第二複數個半導體晶粒堆疊於該基板上之一第二堆疊中；及 提供一囊封劑以至少部分囊封該基板、該第一堆疊及該第二堆疊。
  17. 如請求項16之方法，其中該第一組平面尺寸包含一第一長度及一第一寬度，且其中該第二組平面尺寸包含一第二長度及一第二寬度，且其中該第一長度不同於該第二長度及該第二寬度。
  18. 如請求項17之方法，其中該第一寬度不同於該第二長度及該第二寬度。
  19. 如請求項16之方法，其中該第一半導體晶粒堆疊具有一第一平面面積，該第二半導體晶粒堆疊具有一第二平面面積，且該第一平面面積及該第二平面面積之一總和係該封裝基板之一面積之至少50%。
  20. 如請求項16之方法，其中該第一半導體晶粒堆疊包括第一複數個記憶體晶粒，且其中該第二半導體晶粒堆疊包括第二複數個記憶體晶粒。
  21. 如請求項20之方法，其中該第一複數個記憶體晶粒及該第二複數個記憶體晶粒包括一單一記憶體類型。
TW107141583A 2017-12-29 2018-11-22 包含不同半導體晶粒之多重堆疊的半導體裝置總成及其製作方法 TWI695486B (zh)

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