CN111508846A - Process method of shielded gate trench type MOSFET - Google Patents
Process method of shielded gate trench type MOSFET Download PDFInfo
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- CN111508846A CN111508846A CN202010447881.7A CN202010447881A CN111508846A CN 111508846 A CN111508846 A CN 111508846A CN 202010447881 A CN202010447881 A CN 202010447881A CN 111508846 A CN111508846 A CN 111508846A
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- 238000000034 method Methods 0.000 title claims abstract description 63
- 230000008569 process Effects 0.000 title claims abstract description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 44
- 229920005591 polysilicon Polymers 0.000 claims abstract description 32
- 238000000151 deposition Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000000407 epitaxy Methods 0.000 claims description 3
- 230000007704 transition Effects 0.000 claims description 3
- 238000003672 processing method Methods 0.000 claims 7
- 230000001965 increasing effect Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 63
- 230000006872 improvement Effects 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 239000011148 porous material Substances 0.000 description 3
- 238000005429 filling process Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
Abstract
The invention discloses a process method of a shielded gate trench type MOSFET, which comprises the following steps: firstly, depositing a silicon oxide layer on a semiconductor substrate, and then sequentially depositing a silicon nitride layer and a silicon oxide layer to form an ONO layer; etching the ONO layer; secondly, etching the semiconductor substrate downwards by taking the ONO layer as a hard mask to form a groove; thirdly, performing back etching on the ONO layer; step four, chamfering and etching the bottom of the formed groove; depositing a dielectric layer in the groove; depositing and filling a polycrystalline silicon layer in the groove; and seventhly, etching back the deposited polycrystalline silicon layer. The process method of the invention adds the back etching process of the ONO layer of the hard mask layer before the chamfer etching process of the groove, improves the top appearance of the groove and increases the process tolerance of the polysilicon filling; the etching angle of the groove is allowed to reach more than 88 degrees, and after the etching angle of the groove is increased, the size of each device unit can be reduced, and the performance of the device is enhanced.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a shielded gate trench type MOSFET (metal-oxide-semiconductor field effect transistor) process method.
Background
The groove type double-layer grid MOS is used as a power device and has the characteristics of high breakdown voltage, low on-resistance and high switching speed. The structure of the shielded gate trench type MOSFET is divided into an upper part and a lower part, the lower part of the trench is filled with polysilicon as a source electrode, the upper part of the trench is filled with polysilicon as a gate electrode, and the gate electrode, the source electrode and the trench are isolated by oxide layers. The method is characterized in that polycrystalline silicon filled in the source electrode groove only occupies about half of the inner space of the groove, so that a source electrode contact hole can be contacted with the polycrystalline silicon filled at the lower part of the groove only by being made deeper. The method comprises the steps of firstly depositing an oxide layer on a silicon substrate to serve as a hard mask, then defining a graph on the hard mask by photoresist, removing the photoresist, etching the substrate by the graph defined by the hard mask to form a groove, chamfering the groove, then depositing an oxide layer, filling the groove with a first layer of polycrystalline silicon, carrying out back etching to form a source electrode, depositing a gate oxide layer, depositing polycrystalline silicon and etching to form a grid electrode, and finally carrying out subsequent processes such as body area injection and propulsion, source electrode injection and propulsion, interlayer dielectric deposition and the like.
The above process has the following limitations:
1. in order to ensure the best pore filling performance of the first layer of polysilicon, the angle of the groove needs to be kept at 87.5 degrees, the closing of the top of the groove is greatly influenced when a dielectric layer (an oxide layer) is deposited, and the process tolerance of the pore filling performance of the first layer of polysilicon is small.
2. The angle of 87.5 degrees of the groove limits the further reduction of the occupied area of the whole device, affects the integration level and prevents the further improvement of the device performance.
3. When the trench angle needs to be larger than 88 °, as shown by the dashed line frame in fig. 4, a gap may exist in the first layer of polysilicon deposition (i.e., a void is formed in the polysilicon filling), which affects the etching and the subsequent IPO (Inter-Poly Oxide, Inter-polysilicon Oxide film) morphology.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a shielded gate trench type MOSFET process method which is more suitable for perfectly filling a trench with a trench angle of more than or equal to 88 degrees.
In order to solve the above problems, the process method of the invention for the shielded gate trench MOSFET comprises the following process steps:
firstly, depositing a silicon oxide layer on a semiconductor substrate, and then sequentially depositing a silicon nitride layer and a silicon oxide layer to form an ONO layer; the ONO layer is etched to expose a trench etch region.
And step two, taking the ONO layer as a hard mask, and etching the semiconductor substrate downwards to form a groove.
And step three, performing back etching on the ONO layer.
And step four, performing chamfer etching on the bottom of the formed groove.
And step five, depositing a dielectric layer in the groove.
And sixthly, depositing and filling a polycrystalline silicon layer in the groove.
And seventhly, etching back the deposited polycrystalline silicon layer.
In a further improvement, in the first step, the semiconductor substrate includes a silicon substrate or is a silicon epitaxy; the thickness of the oxide layer at the topmost layer of the ONO layer is larger than that of the silicon nitride layer and the silicon oxide layer below the ONO layer.
In a further improvement, in the second step, the groove angle can reach more than or equal to 88 degrees.
The further improvement is that in the third step, the ONO layer is etched back by adopting a wet process, so that the ONO layer which is positioned at the two sides of the top of the groove and used as a hard mask is continuously and transversely etched, and the opening range between the ONO masks at the top of the groove area is enlarged.
The further improvement is that in the fourth step, the transition between the bottom of the groove and the side wall of the groove is smoother due to the chamfer angle at the bottom of the groove, so that the adhesiveness of the dielectric film layer and the attaching appearance of the bottom of the groove are facilitated.
In a further improvement, in the fifth step, the dielectric layer is formed by a thermal oxidation method and a CVD process.
In the sixth step, the trench is filled with polysilicon, and etching back is performed after the trench is filled with polysilicon, so as to form a lower polysilicon electrode in the shield gate trench.
In a further improvement, the method also comprises the following steps of depositing an inter-polysilicon oxide film on the upper part of the polysilicon in the trench after the polysilicon etch back is completed, depositing and filling a second layer of polysilicon and etching back to form a trench upper electrode.
According to the shielded gate trench type MOSFET process method, the back etching process of the ONO layer of the hard mask layer is added before the trench chamfer etching process, the top appearance of the trench is improved, and the process tolerance of polysilicon filling is increased; the etching angle of the groove is allowed to reach more than 88 degrees, and the dielectric layer has good polycrystalline silicon hole filling characteristics when adopting HDPCVD or SACVD; after the etching angle of the groove is increased, the size of each device unit can be reduced, and the performance of the device is enhanced.
Drawings
FIGS. 1-3 are schematic diagrams of the key steps of filling the polysilicon in the lower portion of the trench in the prior art.
Fig. 4 is a micrograph of voids or gaps that appear after the prior art process has completed the polysilicon fill in the trench.
FIGS. 5 to 10 are schematic views of the process steps of the present invention.
FIG. 11 is a flow chart of the process steps of the present invention.
Detailed Description
The invention relates to a process method of a shield grid groove type MOSFET, which mainly aims at a polysilicon filling process of a groove of the shield grid groove type MOSFET, and mainly aims at a polysilicon electrode at the lower part of the groove, namely a filling process of a first layer of polysilicon.
The process steps provided by the invention, namely the filling step of the first layer of polysilicon, mainly comprise the following working procedures:
step one, depositing a silicon oxide layer on a semiconductor substrate, such as a silicon substrate or a silicon epitaxy, as shown in fig. 5, and then sequentially depositing a silicon nitride layer and a silicon oxide layer to form an ONO layer; etching the ONO layer to expose a groove etching area; the thickness of the topmost silicon oxide layer in the ONO layer can be increased properly and is higher than that of the silicon nitride layer or the bottom silicon oxide layer.
And step two, taking the ONO layer as a hard mask, and etching the semiconductor substrate downwards to form a groove. As shown in fig. 6, the angle of the trench etched is 87.5 °, and the process of the present invention can increase the trench etching angle to 88 ° or more. Increasing the trench etch angle allows the device cell size to be scaled down appropriately to save area and enhance performance.
And step three, performing back etching on the ONO layer. As shown in fig. 7, the ONO layer is etched back by a wet process, so that the ONO layer serving as a hard mask on both sides of the top of the trench is continuously etched in a lateral direction, thereby enlarging the opening range between the ONO masks on the top of the trench region and optimizing the trench filling performance.
And step four, performing chamfer etching on the bottom of the formed groove. The process ensures that the transition of the bottom of the groove is smoother, namely the bottom of the groove is more rounded, and the film thickness inside the groove is good in uniformity during the deposition of a subsequent dielectric layer.
And fifthly, forming a dielectric layer in the groove by adopting a thermal oxidation method and a CVD (chemical vapor deposition) process. A dense oxide film is formed by a thermal oxidation method, and then a CVD (high-density plasma deposition) process is adopted to deposit an oxide film, such as an HDP CVD (high-density plasma chemical vapor deposition) or SACVD process, so that good pore filling characteristics can be ensured.
And sixthly, depositing and filling a polycrystalline silicon layer in the groove until the deposited polycrystalline silicon layer completely fills the groove. As shown in fig. 10.
And seventhly, carrying out back etching on the deposited polycrystalline silicon layer, filling the groove with the polycrystalline silicon, and then carrying out back etching to form a lower-layer polycrystalline silicon electrode in the shielding grid groove. The underlying polysilicon is finally etched to the state shown in fig. 3.
The process mainly aims at the deposition and back etching of the first layer of polysilicon, and in the subsequent process steps, the process also comprises the steps of forming an inter-polysilicon layer oxide layer, depositing the second layer of polysilicon and back etching to form an upper electrode in the groove, which is the same as the traditional process and is not repeated.
The process can increase the groove etching angle to be more than or equal to 88 degrees, and simultaneously carry out the back etching process of the hard mask layer before the groove chamfering process, thereby improving the top appearance of the groove, improving the hole filling performance of the first layer of polysilicon deposition, enhancing the process tolerance, and improving the hole filling performance of the polysilicon by the medium layer HDP CVD method or SACVD method deposition. The increase of the groove etching angle is beneficial to reducing the layout area of the device unit and improving the performance of the device.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A process method of a shielded gate trench type MOSFET is characterized in that: comprises the following process steps:
firstly, depositing a silicon oxide layer on a semiconductor substrate, and then sequentially depositing a silicon nitride layer and a silicon oxide layer to form an ONO layer; etching the ONO layer to expose a groove etching area;
secondly, etching the semiconductor substrate downwards by taking the ONO layer as a hard mask to form a groove;
thirdly, performing back etching on the ONO layer;
step four, chamfering and etching the bottom of the formed groove;
depositing a dielectric layer in the groove;
depositing and filling a polycrystalline silicon layer in the groove;
and seventhly, etching back the deposited polycrystalline silicon layer.
2. The shielded gate trench MOSFET processing method of claim 1 further comprising: in the first step, the semiconductor substrate comprises a silicon substrate or a silicon epitaxy; the thickness of the oxide layer at the topmost layer of the ONO layer is larger than that of the silicon nitride layer and the silicon oxide layer below the ONO layer.
3. The shielded gate trench MOSFET processing method of claim 1 further comprising: in the second step, the groove angle can reach more than or equal to 88 degrees.
4. The shielded gate trench MOSFET processing method of claim 1 further comprising: in the third step, the ONO layer is etched back by adopting a wet process, so that the ONO layer which is positioned at the two sides of the top of the groove and used as a hard mask is continuously etched transversely, and the opening range between the ONO masks at the top of the groove area is enlarged.
5. The shielded gate trench MOSFET processing method of claim 1 further comprising: in the fourth step, the transition between the bottom of the groove and the side wall of the groove is smoother by chamfering the bottom of the groove, so that the adhesiveness of the dielectric film layer and the attaching appearance of the bottom of the groove are facilitated.
6. The shielded gate trench MOSFET processing method of claim 1 further comprising: in the fifth step, the dielectric layer is formed by a thermal oxidation method and a CVD process, wherein the CVD process comprises HDP CVD or SACVD.
7. The shielded gate trench MOSFET processing method of claim 1 further comprising: and seventhly, after the grooves are filled with the polycrystalline silicon, back etching is carried out to form the lower polycrystalline silicon electrode in the shielding grid grooves.
8. The shielded gate trench MOSFET processing method of claim 1 further comprising: and the subsequent steps comprise depositing an inter-polysilicon oxide film on the upper part of the polysilicon in the trench after the polysilicon etch-back is finished, depositing and filling a second layer of polysilicon and etching back to form a trench upper electrode.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010447881.7A CN111508846A (en) | 2020-05-25 | 2020-05-25 | Process method of shielded gate trench type MOSFET |
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| CN202010447881.7A CN111508846A (en) | 2020-05-25 | 2020-05-25 | Process method of shielded gate trench type MOSFET |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6235643B1 (en) * | 1999-08-10 | 2001-05-22 | Applied Materials, Inc. | Method for etching a trench having rounded top and bottom corners in a silicon substrate |
| US6541382B1 (en) * | 2000-04-17 | 2003-04-01 | Taiwan Semiconductor Manufacturing Company | Lining and corner rounding method for shallow trench isolation |
| US20050142804A1 (en) * | 2003-12-30 | 2005-06-30 | Dongbuanam Semiconductor Inc. | Method for fabricating shallow trench isolation structure of semiconductor device |
| CN102280402A (en) * | 2010-06-12 | 2011-12-14 | 上海华虹Nec电子有限公司 | Method for etching and filling deep groove |
| CN103137483A (en) * | 2011-11-30 | 2013-06-05 | 上海华虹Nec电子有限公司 | Method for eliminating sharp corner at top end of groove |
| CN105448741A (en) * | 2015-12-31 | 2016-03-30 | 上海华虹宏力半导体制造有限公司 | Shield grid groove type MOSFET process method |
| CN106298945A (en) * | 2016-09-30 | 2017-01-04 | 上海华虹宏力半导体制造有限公司 | Shield grid trench MOSFET process |
-
2020
- 2020-05-25 CN CN202010447881.7A patent/CN111508846A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6235643B1 (en) * | 1999-08-10 | 2001-05-22 | Applied Materials, Inc. | Method for etching a trench having rounded top and bottom corners in a silicon substrate |
| US6541382B1 (en) * | 2000-04-17 | 2003-04-01 | Taiwan Semiconductor Manufacturing Company | Lining and corner rounding method for shallow trench isolation |
| US20050142804A1 (en) * | 2003-12-30 | 2005-06-30 | Dongbuanam Semiconductor Inc. | Method for fabricating shallow trench isolation structure of semiconductor device |
| CN102280402A (en) * | 2010-06-12 | 2011-12-14 | 上海华虹Nec电子有限公司 | Method for etching and filling deep groove |
| CN103137483A (en) * | 2011-11-30 | 2013-06-05 | 上海华虹Nec电子有限公司 | Method for eliminating sharp corner at top end of groove |
| CN105448741A (en) * | 2015-12-31 | 2016-03-30 | 上海华虹宏力半导体制造有限公司 | Shield grid groove type MOSFET process method |
| CN106298945A (en) * | 2016-09-30 | 2017-01-04 | 上海华虹宏力半导体制造有限公司 | Shield grid trench MOSFET process |
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