CN111508840B - Stepped GaN gate device and preparation method thereof - Google Patents

Stepped GaN gate device and preparation method thereof Download PDF

Info

Publication number
CN111508840B
CN111508840B CN202010545650.XA CN202010545650A CN111508840B CN 111508840 B CN111508840 B CN 111508840B CN 202010545650 A CN202010545650 A CN 202010545650A CN 111508840 B CN111508840 B CN 111508840B
Authority
CN
China
Prior art keywords
region
layer
gate
etching
gan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010545650.XA
Other languages
Chinese (zh)
Other versions
CN111508840A (en
Inventor
冯光建
蔡永清
陈桥波
黄雷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhejiang Jimaike Microelectronics Co Ltd
Original Assignee
Zhejiang Jimaike Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhejiang Jimaike Microelectronics Co Ltd filed Critical Zhejiang Jimaike Microelectronics Co Ltd
Priority to CN202010545650.XA priority Critical patent/CN111508840B/en
Publication of CN111508840A publication Critical patent/CN111508840A/en
Application granted granted Critical
Publication of CN111508840B publication Critical patent/CN111508840B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention provides a step type GaN grid device and a preparation method thereof, wherein the preparation method comprises the following steps: providing a substrate, growing a GaN channel layer and a barrier layer, and defining a gate, a source region and a drain region; removing the barrier layer of the source-drain region, and growing a doped GaN layer on the source-drain region, wherein the upper surface of the doped GaN layer is higher than the barrier layer; depositing an isolation layer, and defining the isolation layer in the vertical direction as a side wall layer; dividing the area except the side wall layer in the grid area into a zeroth etching area and a zeroth step area, wherein the zeroth etching area, the step area and the grid area have the same extending direction; removing the isolation layer of the zeroth etching area; and depositing a gate metal layer in the gate region. The invention forms the step-type field plate of the grid through the process of isolating the side wall, and improves the voltage resistance of the device by utilizing the step-type field plate while reducing the size of the grid. The size of the grid electrode in the invention is controllable, and the precision requirement on photoetching equipment is not high; the stepped field plate structure and the grid structure are formed together, so that the process conditions are simple and easy to implement, and the repeatability is high.

Description

Stepped GaN gate device and preparation method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a stepped GaN gate device and a preparation method thereof.
Background
The GaN High Electron Mobility Transistor (HEMT) has a good application prospect in high voltage scenarios due to its large band gap.
Currently, to further improve the voltage endurance of GaN HEMT devices, the gate-to-drain distance L is generally increasedgdOr a field plate structure is added above the grid electrode towards the direction of the drain electrode so as to adjust the electric field distribution of the drain end and enhance the voltage resistance of the device.
However, increasing the gate-to-drain distance LgdThe method not only increases the device area, but also is not favorable forThe miniaturization of the device is realized, the access resistance is increased, and the frequency performance of the device is weakened; the process method for increasing the field plate structure needs to introduce a preparation flow of the field plate structure comprising additional processes such as photoetching, metal deposition, etching and the like, so that the process cost for preparing the device is increased.
Therefore, there is a need for a new stepped GaN gate device and a method for fabricating the same to solve the above-mentioned problems.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a stepped GaN gate device and a manufacturing method thereof, which are used to solve the problem that the voltage endurance of a GaN HEMT cannot be effectively improved in the prior art.
In order to achieve the above and other related objects, the present invention provides a method for manufacturing a stepped GaN gate device, comprising:
1) providing a substrate, epitaxially growing a GaN channel layer and a barrier layer on the substrate, and defining a gate region, a source region and a drain region;
2) removing the barrier layers of the source region and the drain region, and epitaxially growing a doped GaN layer on the source region and the drain region, wherein the upper surface of the doped GaN layer is higher than the upper surface of the barrier layers;
3) depositing isolation layers on the gate region, the source region and the drain region, and defining the isolation layers distributed in the vertical direction as side wall layers;
4) dividing the area except the side wall layer in the gate area into a zeroth etching area and a zeroth step area, wherein the zeroth etching area, the zeroth step area and the gate area have the same extending direction;
5) removing the isolation layer on the zeroth etching area;
6) and depositing a grid metal layer in the grid region.
As an alternative of the invention, after the step 5), the method also comprises a process of circularly executing the following steps for N times, wherein N represents that the current cyclic process is the number of times, and N is more than or equal to N and more than or equal to 2;
5-a) depositing isolation layers on the gate region, the source region and the drain region;
5-b) dividing the area except the side wall layer in the n-1 th etching area into an n-th etching area and an n-th step area, wherein the n-th step area is adjacent to the n-1 th step area, and the n-th etching area, the n-th step area and the grid area have the same extension direction;
5-c) removing the isolation layer on the nth etching area.
As an alternative of the present invention, after step 6), the following steps are further included:
7) and forming a source metal layer and a drain metal layer on the doped GaN layer.
As an alternative of the present invention, a buffer layer is further formed between the substrate and the GaN channel layer, the buffer layer including an AlGaN layer; the barrier layer comprises an InAlN layer or an AlGaN layer.
As an alternative of the invention, the method of growing the doped GaN layer comprises metal oxide chemical vapor deposition, the doped GaN layer is doped n-type, and the doping source comprises SiH4The doping concentration of the n-type doping is more than 1 × 1019/cm3。
As an alternative of the invention, the isolation layer comprises a SiN layer, the method of forming the SiN layer comprising chemical vapour deposition, the SiN layer having a thickness in the range of 50 to 100 nm.
The present invention also provides a stepped GaN gate device, comprising:
a substrate having gate, source and drain regions defined thereon
A channel layer and a barrier layer sequentially formed on the substrate, the barrier layer being located within the gate region;
the doped GaN layer is formed on the source region and the drain region, and the upper surface of the doped GaN layer is higher than the upper surface of the barrier layer;
the side wall isolation layer is formed on the side wall of the doped GaN layer, and the step isolation layer is formed above the barrier layer; the area in the grid region except the side wall isolation layer is divided into an etching region and a step region, and the step region is adjacent to the doped GaN layer on one side of the grid region; the step isolation layer covers the step region;
a gate metal layer formed in the gate region.
As an alternative of the present invention, the step isolation layer has a plurality of step structures, and a height of the step structure near the gate edge is higher than a height of the step structure far from the gate edge.
As an alternative of the present invention, the stepped GaN gate device further includes a source metal layer and a drain metal layer formed on the doped GaN layer.
As an alternative of the present invention, a buffer layer is further formed between the substrate and the GaN channel layer, the buffer layer including an AlGaN layer; the barrier layer comprises an InAlN layer or an AlGaN layer.
As an alternative of the invention, the doped GaN layer is doped n-type, and the doping concentration of the n-type doping is more than 1 × 1019/cm3。
As an alternative of the invention, the isolation layer comprises a SiN layer having a thickness in the range of 50 to 100 nm.
As described above, the present invention provides a stepped GaN gate device and a method for manufacturing the same, which have the following advantages:
the invention forms the step-type field plate of the grid through the process of isolating the side wall, and improves the voltage resistance of the device by utilizing the step-type field plate while reducing the size of the grid. The size of the grid electrode in the invention is controllable, and the precision requirement on photoetching equipment is not high; the stepped field plate structure and the grid structure are formed together, so that the process conditions are simple and easy to implement, and the repeatability is high.
Drawings
Fig. 1 is a flowchart illustrating a method for fabricating a stepped GaN gate device according to an embodiment of the invention.
Fig. 2 is a schematic cross-sectional view of a GaN channel layer and a barrier layer epitaxially grown on a substrate according to a first embodiment of the invention.
Fig. 3 is a schematic cross-sectional view illustrating the removal of the barrier layer in the source region and the drain region by dry etching according to the first embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view illustrating the growth of doped GaN layers in the source region and the drain region according to a first embodiment of the present invention.
FIG. 5 is a schematic cross-sectional view illustrating a deposited isolation layer according to an embodiment of the invention.
Fig. 6 is a schematic cross-sectional view illustrating a zeroth etching region and a zeroth step region are divided in a gate region and an etching mask is formed according to a first embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view illustrating the isolation layer on the doped GaN layer and the zeroth etched region being removed by etching in the first embodiment of the present invention, and the isolation layer being deposited.
Fig. 8 is a schematic cross-sectional view illustrating a first etching region and a first step region are divided in a zeroth etching region and an etching mask is formed according to a first embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view illustrating the first etched region and the isolation layer on the doped GaN layer being etched away according to a first embodiment of the invention.
Fig. 10 is a schematic cross-sectional view illustrating a gate metal layer, a source metal layer and a drain metal layer formed according to an embodiment of the invention.
Element numbers are used for illustration.
100a substrate; 100a gate region; 100b source region; 100c drain region; 100d the zeroth etching area; 100e zeroth step area; 100f a first etching area; 100g of a first stepped area; 101a GaN channel layer; 102a barrier layer; 102a etching the mask; 103 a buffer layer; 104 doping a GaN layer; 105 an isolation layer; 105a etching the mask; 105b a side wall isolation layer; 105c a step spacer; 106 a gate metal layer; 107 a source metal layer; 108 a drain metal layer; S1-S6 steps 1) -6).
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 10. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
Referring to fig. 1 to 10, the present embodiment provides a method for manufacturing a stepped GaN gate device, which includes the following steps:
1) providing a substrate, epitaxially growing a GaN channel layer and a barrier layer on the substrate, and defining a gate region, a source region and a drain region;
2) removing the barrier layers of the source region and the drain region, and epitaxially growing a doped GaN layer on the source region and the drain region, wherein the upper surface of the doped GaN layer is higher than the upper surface of the barrier layers;
3) depositing isolation layers on the gate region, the source region and the drain region, and defining the isolation layers distributed in the vertical direction as side wall layers;
4) dividing the area except the side wall layer in the gate area into a zeroth etching area and a zeroth step area, wherein the zeroth etching area, the zeroth step area and the gate area have the same extending direction;
5) removing the isolation layer on the zeroth etching area;
6) and depositing a grid metal layer in the grid region.
In step 1), referring to step S1 of fig. 1 and fig. 2, a substrate 100 is provided, a GaN channel layer 101 and a barrier layer 102 are epitaxially grown on the substrate 100, and a gate region 100a, a source region 100b and a drain region 100c are defined.
As an example, as shown in fig. 2, the epitaxial substrate 100 includes a SiC substrate, and may be a substrate such as Si, sapphire, or GaN. A buffer layer 103 for relieving lattice mismatch is further formed between the substrate 100 and the GaN channel layer 101, and the buffer layer 103 includes an AlGaN layer. The barrier layer 102 comprises an InAlN layer or an AlGaN layer. After the GaN channel layer 101 and the barrier layer 102 are epitaxially grown, a gate region 100a, a source region 100b, and a drain region 100c are respectively defined on the surfaces thereof according to device design requirements.
Optionally, a nucleation layer for nucleation of epitaxial growth is further formed between the epitaxial substrate 100 and the buffer layer 103, and the nucleation layer comprises an AlN layer; a back barrier layer including an AlN layer, an AlGaN layer, or an InGaN layer is further formed between the buffer layer 103 and the GaN channel layer 101.
In addition, the invention is not limited to the demarcated areas of the gate region 100a, the source region 100b and the drain region 100c shown in fig. 2, and the design area and shape of the gate source/drain region can be adjusted according to the design requirements of the device.
In step 2), please refer to step S2 of fig. 1 and fig. 3 to 4, the barrier layer 102 of the source region 100b and the drain region 100c is removed, and a doped GaN layer 104 is epitaxially grown on the source region 100b and the drain region 100c, wherein an upper surface of the doped GaN layer 104 is higher than an upper surface of the barrier layer 102.
As shown in fig. 3, an etching mask 102a is formed on the gate region 100a by a photolithography process, and the barrier layer 102 of the source region 100b and the drain region 100c is removed by dry etching. The dry etching includes ICP dry etching using Cl-based etching gas. After dry etching, the barrier layer 102 is removed from the source region 100b and the drain region 100c, exposing the underlying GaN channel layer 101.
As shown in fig. 4, a doped GaN layer 104 is epitaxially grown in the source region 100b and the drain region 100c, and the upper surface of the doped GaN layer 104 is higher than the upper surface of the barrier layer 102. Optionally, the method for growing the doped GaN layer 104 includes metal oxide chemical vapor deposition, the doped GaN layer 104 is n-type doped, and the doping source includes SiH4The doping concentration of the n-type doping is more than 1 × 1019/cm3。
In step 3), referring to step S3 of fig. 1 and fig. 5, an isolation layer 105 is deposited on the gate region 100a, the source region 100b and the drain region 100c, and the isolation layer 105 distributed in the vertical direction is defined as a sidewall layer.
As shown in fig. 5, the isolation layer 105 includes a SiN layer, a method of forming the SiN layer includes chemical vapor deposition, a thickness of the SiN layer ranges from 50 nm to 100nm, and the thickness of the isolation layer 105 may be adjusted or other dielectric materials may be selected to form the isolation layer 105 according to device design requirements.
In step 4), please refer to step S4 of fig. 1 and fig. 6, the area of the gate 101a except for the sidewall layer is divided into a zeroth etched area 100d and a zeroth step area 100e, and the zeroth etched area 100d, the zeroth step area 100e and the gate 100a have the same extending direction.
As shown in fig. 6, the gate region 101a, except for the sidewall layers on both sides, is divided into a zeroth etched region 100d and a zeroth step region 100e, where the zeroth etched region 100d, the zeroth step region 100e and the gate region 100a have the same extending direction, and all extend in a direction perpendicular to the cross section in fig. 6.
In step 5), referring to step S5 of fig. 1 and fig. 6 to 9, the isolation layer 105 on the zeroth etching region 100d is removed.
As shown in fig. 6, an etching mask 105a is formed in the zeroth step region 100e by a photolithography process to expose the zeroth etching region 100d and the isolation layer 105 on the doped GaN layer 104. Specifically, the etching mask 105a determines the step width of the step-type gate of the GaN device of the present invention, and the occupied area thereof can be adjusted according to the requirements of the device design on the number and the shape of the steps.
As shown in fig. 6 to 7, the isolation layer 105 is anisotropically dry etched by using the etching mask 105a as an etching mask, the isolation layer 105 on the zeroth etching region 100d and the doped GaN layer 104 is removed, and the isolation layer 105 on the sidewall layer and the zeroth step region 100e is remained. The dry etching includes RIE etching using F-based etching gas and has anisotropy. After the anisotropic etching, the isolation layer 105 of the sidewall layer will be preserved, and only the isolation layer 105 on the surface area not covered by the etching mask 105a is etched away.
As an example, as shown in fig. 7 to 9, after step 5), a process of circularly executing the following steps for a total of N times is further included, N represents that the current cyclic process is the number of times, and N ≧ 1;
5-a) depositing an isolation layer 105 on said gate region 100a, said source region 100b and said drain region 100 c;
5-b) dividing the area except the side wall layer in the n-1 th etching area into an n-th etching area and an n-th step area, wherein the n-th step area is adjacent to the n-1 th step area, and the n-th etching area, the n-th step area and the gate area 100a have the same extension direction;
5-c) removing the isolation layer 105 on the nth etched region.
In step 5-a), referring to fig. 7, after the process of removing the isolation layer 105 on the zeroth etching region 100d in step 5) is completed, a layer of isolation layer 105 is deposited again, which is the same as the process of depositing the isolation layer 105 in step 3).
In step 5-b), referring to fig. 8, dividing a region excluding the sidewall layer in a zeroth etching region 100d into a first etching region 100f and a first step region 100g, where the first step region 100g is adjacent to the zeroth step region 100e, and the first etching region 100f, the first step region 100g, and the gate region 100a have the same extending direction;
in step 5-c), referring to fig. 9, the isolation layer 105 on the first etching region 100f is removed. The process is the same as the process of etching and removing the isolation layer 105 in fig. 6 to 7 of step 5).
As an example, in the present embodiment, N =1, that is, after the zeroth etching region 100d and the zeroth stepped region 100e are formed in fig. 7, the first etching region 100f and the first stepped region 100g are formed by performing the steps 5-a) to 5-c) once. In other embodiments of the present invention, N may also be set to 2 or more than 2 times, so as to further form structures such as a second etching region and a second step region, or even a third etching region and a third step region by performing steps 5-a) to 5-c) in the first etching region 100f in a cyclic manner.
For a stepped GaN gate structure that performs N cycles of steps 5-a) to 5-c), the length of the gate contact region in the gate region 100a where the subsequently formed gate material is in direct contact with the barrier layer 102 can be expressed as:
L1-2(N+1)L2-(N+1)L3
in the above formula, L1The length occupied by the gate region 100 a; l is2The thickness of the spacer layer is assumed here to be L for each deposition of the isolation layer 1052(ii) a L3 is the length occupied by the step area formed each time and is also the length occupied by the photoetching mask plate, and the length occupied by the step area formed each time is assumed to be the same; the substitution in the formula is (N +1) because the calculation of the length further includes the zeroth etching region 100d and the zeroth step region 100e formed before the steps 5-a) to 5-c) are performed.
In step 6), referring to step S6 of fig. 1 and fig. 10, a gate metal layer 106 is deposited on the gate region 100 a. Optionally, a source metal layer 107 and a drain metal layer 108 are further formed on the doped GaN layer 101 on both sides of the gate region 100a, and the source metal layer 107 and the drain metal layer 108 form ohmic contact with the doped GaN layer 101 on the lower layer. As shown in fig. 10, in the gate region 100a, the gate metal layer 106 deposited in the left gate contact region directly contacts the underlying barrier layer 102 to form a gate structure; the gate metal layer 106 of the right step region is in contact with the isolation layer 105 and is attached to the appearance of the isolation layer 105, so that a step-type field plate structure which is lifted up step by step when being far away from the gate structure is formed. Since the multi-layered isolation layer 105 formed in step 5) has the same material, the boundaries between the layers are not clearly shown in fig. 10.
It should be noted that, for convenience of description, the steps are numbered, but this does not represent that the order of execution of the steps is limited. In other embodiments of the present invention, the steps in this embodiment may also adjust their implementation sequence according to actual requirements.
The stepped gate field plate formed in the embodiment can regulate and control the electric field distribution in the channel, and reduce the highest electric field intensity, thereby improving the voltage resistance of the device. In addition, compared with a field plate process in the prior art, the stepped field plate structure in the embodiment is formed together with the side wall layer and the gate structure, so that the process is simple and good in repeatability; the step morphology is formed step by step through the technological process of multi-step mask and etching, the size of the grid electrode is controllable, the size can be controlled to be smaller, and the method is not limited by the precision limited by photoetching equipment and technology.
Example two
As shown in fig. 10, the present embodiment provides a stepped GaN gate device, including:
a substrate 100 having a gate region 100a, a source region 100b and a drain region 100c defined thereon
A channel layer 101 and a barrier layer 102 sequentially formed on the substrate 100, the barrier layer 102 being located in the gate region 100 a;
a doped GaN layer 104 formed in the source region 100b and the drain region 100c, and having an upper surface higher than an upper surface of the barrier layer 102;
a sidewall spacer 105b formed on the sidewall of the doped GaN layer 104 and a step spacer 105c formed over the barrier layer 102; the area of the gate region 100a except the sidewall isolation layer 105b is divided into an etching region and a step region, and the step region is adjacent to the doped GaN layer 104 on one side of the gate region 100 a; the step isolation layer 105c covers the step region;
a gate metal layer 106 formed in the gate region 100 a.
As an example, as shown in fig. 10, the step isolation layer 105c has a plurality of step structures, and the height of the step structure near the edge of the gate region 100a is higher than the height of the step structure far from the edge of the gate region 100 a. In fig. 10, the step structure on the right side of the gate 100a has 2 levels, and the height increases from left to right, and the height of the step structure on the side close to the edge of the gate 100a is higher; while the gate metal layer 106 in the left side gate contact region directly contacts the underlying barrier layer 102 to form a gate structure.
As an example, as shown in fig. 10, the stepped GaN gate device further includes a source metal layer 107 and a drain metal layer 108 formed on the doped GaN layer 104. The source metal layer 107 and the drain metal layer 108 form ohmic contacts with the underlying doped GaN layer 101.
As an example, as shown in fig. 10, a buffer layer 103 is further formed between the substrate 100 and the GaN channel layer 101, and the buffer layer 103 includes an AlGaN layer; the barrier layer 102 comprises an InAlN layer or an AlGaN layer. The buffer layer 103 serves to alleviate lattice mismatch between the substrate and GaN.
As an example, as shown in fig. 10, the doped GaN layer 104 is n-type doped with a doping concentration greater than 1 × 1019/cm3. Optionally, the method of growing the doped GaN layer 104 includes metal oxide chemical vapor deposition (cvd), and the doping source includes SiH4。
As an example, as shown in fig. 10, the isolation layer 105 includes a SiN layer having a thickness ranging from 50 to 100 nm. Optionally, the method for forming the SiN layer includes chemical vapor deposition, and the thickness of the isolation layer 105 may also be adjusted or other dielectric materials may be selected to form the isolation layer 105 according to device design requirements.
The stepped GaN gate device provided by the embodiment can regulate and control the electric field distribution in the channel by arranging the stepped gate field plate, and reduce the highest electric field intensity, thereby improving the voltage resistance of the device. The step-type gate field plate can be formed by the preparation method shown in the first embodiment, or by using other feasible preparation processes.
In summary, the present invention provides a step-type GaN gate device and a method for manufacturing the same, where the method for manufacturing the step-type GaN gate device includes the following steps: 1) providing a substrate, epitaxially growing a GaN channel layer and a barrier layer on the substrate, and defining a gate region, a source region and a drain region; 2) removing the barrier layers of the source region and the drain region, and epitaxially growing a doped GaN layer on the source region and the drain region, wherein the upper surface of the doped GaN layer is higher than the upper surface of the barrier layers; 3) depositing isolation layers on the gate region, the source region and the drain region, and defining the isolation layers distributed in the vertical direction as side wall layers; 4) dividing the area except the side wall layer in the gate area into a zeroth etching area and a zeroth step area, wherein the zeroth etching area, the zeroth step area and the gate area have the same extending direction; 5) removing the isolation layer on the zeroth etching area; 6) and depositing a grid metal layer in the grid region. The invention forms the step-type field plate of the grid through the process of isolating the side wall, and improves the voltage resistance of the device by utilizing the step-type field plate while reducing the size of the grid. The size of the grid electrode in the invention is controllable, and the precision requirement on photoetching equipment is not high; the stepped field plate structure and the grid structure are formed together, so that the process conditions are simple and easy to implement, and the repeatability is high.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (6)

1. A preparation method of a stepped GaN gate device is characterized by comprising the following steps:
1) providing a substrate, epitaxially growing a GaN channel layer and a barrier layer on the substrate, and defining a gate region, a source region and a drain region;
2) removing the barrier layers of the source region and the drain region, and epitaxially growing a doped GaN layer on the source region and the drain region, wherein the upper surface of the doped GaN layer is higher than the upper surface of the barrier layers;
3) depositing isolation layers on the gate region, the source region and the drain region, and defining the isolation layers distributed in the vertical direction as side wall layers;
4) dividing the area except the side wall layer in the gate region into a zero etching region and a zero step region, wherein the zero etching region, the zero step region and the gate region have the same extension direction, the extension direction is perpendicular to the connecting line direction of the source region and the drain region, and the zero etching region is positioned on one side far away from the drain region relative to the zero step region;
5) removing the isolation layer on the zeroth etching area;
6) and depositing a grid metal layer in the grid region.
2. The method for manufacturing the stepped GaN gate device according to claim 1, wherein after the step 5), the method further comprises a process of circularly executing the following steps for N times, wherein N represents the current cyclic process as the number of times, and N is greater than or equal to N and greater than or equal to 2;
5-a) depositing isolation layers on the gate region, the source region and the drain region;
5-b) dividing a region except the side wall layer in the n-1 th etching region into an nth etching region and an nth step region, wherein the nth step region is adjacent to the n-1 th step region, the nth etching region, the nth step region and the gate region have the same extension direction, the extension direction is perpendicular to the connecting line direction of the source region and the drain region, and the nth etching region is positioned on one side far away from the drain region relative to the nth step region;
5-c) removing the isolation layer on the nth etching area.
3. The method of manufacturing a stepped GaN gate device of claim 1, further comprising, after step 6), the steps of:
7) and forming a source metal layer and a drain metal layer on the doped GaN layer.
4. The method of claim 1, wherein a buffer layer is further formed between the substrate and the GaN channel layer, the buffer layer comprising an AlGaN layer; the barrier layer comprises an InAlN layer or an AlGaN layer.
5. The method of claim 1, wherein growing the GaN-doped layer comprises chemical vapor deposition of metal oxide, the GaN-doped layer is n-type doped, and the dopant source comprises SiH4The doping concentration of the n-type doping is more than 1 × 1019/cm3。
6. The method of claim 1, wherein the isolation layer comprises a SiN layer, and the SiN layer is formed by chemical vapor deposition, wherein the SiN layer has a thickness in a range of 50 to 100 nm.
CN202010545650.XA 2020-06-16 2020-06-16 Stepped GaN gate device and preparation method thereof Active CN111508840B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010545650.XA CN111508840B (en) 2020-06-16 2020-06-16 Stepped GaN gate device and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010545650.XA CN111508840B (en) 2020-06-16 2020-06-16 Stepped GaN gate device and preparation method thereof

Publications (2)

Publication Number Publication Date
CN111508840A CN111508840A (en) 2020-08-07
CN111508840B true CN111508840B (en) 2020-10-16

Family

ID=71875380

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010545650.XA Active CN111508840B (en) 2020-06-16 2020-06-16 Stepped GaN gate device and preparation method thereof

Country Status (1)

Country Link
CN (1) CN111508840B (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3180776B2 (en) * 1998-09-22 2001-06-25 日本電気株式会社 Field-effect transistor
JP5334149B2 (en) * 2006-06-02 2013-11-06 独立行政法人産業技術総合研究所 Nitride semiconductor field effect transistor
CN105448964A (en) * 2015-11-23 2016-03-30 西安电子科技大学 Composite stepped field plate trench gate AlGaN/GaN HEMT high-voltage device structure and manufacturing method therefor
KR102271008B1 (en) * 2017-10-27 2021-06-29 삼성전자주식회사 Semiconductor device
CN109103104A (en) * 2018-07-20 2018-12-28 深圳市晶相技术有限公司 Semiconductor devices and preparation method thereof

Also Published As

Publication number Publication date
CN111508840A (en) 2020-08-07

Similar Documents

Publication Publication Date Title
JP7497446B2 (en) Semiconductor devices, their manufacturing methods and applications
US20140312431A1 (en) Semiconductor Devices and Methods of Manufacture Thereof
CN105932041B (en) The face N GaN base fin high electron mobility transistor and production method
US10700189B1 (en) Semiconductor devices and methods for forming the same
CN108389904B (en) GaN HEMT device and preparation method thereof
CN104269434A (en) Transistor with high electronic mobility
CN109524460A (en) High hole mobility transistor
CN111430240A (en) GaN device based on field plate composite structure and preparation method thereof
CN111952355B (en) GaN HEMT device based on multi-leakage-finger structure and preparation method thereof
WO2022199309A1 (en) Hemt device having p-gan cap layer and preparation method therefor
CN117438457B (en) Groove gate type GaN-based HEMT device and preparation method thereof
CN112216741A (en) Insulation structure of high electron mobility transistor and manufacturing method thereof
CN113035783A (en) Graphene device and GaN device heterogeneous integrated structure and preparation method thereof
CN111508840B (en) Stepped GaN gate device and preparation method thereof
TW202109739A (en) Semiconductor device and method of manufacturing the same
CN109727863A (en) A kind of AlGan/GaN HEMT device structure and production method based on self-registered technology
CN113594035A (en) HEMT device and preparation method thereof
CN113823557A (en) HEMT device and preparation method thereof
CN111584619A (en) GaN device and preparation method
CN113889412B (en) Ohmic contact GaN device and preparation method thereof
TWI791364B (en) Method of manufacturing normally-off gallium nitride device
CN112310211B (en) Semiconductor device and method for manufacturing the same
CN112490278B (en) Semiconductor epitaxial structure with reduced defects
US7205657B2 (en) Complimentary lateral nitride transistors
US20240128365A1 (en) Nitride based semiconductor device and method for manufacturing same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant