CN111446535A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

Info

Publication number
CN111446535A
CN111446535A CN201910058281.9A CN201910058281A CN111446535A CN 111446535 A CN111446535 A CN 111446535A CN 201910058281 A CN201910058281 A CN 201910058281A CN 111446535 A CN111446535 A CN 111446535A
Authority
CN
China
Prior art keywords
antenna
electronic
electronic component
package
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910058281.9A
Other languages
English (en)
Other versions
CN111446535B (zh
Inventor
蔡文荣
叶懋华
邱志贤
蔡瀛洲
柯俊吉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN111446535A publication Critical patent/CN111446535A/zh
Application granted granted Critical
Publication of CN111446535B publication Critical patent/CN111446535B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/50—Structural association of antennas with earthing switches, lead-in devices or lightning protectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/0087—Apparatus or processes specially adapted for manufacturing antenna arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
    • H01Q21/061—Two dimensional planar arrays
    • H01Q21/065—Patch antenna array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
    • H01Q9/04—Resonant antennas
    • H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
    • H01Q9/0414—Substantially flat resonant element parallel to ground plane, e.g. patch antenna in a stacked or folded configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6688—Mixed frequency adaptations, i.e. for operation at different frequencies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/40—Radiating elements coated with or embedded in protective material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
    • H01Q9/04—Resonant antennas
    • H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Details Of Aerials (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)

Abstract

一种电子封装件及其制法，通过于承载结构下侧接置天线框架、第一电子元件与第二电子元件，且于该承载结构上侧结合天线结构，以令该第一电子元件电性连接该天线结构，且该第二电子元件电性连接该天线框架，以经由同时整合两种不同天线型态于同一电子封装件中，使该电子封装件于后续应用的电路板，无需增加面积即可具备两种波长的传输讯号的功能。

Description

电子封装件及其制法
技术领域
本发明关于一种电子封装件，特别是关于一种具有天线结构的电子封装件及其制法。
背景技术
现今无线通讯技术已广泛应用于各式消费性电子产品(如手机、平板电脑等)，以利接收或发送各种无线讯号。同时，为满足消费性电子产品的便于携带性及上网便利性(如观看多媒体内容)，无线通讯模块的制造与设计朝轻、薄、短、小的需求作开发，其中，平面天线(Patch Antenna)因具有体积小、重量轻与制造容易等特性而广泛利用在电子产品的无线通讯模块中。
目前的多媒体内容因画质的提升而造成其档案资料量变得更大，故无线传输的频宽也需变大，因而产生第五代的无线传输(5G)，且5G因传输频率较高，其相关无线通讯模块的尺寸的要求也较高。
5G的应用频率范围约在1GHz～1000GHz之间的高频频段，其商业应用模式为5G搭配4G LTE，并于户外架设一蜂巢式基站以配合设于室内的小基站，故5G行动通讯会于基站内使用大量天线以符合5G系统的大容量快速传输且低延迟。
图1为现有无线通讯模块1的立体示意图。如图1所示，该无线通讯模块1包括：一基板10、设于该基板10上的多个电子元件11、一天线结构12以及封装材13。该基板10为电路板并呈矩形体。该电子元件11设于该基板10上且电性连接该基板10。该天线结构12为平面型且具有一天线本体120与一导线121a，该天线本体120经由该导线121a电性连接该电子元件11。该封装材13覆盖该电子元件11与该部分导线121a。
然而，5G系统因讯号品质与传输速度要求，需更多天线配置，以提升讯号的品质与传输速度，而现有无线通讯模块1中，该天线结构12为平面型，且该基板10的长宽尺寸均为固定，因而限制该天线结构12的功能，故无法同时配合5G毫米波及Sub-6Ghz波长的天线运作，因而该无线通讯模块1难以达到5G系统的天线运作的需求。
此外，若终端产品欲同时具备5G毫米波及Sub-6Ghz波长的天线运作，需将两种天线封装结构分别接置于终端产品(如智能手机)的电路板上，致使该电路板的其它空间上需布设不同功能的封装结构或被动元件，故该终端产品所用的电路板的体积需增加，因而该终端产品难以符合轻薄短小的需求。
又，考量该天线结构12为平面型，且基于该天线结构12与该电子元件11之间的电磁辐射特性及该天线结构12的体积限制，故于制程中，该天线本体120难以与该电子元件11整合制作，也就是，该封装材13仅覆盖该电子元件11，并未覆盖该天线本体120，致使封装制程的模具需对应该些电子元件11的布设区域，而非对应该基板10的尺寸，因而不利于封装制程。
另外，因该天线结构12为平面型，故需于该基板10的表面上增加布设区域(未形成该封装材13的区域)以形成该天线本体120，致使该基板10的宽度难以缩减，因而难以缩小该无线通讯模块1的宽度，导致该无线通讯模块1无法达到微小化的需求。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失，本发明提供一种电子封装件及其制法，无需增加面积即可具备两种波长的传输讯号的功能。
本发明的电子封装件，包括：承载结构，其具有相对的第一侧与第二侧；天线结构，其设于该承载结构的第二侧上；天线框架，其设于该承载结构的第一侧上；第一电子元件，其接置于该承载结构的第一侧上并耦接该天线结构；以及第二电子元件，其接置于该承载结构的第一侧上并耦接该天线框架。
本发明还提供一种电子封装件的制法，包括：提供一具有相对的第一侧与第二侧的承载结构，且于该承载结构的第一侧上设置第一电子元件与第二电子元件；于该承载结构的第二侧上设置天线结构，并使该第一电子元件耦接该天线结构；以及设置天线框架于该承载结构的第一侧上，并使该第二电子元件耦接该天线框架。
前述的电子封装件及其制法中，该承载结构包含有第一线路部，以电性连接该第一电子元件与该天线结构。
前述的电子封装件及其制法中，该承载结构包含有第二线路部，以电性连接该第二电子元件与该天线框架。
前述的电子封装件及其制法中，该天线结构包含绝缘体与天线本体，该天线本体包含有相对配置于该绝缘体两侧的第一天线层与第二天线层，且该绝缘体与该第二天线层结合于该承载结构的第二侧上。
前述的电子封装件及其制法中，该天线结构为毫米波式天线。
前述的电子封装件及其制法中，该天线框架为Sub-6GHz波长型天线。
前述的电子封装件及其制法中，该第一电子元件与第二电子元件为不同的射频芯片。
前述的电子封装件及其制法中，该第一电子元件为具发射毫米波功能的半导体芯片。
前述的电子封装件及其制法中，该第二电子元件为具发射Sub-6GHz波长功能的半导体芯片。
前述的电子封装件及其制法中，还包括形成多个导电元件于该承载结构的第一侧上。
前述的电子封装件及其制法中，还包括形成封装层于该承载结构的第一侧上，使该封装层包覆该天线框架、第一电子元件与第二电子元件。例如，该封装层具有外露该承载结构的开孔，以于该开孔中形成导电元件，使该导电元件电性连接该承载结构。
前述的电子封装件及其制法中，该第一电子元件与第二电子元件位于该天线框架内。
前述的电子封装件及其制法中，该第一电子元件与第二电子元件的至少其中一者位于该天线框架外。
前述的电子封装件及其制法中，该第一电子元件与第二电子元件间隔排设于该承载结构的第一侧上。
前述的电子封装件及其制法中，该第一电子元件与第二电子元件为相互堆叠。
由上可知，本发明的电子封装件及其制法中，主要经由同时整合该天线结构及该天线框架于同一电子封装件中，故相较于现有技术的分别形成两封装结构而设于电路板上，本发明的电子封装件于后续应用的电路板，其面积无需增加，即可具备两种波长的传输讯号的功能，因而能达到终端产品轻薄短小的需求。
此外，本发明经由该天线框架的设计，以于制程中，该封装层能覆盖该第一电子元件与第二电子元件及该天线框架，使封装制程的模具能对应该承载结构的尺寸，而有利于封装制程。
又，该天线框架架设于该承载结构上而呈立体式天线，因而无需于该承载结构上增加布设区域，故相较于现有技术，本发明能于预定的承载结构尺寸下增加天线功能，因而得以达到具备两种天线运作的需求，且能使该电子封装件符合微小化的需求。
附图说明
图1为现有无线通讯模块的剖面示意图。
图2A至图2C为本发明的电子封装件的制法的剖面示意图。
图2A’及图2A”为图2A的其它实施例示意图。
图2D为图2C的另一实施例示意图。
图3A至图3C为本发明的电子封装件的制法其它实施例的剖面示意图。
符号说明
1 无线通讯模块
2,2’,2”,3,3’,3” 电子封装件
2a,12 天线结构
2b 天线框架
9 电路板
10 基板
11 电子元件
13 封装材
20 承载结构
20a 第一侧
20b 第二侧
21a,31a 第一电子元件
21b,31b 第二电子元件
22 绝缘体
22a 第一表面
22b 第二表面
23,120 天线本体
23a 第一天线层
23b 第二天线层
24 配线部
25 封装层
26 导电元件
121a 导线
200 介电材
201 第一线路部
202 第二线路部
210,310 导电凸块
211,311 焊线
240 导电层
241 布线层
242 外接垫
250 开孔。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2C为本发明的电子封装件的第一实施例的制法的剖面示意图。
如图2A所示，提供一具有相对的第一侧20a与第二侧20b的承载结构20，且于该第一侧20a上接置有至少一天线框架2b、第一电子元件21a与第二电子元件21b，并于该第二侧20b上结合一天线结构2a。
所述的承载结构20例如为具有核心层与线路结构的封装基板(substrate)或无核心层(coreless)的线路结构，其包含介电材200及至少一形成于该介电材200上的第一线路部201与第二线路部202，如至少一扇出(fan out)型重布线路层(redistribution layer，简称RDL)。
在本实施例中，该承载结构20还可具有配线部24，其包含一可接地该天线结构2a的导电层240、至少一电性连接该导电层240与该第一线路部201、第二线路部202的布线层241、及多个电性连接该布线层241并外露于该第一侧20a的外接垫242。例如，该配线部24为可与该第一及第二线路部201,202一起制作于该介电材200中。
此外，该导电层240可为至少一完整、网状或任意图案的金属薄片(foil)；或者，该导电层240可为图案化的导电材。
所述的第一电子元件21a与第二电子元件21b设于该承载结构20的第一侧20a上，例如该第一电子元件21a与第二电子元件21b为不同的射频芯片。
在本实施例中，该第一电子元件21a为具发射5G毫米波(㎜Wave)功能的半导体芯片，其电性连接该第一线路部201，且该第二电子元件21b为具发射Sub-6GHz波长功能的半导体芯片，其电性连接该第二线路部202。
此外，该第一电子元件21a经由多个如焊锡材料的导电凸块210以覆晶方式设于该第一线路部201上并电性连接该第一线路部201；或者，该第一电子元件21a可经由多个焊线211(如图2A’所示)以打线方式电性连接该第一线路部201；亦或，该第一电子元件21a可直接接触该第一线路部201。同理地，该第二电子元件21b电性连接该第二线路部202的方式也可采用上述方式。然而，有关该第一电子元件21a与第二电子元件21b电性连接该承载结构20的方式不限于上述。
又，于同一制程中，该第一电子元件21a电性连接该承载结构20的方式与该第二电子元件21b电性连接该承载结构20的方式可相同(如图2A及图2A’所示)或不相同(如图2A”所示)。
另外，该第一电子元件21a与第二电子元件21b水平间隔排设于该承载结构20的第一侧20a上。
所述的天线结构2a为毫米波式天线，其对应该第一电子元件21a作配置。
在本实施例中，该天线结构2a包含结合于该第二侧20b上的绝缘体22及天线本体23。例如，该绝缘体22具有相对的第一表面22a与第二表面22b，并以该第二表面22b结合该承载结构20的第二侧20b，其中，形成该绝缘体22的材质为聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(epoxy)或封装材(molding compound)等，但并不限于上述。
此外，该天线本体23结合该绝缘体22并耦接(如电性连接)该第一电子元件21a，以发射毫米波。例如，该天线本体23包含相互分离且相对应配置于该绝缘体22相对两侧的一第一天线层23a与一第二天线层23b，该第一天线层23a设于该绝缘体22的第一表面22a上，且该第二天线层23b位于该绝缘体22的第二表面22b上以接触该承载结构20的第二侧20b并电性连接该第一线路部201，其中，该第一天线层23a的布设位置对应该第二天线层23b的布设位置。
又，可经由溅镀(sputtering)、蒸镀(vaporing)、电镀、无电电镀、化镀或贴膜(foiling)等方式制作厚度轻薄的天线层。例如，于该第一绝缘体22(或该承载结构20)上形成图案化导电材，以作为第一天线层23a或第二天线层23b，并令该导电层240于该承载结构20的布设面积大于该第二天线层23b结合该承载结构20的布设面积。
另外，该第一天线层23a与该第二天线层23b以耦合方式传输讯号。例如，该第一天线层23a与该第二天线层23b可由交变电压、交变电流或辐射变化产生辐射能量，且该辐射能量为电磁场，以令该第一天线层23a与该第二天线层23b能相互电磁耦合，使天线讯号能于该第一天线层23a与该第二天线层23b之间传递。
有关该天线结构2a的实施例繁多，如天线基板堆叠于该第二侧20b上，并不限于上述。
所述的天线框架2b为Sub-6GHz波长型天线，其对应该第二电子元件21b作配置。
在本实施例中，该天线框架2b经由该第二线路部202耦接(如电性连接)该第二电子元件21b，以发射Sub-6GHz波长。
此外，如图2A所示，该天线框架2b可环绕于该第一电子元件21a与第二电子元件21b周围，即该第一电子元件21a与第二电子元件21b位于该天线框架2b内；或者，如图2A’及图2A”所示，该第一电子元件21a与第二电子元件21b的至少其中一者位于该天线框架2b外。
如图2B所示，接续图2A的制程，设置多个导电元件26于该承载结构20的第一侧20a上，以形成电子封装件2，且该电子封装件2可经由该些导电元件26结合于一如电路板9的电子装置上。
在本实施例中，该导电元件26例如为焊球(solder ball)或金属凸块(如铜凸块)，其设于该承载结构20的第一侧20a的外接垫242上，以电性连接该承载结构20。
在后续制程中，如图2C所示，可依需求形成一封装层25于该承载结构20的第一侧20a上，以包覆该天线框架2b、该第一电子元件21a与第二电子元件21b，以获取电子封装件2’的另一种实施例。
在本实施例中，形成该封装层25的材质为高导热性材料，以利于该第一电子元件21a与第二电子元件21b散热同时提供该第一电子元件21a与第二电子元件21b保护，避免发生变形裂损，其中，形成该封装层25的材质例如为聚酰亚胺(polyimide，简称PI)、干膜(dryfilm)、环氧树脂(epoxy)或封装材(molding compound)等，但并不限于上述。
此外，该封装层25可包覆该些导电凸块210；或者，将底胶(图略)形成于该承载结构20的第一侧20a与该第一电子元件21a(及/或第二电子元件21b)之间以包覆该些导电凸块210，再令该封装层25包覆该底胶。
又，在另一实施例中(图未示)，该封装层25也可包覆该导电元件26，且令该导电元件26的端部外露出该封装层25。或者，如图2D所示的电子封装件2”，先形成该封装层25，再于该封装层25中形成开孔250，以令该外接垫242外露于该开孔250，之后将该导电元件26形成于该开孔250中的外接垫242上。
图3A、图3B或图3C为本发明的电子封装件的第二实施例的剖面示意图。本实施例与第一实施例的差异在于电子元件的设置方式，其它制程大致相同，故以下仅说明相异处，而不再赘述相同处。
如图3A、图3B或图3C所示，对应于图2A的制程中，第一电子元件31a与第二电子元件31b以垂直堆叠方式设于该承载结构20的第一侧20a上。
在本实施例中，该第一电子元件31a经由多个如焊锡材料的导电凸块310以覆晶方式设于该第一线路部201上并电性连接该第一线路部201，且该第二电子元件31b堆叠于该第一电子元件31a上并经由多个焊线311以打线方式电性连接该第二线路部202。
在后续制程中，依据如图2B至图2D所示的制程，以获取各种电子封装件3,3’,3”的实施例。
应可理解地，也可将该第二电子元件31b以覆晶方式设于该第二线路部202上并电性连接该第二线路部202，且该第一电子元件31a堆叠于该第二电子元件31b上并经由多个焊线311以打线方式电性连接该第一线路部201。
本发明的制法经由同时整合两种不同天线(该天线结构2a及该天线框架2b)于同一电子封装件2,2’,2”,3,3’,3”中，故相较于现有技术的分别形成两封装结构而设于电路板上，本发明的电子封装件2,2’,2”,3,3’,3”于后续应用的电路板9，其面积无需增加，因而能达到终端产品轻薄短小的需求。
此外，本发明的制法中，利用金属片折叠成立体化天线框架2b，以于制程中，该天线框架2b能与该第一及第二电子元件21a,21b整合制作，也就是一同进行封装，使该封装层25能覆盖该天线框架2b与该第一及第二电子元件21a,21b，故封装制程用的模具能对应该承载结构20的尺寸，因而有利于封装制程。
又，该天线框架2b架设于该承载结构20上而呈立体式天线，因而无需于该承载结构20的第一侧20a表面上增加布设区域，故相较于现有技术，本发明的制法能于预定的承载结构20尺寸下增加天线功能(即Sub-6GHz波长的讯号功能)，因而得以达到具备两种天线运作的需求，且能使该电子封装件2,2’,2”,3,3’,3”符合微小化的需求。
另外，本发明的制法经由该承载结构20的第二侧20b上形成位于该绝缘体22相对两侧的第一天线层23a与第二天线层23b，以形成立体化天线本体23，故于制程中，封装制程用的模具能对应该承载结构20的尺寸，因而有利于封装制程，且无需于该承载结构20的第二侧20b表面上增加布设区域，使本发明的制法能于预定的承载结构20尺寸下制作天线(即毫米波式天线)，进而该电子封装件2,2’,2”,3,3’,3”符合微小化的需求。
另一方面，可利用该导电层240防止该天线结构2a对该第一电子元件21a与第二电子元件21b的串音干扰(cross talking)、噪音干涉(noise interfering)及辐射干扰(radiation interference)等问题。
本发明还提供一种电子封装件2,2’,2”,3,3’,3”，其包括：一承载结构20、第一电子元件21a,31a、第二电子元件21b,31b、天线结构2a、以及天线框架2b。
所述的承载结构20具有相对的第一侧20a与第二侧20b。
所述的天线结构2a设于该承载结构20的第二侧20b上。
所述的天线框架2b设于该承载结构20的第一侧20a上。
所述的第一电子元件21a,31a接置于该承载结构20的第一侧20a上并电性连接该天线结构2a。
所述的第二电子元件21b,31b接置于该承载结构20的第一侧20a上并电性连接该天线框架2b。
在一实施例中，该承载结构20包含有第一线路部201，以电性连接该第一电子元件21a,31a与该天线结构2a。
在一实施例中，该承载结构20包含有第二线路部202，以电性连接该第二电子元件21b,31b与该天线框架2b。
在一实施例中，该天线结构2a包含绝缘体22与天线本体23，该天线本体23包含有相对配置的第一天线层23a与第二天线层23b，且该绝缘体22与该第二天线层23b结合于该承载结构20的第二侧20b上。
在一实施例中，该天线结构2a为毫米波式天线。
在一实施例中，该天线框架2b为Sub-6GHz波长型天线。
在一实施例中，该第一与第二电子元件21a,21b,31a,31b为不同的射频芯片。
在一实施例中，该第一电子元件21a,31a为具发射毫米波功能的半导体芯片。
在一实施例中，该第二电子元件21b,31b为具发射Sub-6GHz波长功能的半导体芯片。
在一实施例中，所述的电子封装件2,2’,2”,3,3’,3”还包括多个导电元件26，其设于该承载结构20的第一侧20a上并电性连接该承载结构20的配线部24。
在一实施例中，所述的电子封装件2’,2”,3’,3”还包括封装层25，其形成于该承载结构20的第一侧20a上并包覆该天线框架2b、第一与第二电子元件21a,21b,31a,31b。进一步，该封装层25具有外露该承载结构20的开孔250，以于该开孔250中形成导电元件26，使该导电元件26电性连接该承载结构20的配线部24。
在一实施例中，该第一电子元件21a与第二电子元件21b间隔排设于该承载结构20的第一侧20a上。
在一实施例中，该第一电子元件31a与第二电子元件31b为相互堆叠。
综上所述，本发明的电子封装件及其制法，经由同时整合两种不同天线(该天线结构及该天线框架)于同一电子封装件中，故本发明的电子封装件于后续应用的电路板，其面积无需增加，即可具备两种波长的传输讯号的功能，因而能达到终端产品轻薄短小的需求。
此外，本发明经由该天线框架的设计，以于制程中，该封装层能覆盖该第一电子元件与第二电子元件及该天线框架，使封装制程的模具能对应该承载结构的尺寸，而有利于封装制程。
又，该天线框架架设于该承载结构上而呈立体式天线，因而无需于该承载结构上增加布设区域，故本发明能于预定的承载结构尺寸下增加天线功能，因而得以达到具备两种天线运作的需求，且能使该电子封装件符合微小化的需求。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (32)

1.一种电子封装件，其特征在于，包括：
承载结构，其具有相对的第一侧与第二侧；
天线结构，其设于该承载结构的第二侧上；
天线框架，其设于该承载结构的第一侧上；
第一电子元件，其接置于该承载结构的第一侧上并耦接该天线结构；以及
第二电子元件，其接置于该承载结构的第一侧上并耦接该天线框架。
2.根据权利要求1所述的电子封装件，其特征在于，该承载结构包含有第一线路部，以电性连接该第一电子元件与该天线结构。
3.根据权利要求1所述的电子封装件，其特征在于，该承载结构包含有第二线路部，以电性连接该第二电子元件与该天线框架。
4.根据权利要求1所述的电子封装件，其特征在于，该天线结构包含绝缘体与天线本体，该天线本体包含有相对配置于该绝缘体两侧的第一天线层与第二天线层，且该绝缘体与该第二天线层结合于该承载结构的第二侧上。
5.根据权利要求1所述的电子封装件，其特征在于，该天线结构为毫米波式天线。
6.根据权利要求1所述的电子封装件，其特征在于，该天线框架为Sub-6GHz波长型天线。
7.根据权利要求1所述的电子封装件，其特征在于，该第一电子元件与第二电子元件为不同的射频芯片。
8.根据权利要求1所述的电子封装件，其特征在于，该第一电子元件为具发射毫米波功能的半导体芯片。
9.根据权利要求1所述的电子封装件，其特征在于，该第二电子元件为具发射Sub-6GHz波长功能的半导体芯片。
10.根据权利要求1所述的电子封装件，其特征在于，该电子封装件还包括多个导电元件，其设于该承载结构的第一侧上。
11.根据权利要求1所述的电子封装件，其特征在于，该电子封装件还包括封装层，其形成于该承载结构的第一侧上并包覆该天线框架、第一电子元件与第二电子元件。
12.根据权利要求11所述的电子封装件，其特征在于，该封装层具有外露该承载结构的开孔，以于该开孔中形成电性连接该承载结构的导电元件。
13.根据权利要求1所述的电子封装件，其特征在于，该第一电子元件与第二电子元件位于该天线框架内。
14.根据权利要求1所述的电子封装件，其特征在于，该第一电子元件与第二电子元件的至少其中一者位于该天线框架外。
15.根据权利要求1所述的电子封装件，其特征在于，该第一电子元件与第二电子元件间隔排设于该承载结构的第一侧上。
16.根据权利要求1所述的电子封装件，其特征在于，该第一电子元件与第二电子元件为相互堆叠。
17.一种电子封装件的制法，其特征在于，包括：
提供一具有相对的第一侧与第二侧的承载结构，且于该承载结构的第一侧上设置第一电子元件与第二电子元件；
于该承载结构的第二侧上设置天线结构，并使该第一电子元件耦接该天线结构；以及
设置天线框架于该承载结构的第一侧上，并使该第二电子元件耦接该天线框架。
18.根据权利要求17所述的电子封装件的制法，其特征在于，该承载结构包含有第一线路部，以电性连接该第一电子元件与该天线结构。
19.根据权利要求17所述的电子封装件的制法，其特征在于，该承载结构包含有第二线路部，以电性连接该第二电子元件与该天线框架。
20.根据权利要求17所述的电子封装件的制法，其特征在于，该天线结构包含绝缘体与天线本体，该天线本体包含有相对配置于该绝缘体两侧的第一天线层与第二天线层，且该绝缘体与该第二天线层结合于该承载结构的第二侧上。
21.根据权利要求17所述的电子封装件的制法，其特征在于，该天线结构为毫米波式天线。
22.根据权利要求17所述的电子封装件的制法，其特征在于，该天线框架为Sub-6GHz波长型天线。
23.根据权利要求17所述的电子封装件的制法，其特征在于，该第一电子元件与第二电子元件为不同的射频芯片。
24.根据权利要求17所述的电子封装件的制法，其特征在于，该第一电子元件为具发射毫米波功能的半导体芯片。
25.根据权利要求17所述的电子封装件的制法，其特征在于，该第二电子元件为具发射Sub-6GHz波长功能的半导体芯片。
26.根据权利要求17所述的电子封装件的制法，其特征在于，该制法还包括形成多个导电元件于该承载结构的第一侧上。
27.根据权利要求17所述的电子封装件的制法，其特征在于，该制法还包括形成封装层于该承载结构的第一侧上，使该封装层包覆该天线框架、第一电子元件与第二电子元件。
28.根据权利要求27所述的电子封装件的制法，其特征在于，该封装层具有外露该承载结构的开孔，以于该开孔中形成电性连接该承载结构的导电元件。
29.根据权利要求17所述的电子封装件的制法，其特征在于，该第一电子元件与第二电子元件位于该天线框架内。
30.根据权利要求17所述的电子封装件的制法，其特征在于，该第一电子元件与第二电子元件的至少其中一者位于该天线框架外。
31.根据权利要求17所述的电子封装件的制法，其特征在于，该第一电子元件与第二电子元件为间隔排设于该承载结构的第一侧上。
32.根据权利要求17所述的电子封装件的制法，其特征在于，该第一电子元件与第二电子元件为相互堆叠。
CN201910058281.9A 2019-01-17 2019-01-22 电子封装件及其制法 Active CN111446535B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW108101822 2019-01-17
TW108101822A TWI698046B (zh) 2019-01-17 2019-01-17 電子封裝件及其製法

Publications (2)

Publication Number Publication Date
CN111446535A true CN111446535A (zh) 2020-07-24
CN111446535B CN111446535B (zh) 2022-04-08

Family

ID=71609088

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910058281.9A Active CN111446535B (zh) 2019-01-17 2019-01-22 电子封装件及其制法

Country Status (3)

Country Link
US (1) US10833394B2 (zh)
CN (1) CN111446535B (zh)
TW (1) TWI698046B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI663701B (zh) * 2017-04-28 2019-06-21 矽品精密工業股份有限公司 電子封裝件及其製法
US11978697B2 (en) * 2021-07-16 2024-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure
US11735830B2 (en) * 2021-08-06 2023-08-22 Advanced Semiconductor Engineering, Inc. Antenna device and method for manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170018513A1 (en) * 2011-07-07 2017-01-19 Samsung Electro-Mechanics Co., Ltd. Semiconductor package including an antenna formed in a groove within a sealing element
WO2018125240A1 (en) * 2016-12-30 2018-07-05 Intel Corporation Microelectronic devices designed with flexible package substrates with distributed stacked antennas for high frequency communication systems
CN108735677A (zh) * 2017-04-25 2018-11-02 矽品精密工业股份有限公司 电子封装件及其制法
CN108807297A (zh) * 2017-04-28 2018-11-13 矽品精密工业股份有限公司 电子封装件及其制法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9153542B2 (en) * 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
US9431369B2 (en) * 2012-12-13 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Antenna apparatus and method
US10622318B2 (en) * 2017-04-26 2020-04-14 Advanced Semiconductor Engineering Korea, Inc. Semiconductor package device and method of manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170018513A1 (en) * 2011-07-07 2017-01-19 Samsung Electro-Mechanics Co., Ltd. Semiconductor package including an antenna formed in a groove within a sealing element
WO2018125240A1 (en) * 2016-12-30 2018-07-05 Intel Corporation Microelectronic devices designed with flexible package substrates with distributed stacked antennas for high frequency communication systems
CN108735677A (zh) * 2017-04-25 2018-11-02 矽品精密工业股份有限公司 电子封装件及其制法
CN108807297A (zh) * 2017-04-28 2018-11-13 矽品精密工业股份有限公司 电子封装件及其制法

Also Published As

Publication number Publication date
US10833394B2 (en) 2020-11-10
TW202029568A (zh) 2020-08-01
TWI698046B (zh) 2020-07-01
US20200235462A1 (en) 2020-07-23
CN111446535B (zh) 2022-04-08

Similar Documents

Publication Publication Date Title
CN106450659B (zh) 电子模块
US11223117B2 (en) Electronic package and electronic device having the electronic package
US11670607B2 (en) Electronic package
CN111799181B (zh) 电子封装件及其制法
TWI700801B (zh) 電子封裝件及其製法
CN111446535B (zh) 电子封装件及其制法
CN115313013A (zh) 天线结构及其电子封装件
CN113539979A (zh) 封装结构及其制法
CN108962878B (zh) 电子封装件及其制法
CN108735677B (zh) 电子封装件及其制法
CN116073133A (zh) 电子装置及其制造方法
US20240145908A1 (en) Electronic package and manufacturing method thereof
TW201947727A (zh) 電子封裝件及其製法
TWI815314B (zh) 電子封裝件及其製法
US12057618B2 (en) Electronic package and fabrication method thereof
CN116246965B (zh) 组合型空气耦合天线封装结构及制备方法
TWI789977B (zh) 電子裝置及其製造方法
CN117558695A (zh) 电子封装件及其制法
CN113517238A (zh) 电子封装件及其制法
CN110896584A (zh) 电子封装件
CN117174669A (zh) 电子封装件及其制法
CN115603030A (zh) 电子装置及其制造方法
CN113540055A (zh) 电子装置及其制法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant