CN111416023A - Method for improving light efficiency by laterally coating high-reflection film on metal electrode - Google Patents
Method for improving light efficiency by laterally coating high-reflection film on metal electrode Download PDFInfo
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- CN111416023A CN111416023A CN201910010353.2A CN201910010353A CN111416023A CN 111416023 A CN111416023 A CN 111416023A CN 201910010353 A CN201910010353 A CN 201910010353A CN 111416023 A CN111416023 A CN 111416023A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0091—Processes for devices with an active region comprising only IV-VI compounds
Abstract
The invention relates to the technical field of L ED, in particular to a method for improving light efficiency by laterally coating a high-reflection film on a metal electrode, which comprises the following steps of 1) MSA, CB L, TC L, PAD, NDBR and PSV, and specifically comprises the following steps of 1) defining the pattern size of a L ED chip on GAN by MSA, 2) CB L depositing a layer of SiO2A current barrier layer, 3) TC L depositing a conductive layer, 4) PAD plating a metal electrode for conducting, 5) NDBR plating a high-reflection DBR layer on the side of the metal electrode, 6) PSV plating a SiO layer2The invention breaks the conventional thought as a chip protective layer, increases the reflection of lateral light on the metal electrode by plating a high-reflection DBR layer on the side surface of the metal electrode so as to further realize the maximization of light efficiency, has simple preparation process, meets the manufacturing requirement of L ED chips, and can be popularized and applied in actual industrial production.
Description
Technical Field
The invention relates to the technical field of L ED, in particular to a method for improving light efficiency by laterally coating a high-reflection film on a metal electrode.
Background
Currently, a third generation light source L ED gradually replaces a traditional light source with specific energy-saving and environment-friendly advantages, the light emitting core of the L ED light source lies in chip manufacturing and light effect extraction, and currently, L ED chip manufacturing in the industry is mainly a chip with a forward mounting structure, namely, light emitted by an epitaxial GAN is emitted from the front of the chip to the maximum extent by utilizing a series of transmission and reflection principles, and absorption of light on the aspects of the back and side walls of the chip is reduced, so that light effect maximization is realized.
At present, the light-emitting efficiency of epitaxy does not reach 100% at the end of a middle-stream chip of the chip, wherein one part of the light-emitting efficiency is shielded by a metal electrode, although an Al layer with a certain thickness is arranged below the metal electrode, the thickness of the metal electrode can be relatively shielded.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a method for improving the luminous efficiency by coating a high-reflection film on the lateral side of a metal electrode.
In order to achieve the purpose, the invention is realized by the following technical scheme:
a method for improving light efficiency by laterally coating a high-reflection film on a metal electrode comprises the following steps of MSA, CB L, TC L, PAD, NDBR and PSV:
1) MSA, L ED chip pattern size is defined on GAN;
2) CB L deposition of a layer of SiO2A current blocking layer;
3) TC L depositing a conductive layer;
4) PAD: plating a metal electrode for conducting operation;
5) NDBR: plating a high-reflection DBR layer on the side surface of the metal electrode;
6) PSV: finally, a layer of SiO is plated2As chip protection layer.
Preferably, the highly reflective DBR layer in step 5) is made of SiO2And Ti3O5And the thickness of the high-reflection DBR layer is 3.0-6.0 um.
Preferably, the thickness of the highly reflective DBR layer is 3.5 um.
Preferably, SiO in the high-reflection DBR layer2With Ti3O5The thickness ratio of (1): 1.
preferably, the metal electrode in step 4) is any one of a gold electrode, a silver electrode or a copper electrode.
Preferably, the conductive layer in step 3) is an indium tin oxide deposition layer.
Has the advantages that:
the invention breaks through the conventional thought, increases the reflection of lateral light on the metal electrode by plating a high-reflection DBR layer on the side surface of the metal electrode, further realizes the maximization of the light efficiency, has simple preparation process, meets the manufacturing requirement of L ED chips, and can be popularized and applied in the actual industrial production.
Drawings
FIG. 1 is a schematic structural diagram of an L ED chip prepared according to the present invention;
FIG. 2 is a schematic diagram of the structure of L ED chip prepared by the prior art;
FIG. 3 is a comparison graph of the brightness of L ED chips manufactured by the present invention and the prior art under different conditions;
fig. 4 is a voltage comparison graph of L ED chips manufactured by the technical solution of the present invention and the prior art under different conditions.
1, P-PAD, 2, PSV, 3, TC L, 4, CB L, 5, P-GAN, 6, MQW, 7, N-GAN, 8, substrate, 9, pressing plate, 10, DBR, 11, high reflection DBR layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1:
a method for improving light efficiency by laterally coating a high-reflection film on a metal electrode is characterized in that the process flow of the method comprises MSA, CB L, TC L, PAD, NDBR and PSV, and the method comprises the following specific steps:
1) MSA, L ED chip pattern size is defined on GAN;
2) CB L deposition of a layer of SiO2A current blocking layer;
3) TC L depositing a conductive layer;
4) PAD: plating a metal electrode for conducting operation;
5) NDBR: plating a high-reflection DBR layer on the side surface of the metal electrode;
6) PSV: finally, a layer of SiO is plated2As chip protection layer.
Step 5) the high reflectivity DBR layer is made of SiO2And Ti3O5And the high-reflection DBR layer is 3.5um in thickness.
SiO in high reflection DBR layer2With Ti3O5The thickness ratio of (1): 1.
and 4), selecting any one of a gold electrode, a silver electrode or a copper electrode as the metal electrode in the step 4).
The conducting layer in the step 3) is an indium tin oxide deposition layer.
Example 2:
a method for improving light efficiency by laterally coating a high-reflection film on a metal electrode is characterized in that the process flow of the method comprises MSA, CB L, TC L, PAD, NDBR and PSV, and the method comprises the following specific steps:
1) MSA, L ED chip pattern size is defined on GAN;
2) CB L deposition of a layer of SiO2A current blocking layer;
3) TC L depositing a conductive layer;
4) PAD: plating a metal electrode for conducting operation;
5) NDBR: plating a high-reflection DBR layer on the side surface of the metal electrode;
6)PSV: finally, a layer of SiO is plated2As chip protection layer.
Step 5) the high reflectivity DBR layer is made of SiO2And Ti3O5And the high-reflection DBR layer is 6.0um in thickness.
SiO in high reflection DBR layer2With Ti3O5The thickness ratio of (1): 1.
and 4), selecting any one of a gold electrode, a silver electrode or a copper electrode as the metal electrode in the step 4).
The conducting layer in the step 3) is an indium tin oxide deposition layer.
Example 3:
a method for improving light efficiency by laterally coating a high-reflection film on a metal electrode is characterized in that the process flow of the method comprises MSA, CB L, TC L, PAD, NDBR and PSV, and the method comprises the following specific steps:
1) MSA, L ED chip pattern size is defined on GAN;
2) CB L deposition of a layer of SiO2A current blocking layer;
3) TC L depositing a conductive layer;
4) PAD: plating a metal electrode for conducting operation;
5) NDBR: plating a high-reflection DBR layer on the side surface of the metal electrode;
6) PSV: finally, a layer of SiO is plated2As chip protection layer.
Step 5) the high reflectivity DBR layer is made of SiO2And Ti3O5And the high-reflection DBR layer is 3.0um in thickness.
SiO in high reflection DBR layer2With Ti3O5The thickness ratio of (1): 1.
and 4), selecting any one of a gold electrode, a silver electrode or a copper electrode as the metal electrode in the step 4).
The conducting layer in the step 3) is an indium tin oxide deposition layer.
Example 4:
a method for improving light efficiency by laterally coating a high-reflection film on a metal electrode is characterized in that the process flow of the method comprises MSA, CB L, TC L, PAD, NDBR and PSV, and the method comprises the following specific steps:
1) MSA, L ED chip pattern size is defined on GAN;
2) CB L deposition of a layer of SiO2A current blocking layer;
3) TC L depositing a conductive layer;
4) PAD: plating a metal electrode for conducting operation;
5) NDBR: plating a high-reflection DBR layer on the side surface of the metal electrode;
6) PSV: finally, a layer of SiO is plated2As chip protection layer.
Step 5) the high reflectivity DBR layer is made of SiO2And Ti3O5And the high-reflection DBR layer is 5.0um in thickness.
SiO in high reflection DBR layer2With Ti3O5The thickness ratio of (1): 1.
and 4), selecting any one of a gold electrode, a silver electrode or a copper electrode as the metal electrode in the step 4).
The conducting layer in the step 3) is an indium tin oxide deposition layer.
Performance testing
Under the condition of K070491, an L ED chip prepared by the technical scheme in the example 1 is marked as K070491_06GV, and a L ED chip prepared by the prior technical scheme is marked as K070491_08 GV.
Under the condition of K220276, L ED chips prepared by the technical scheme in the example 2 are respectively marked as K220276_29ZV and K220276_31ZV, and L ED chips prepared by the technical scheme are respectively marked as K220276_24ZV and K220276_30 ZV.
Under the condition of K390106, L ED chips prepared by the technical scheme in example 3 are marked as K390106_02GA, and L ED chips prepared by the technical scheme are marked as K220276_01 GA.
Under the condition of K400099, the L ED chip prepared by the technical scheme in example 3 was designated as K400099_26GA, and the L ED chip prepared by the technical scheme was designated as K400099_24 GA.
The voltage and brightness measurements were performed on the L ED chips thus obtained, and the results are shown in FIGS. 3 and 4.
Wherein, POR is the prior art scheme (the process flow of the prior art scheme is MSA → CB L → TC L → PAD → PSV), and experiment is the technical scheme of the invention.
Under different conditions, the average values of the voltage and the brightness of the L ED chip prepared by the technical scheme of the invention and the L ED chip prepared by the prior technical scheme are as follows:
the test result shows that: after the chip is manufactured by the technical scheme, the tested VF has no difference, and the average brightness is higher than that of the prior art by about 1.2 percent.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (6)
1. A method for improving light efficiency by laterally coating a high-reflection film on a metal electrode is characterized in that the process flow of the method comprises MSA, CB L, TC L, PAD, NDBR and PSV, and the method comprises the following specific steps:
1) MSA, L ED chip pattern size is defined on GAN;
2) CB L deposition of a layer of SiO2A current blocking layer;
3) TC L depositing a conductive layer;
4) PAD: plating a metal electrode for conducting operation;
5) NDBR: plating a high-reflection DBR layer on the side surface of the metal electrode;
6) PSV: finally, a layer of SiO is plated2As chip protection layer.
2. The method of claim 1, wherein the metal electrode is coated with a high reflective film to improve the light efficiency, further comprising: the high reflection DBR layer in the step 5) is made of SiO2And Ti3O5And the thickness of the high-reflection DBR layer is 3.0-6.0 um.
3. The method of claim 2, wherein the metal electrode is coated with a high reflective film to improve the light efficiency, further comprising: the thickness of the high reflection DBR layer is 3.5 um.
4. A method as claimed in claim 2 or 3, wherein the metal electrode is coated with a high reflective film laterally to improve the light efficiency, the method comprising: SiO in the high-reflection DBR layer2With Ti3O5The thickness ratio of (1): 1.
5. the method of claim 1, wherein the metal electrode is coated with a high reflective film to improve the light efficiency, further comprising: in the step 4), the metal electrode is any one of a gold electrode, a silver electrode or a copper electrode.
6. The method of claim 1, wherein the metal electrode is coated with a high reflective film to improve the light efficiency, further comprising: in the step 3), the conducting layer is an indium tin oxide deposition layer.
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Citations (5)
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JP2000031540A (en) * | 1999-06-18 | 2000-01-28 | Toyoda Gosei Co Ltd | Manufacture of gallium nitride based compound semiconductor light emitting element |
US20060081858A1 (en) * | 2004-10-14 | 2006-04-20 | Chung-Hsiang Lin | Light emitting device with omnidirectional reflectors |
CN101872823A (en) * | 2010-06-07 | 2010-10-27 | 厦门市三安光电科技有限公司 | Gallium nitride-based light-emitting diode (LED) with distributed Bragg reflectors on side walls and preparation method thereof |
CN104112801A (en) * | 2010-03-10 | 2014-10-22 | Lg伊诺特有限公司 | Light emitting device |
CN108336200A (en) * | 2018-03-27 | 2018-07-27 | 湘能华磊光电股份有限公司 | LED chip structure and preparation method thereof |
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- 2019-01-07 CN CN201910010353.2A patent/CN111416023A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000031540A (en) * | 1999-06-18 | 2000-01-28 | Toyoda Gosei Co Ltd | Manufacture of gallium nitride based compound semiconductor light emitting element |
US20060081858A1 (en) * | 2004-10-14 | 2006-04-20 | Chung-Hsiang Lin | Light emitting device with omnidirectional reflectors |
CN104112801A (en) * | 2010-03-10 | 2014-10-22 | Lg伊诺特有限公司 | Light emitting device |
CN101872823A (en) * | 2010-06-07 | 2010-10-27 | 厦门市三安光电科技有限公司 | Gallium nitride-based light-emitting diode (LED) with distributed Bragg reflectors on side walls and preparation method thereof |
CN108336200A (en) * | 2018-03-27 | 2018-07-27 | 湘能华磊光电股份有限公司 | LED chip structure and preparation method thereof |
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Application publication date: 20200714 |