CN111403472A - 沟槽栅极沟槽场板垂直mosfet - Google Patents

沟槽栅极沟槽场板垂直mosfet Download PDF

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CN111403472A
CN111403472A CN202010222697.2A CN202010222697A CN111403472A CN 111403472 A CN111403472 A CN 111403472A CN 202010222697 A CN202010222697 A CN 202010222697A CN 111403472 A CN111403472 A CN 111403472A
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trench
region
closed boundary
gate dielectric
vertical drain
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CN111403472B (zh
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M·丹尼森
S·彭德哈卡尔
G·马图尔
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Texas Instruments Inc
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Texas Instruments Inc
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    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

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Abstract

本申请公开沟槽栅极沟槽场板垂直MOSFET。在所描述的示例中，一种具有垂直漏极延伸MOS晶体管(110)的半导体器件(100)可以通过形成深沟槽结构(104)以定义晶体管(110)的至少一个垂直漂移区(108)而形成，使得每个垂直漂移区(108)在至少两个对侧上被深沟槽结构(104)限制。深沟槽结构(104)被间隔开以形成漂移区(108)的RESURF区域。沟槽栅极(114)被形成在衬底(102)中的沟槽内并位于垂直漂移区(108)上方。本体区(118)位于衬底(102)内并在垂直偏移区(108)上方。

Description

沟槽栅极沟槽场板垂直MOSFET
本申请是国际申请日为2014年09月26日、进入国家阶段日为2016年06月01日的名称为“沟槽栅极沟槽场板垂直MOSFET”的中国专利申请201480065666.3(PCT/US2014/057766)的分案申请。
技术领域
本发明总体涉及半导体器件，并且特别涉及半导体器件中的漏极延伸晶体管。
背景技术
一种延伸漏极金属氧化物半导体(MOS)晶体管的特征可以是导通状态下的晶体管的电阻、晶体管在含有该晶体管的衬底的顶表面处占用的横向面积以及在晶体管的漏极节点与源极节点之间限制晶体管的最大工作电势的击穿电势。可能期望针对导通状态电阻和击穿电势的给定值而减小晶体管的面积。减小面积的一种技术是在垂直方向上在延伸漏极中配置漂移区，使得漂移区中的漏极电流垂直于衬底的顶表面流动。利用平面处理工艺将垂直定向漂移区集成在半导体器件中而同时维持期望的加工成本和复杂度可能是有问题的。
发明内容
在所描述的示例中，一种具有垂直漏极延伸MOS晶体管的半导体器件可以通过形成深沟槽结构以定义晶体管的至少一个垂直漂移区而形成，使得每个垂直漂移区在至少两个对侧上被深沟槽结构限制。深沟槽结构被间隔开以形成漂移区的RESURF区域。沟槽栅极被形成在衬底中的沟槽内并位于垂直漂移区上方。本体区(body region)位于衬底内并在垂直漂移区上方。
附图说明
图1是具有垂直漏极延伸MOS晶体管的半导体器件的剖面图。
图2A至图2H是图1的半导体器件在连续加工阶段中的剖面图。
图3是具有垂直漏极延伸MOS晶体管的半导体器件的剖面图。
图4是具有垂直漏极延伸MOS晶体管的半导体器件的剖面图。
图5是具有垂直漏极延伸MOS晶体管的半导体器件的剖面图。
图6是具有垂直漏极延伸MOS晶体管的半导体器件的剖面图。
图7是具有垂直漏极延伸MOS晶体管的半导体器件的剖面图。
图8和图9是设置在沟槽中的沟槽栅极的不同配置的剖面图。
图10至图12是具有垂直漏极延伸MOS晶体管的半导体器件的俯视图。
具体实施方式
通过引用将以下共同待决的专利申请合并到本专利申请中：美国申请号US14/044,909号和美国申请号US 14/044,926。
在至少一个示例中，半导体器件可以是包含垂直漏极延伸MOS晶体管和其他晶体管的集成电路。在另一个示例中，半导体器件可以是分立元件，其中垂直漏极延伸MOS晶体管是仅有的晶体管。垂直漏极接触区可以被设置在深沟槽结构的相邻部分之间。
出于本说明书的目的，术语“RESURF”指的是降低相邻半导体区域中的电场的材料。例如，RESURF区可以是这样一种半导体区域，其具有与相邻半导体区域相反的导电类型。RESURF结构在Appels等人的“Thin Layer High VoltageDevices”,Philips J,Res.351-13,1980中有所描述。
在本公开中所描述的示例描述了n沟道器件。对应的p沟道器件可以通过适当地改变掺杂极性而形成。图1是具有垂直漏极延伸MOS晶体管的半导体器件的剖视图。半导体器件100被形成于p型半导体衬底102之中和之上。垂直漏极延伸MOS晶体管110包含被设置在衬底102中以定义至少一个n型垂直漏极接触区106的多个深沟槽结构104以及由深沟槽结构104的实例分离的多个相邻n型垂直定向漂移区108。至少一个垂直漏极接触区106和垂直定向漂移区108与设置在衬底102中的n型掩埋层112接触。深沟槽结构104在深度上都是基本相等的。
沟槽栅极114和对应的栅极介电层116被设置在垂直定向漂移区108中的沟槽内，使得垂直定向漂移区108的顶部部分接触栅极介电层116的底部部分。如图1所示，沟槽栅极114可以横跨垂直定向漂移区108延伸并且在垂直定向漂移区108的相对侧面上邻接深沟槽结构104。至少一个p型本体区118被设置在垂直定向漂移区108上方的衬底102中并且与栅极介电层116接触。与至少一个p型本体区118和栅极介电层116接触的n型源区120被设置在衬底102中。与至少一个p型本体区118接触的可选p型本体接触区122可以被设置在衬底102中。沟槽栅极114的顶表面与衬底102的顶表面基本相平；这可以通过利用例如化学机械抛光(CMP)工艺来实现。沟槽栅极的其他配置可以被用在具有如图1所示的深沟槽结构104、垂直漏极接触区106和垂直定向漂移区108的配置的垂直漏极延伸MOS晶体管110中。
深沟槽结构104的深度为1至5微米并且宽度为0.5至1.5微米。例如，2.5微米深的深沟槽结构104可以为垂直漏极延伸MOS晶体管110提供30伏特工作电压。4微米深的深沟槽结构104可以为垂直漏极延伸MOS晶体管110提供50伏特工作电压。深沟槽结构104具有介电衬层124并且可以具有可选的导电中心构件126。与垂直定向漂移区108邻接的深沟槽结构104的实例隔开0.5至2微米，以便为垂直定向漂移区108提供RESURF区。与垂直漏极接触区106邻接的深沟槽结构104的实例可以间隔开例如0.5至2.5微米。在垂直漏极延伸MOS晶体管110的操作过程中，导电中心构件126(如果有的话)可以被电偏置以降低垂直定向漂移区108的峰值电场。例如，导电中心构件126可以被连接到源区120、连接到沟槽栅极114或者连接到具有期望电势的偏压源。
图2A至图2H是图1的半导体器件在连续加工阶段中的剖面图。参考图2A，一种n型掩埋层注入区128被形成在衬底102内为图1的n型掩埋层112定义的区域内，例如使用掩模在30keV到100keV的电压下以1×l015cm-2到5×l015cm-2的剂量注入锑。
参考图2B，执行热驱动操作和p型外延生长操作，其扩散并激活在掩埋层注入区128中已注入的n型掺杂物以形成n型掩埋层112并在n型掩埋层112上方形成衬底102的p型外延层130。例如，外延层130可以是3至6微米厚。
参考图2C，通过在衬底中刻蚀深隔离沟槽、形成介电衬层124并且随后可选地形成导电中心构件126来形成深沟槽结构104。深隔离沟槽可以通过例如表述为在衬底102的顶表面上方形成一层硬掩模材料的工艺来形成。可以通过利用光刻法形成刻蚀掩模且随后利用反应离子刻蚀(RIE)工艺移除在为深隔离沟槽定义的区域上方的硬掩模材料来形成硬掩模。在将硬掩模图案化之后，使用各向异性刻蚀工艺(例如Bosch深反应离子刻蚀工艺或者连续深反应离子刻蚀工艺)将深隔离沟槽中的材料从衬底102上移除。
例如，介电衬层124可以包括热生长的二氧化硅。介电衬层124也可以包括由化学气相沉积(CVD)工艺形成的一层或多层介电材料，例如二氧化硅、氮化硅和/或氮氧化硅。如果垂直漏极延伸MOS晶体管110中包括导电中心构件126，则该导电中心构件126被形成在介电衬层124上。例如，导电中心构件126可以包括多晶体硅(通常被称为多晶硅)，其通过在580℃至650℃的温度下在低压反应器中热分解SiH4气体而形成。该多晶硅可以在形成过程中被掺杂以提供期望的电阻。被填充的深隔离沟槽形成深沟槽结构104。来自介电衬层124的形成过程且位于衬底102的顶表面上方的多余介电材料和来自导电中心构件126的形成过程且位于衬底102的顶表面上方的多余导电材料可以被去除，例如通过使用回蚀和/或化学机械抛光(CMP)工艺。
参考图2D，执行漏极接触离子注入工艺，其将n型掺杂物例如磷注入到图1中为垂直漏极接触区106定义的区域中的衬底102内，以形成漏极接触注入区132。例如，漏极接触离子注入工艺的剂量可以是l×l016cm-2至3×l016cm-2。
参考图2E，执行漂移区离子注入工艺，其将n型掺杂物例如磷注入到图1中为垂直定向漂移区108定义的区域之中或上方的衬底102内，以形成漂移注入区134。例如，漂移区离子注入工艺的剂量可以是l×l012cm-2至1×l013cm-2。在该实施例的至少一个版本中，如图2E所示，通过形成遮挡为深沟槽结构104定义的区域以外的衬底102的漂移区注入掩模，漂移注入区134可以被限制在与垂直定向漂移区108邻接的深沟槽结构104的实例之间的衬底区域。在替代版本中，有可能通过将漂移区离子注入工艺执行为均厚(blanket)注入工艺，使得漂移注入区134可以延伸到图1中为垂直漏极接触区106定义的衬底区域内。漏极接触离子注入工艺的剂量至少是漂移区离子注入剂量的十倍高。
参考图2F，执行热驱动操作，其加热衬底102以激活并扩散在漂移注入区134和漏极接触注入区132中注入的掺杂物，并由此分别形成垂直定向漂移区108和垂直漏极接触区106。热驱动操作的条件取决于深沟槽结构104的深度以及位于深沟槽结构104的底部的垂直漏极接触区106的期望横向范围。例如，具有2.5微米深的深沟槽结构104的垂直漏极延伸MOS晶体管110可以具有在1100℃下对衬底102加热3.5到4小时的热驱动操作，或者同等退火条件，例如在1125℃下加热2小时或者在1050℃下加热12小时。
参考图2G，在垂直定向漂移区108上方形成至少一个p型本体区118。本体区118可以例如通过在衬底102的顶表面上方形成光刻胶注入掩模并且将p型掺杂物例如硼以l×l013cm-2至5×l013cm-2的剂量注入到垂直定向漂移区108内来形成。随后可以通过退火工艺来激活所注入的p型掺杂物，例如在快速热处理器(RTP)工具中以1000℃加热60秒，或者同等退火条件，例如以1025℃加热30秒或者以975℃加热100秒。可替代地，可以执行均厚本体注入，其将p型本体掺杂物注入到衬底102内(包括垂直定向漂移区108和深沟槽结构104)。
参考图2H，沟槽栅极114和栅极介电层116被形成在垂直定向漂移区108上方的衬底102中的栅极沟槽内，使得栅极介电层116邻接本体区118。栅极沟槽可以通过以下步骤形成：在衬底102上方形成硬掩模层并利用光刻胶刻蚀掩模来将硬掩模层图案化，并且刻蚀硬掩模层以形成栅极沟槽硬掩模。然后可以利用定时RIE工艺来刻蚀栅极沟槽。随后的湿法清洁操作例如稀氟氢酸清洁可以从栅极沟槽去除由RIE工艺产生的多余残渣。
栅极介电层116被形成在栅极沟槽的侧面和底部上。栅极介电层116可以是一层或多层二氧化硅、氮氧化硅、氧化铝、氮氧化铝、氧化铪、硅酸铪、氮氧化硅铪、氧化锆、硅酸锆、氮氧化硅锆、上述材料的组合或其他绝缘材料。栅极介电层116可能包括氮，这是暴露于50℃至800℃的温度下的含氮等离子体或含氮环境气体所导致的。可以通过多种栅极介电形成工艺中的任何一种来形成栅极介电层116，例如热氧化、氧化层的等离子体氮化和/或通过原子层沉积(ALD)实现的介电材料沉积。栅极介电层116的厚度可以是针对垂直漏极延伸MOS晶体管110上的每伏特栅-源偏压2.5至3.3纳米。例如，在沟槽栅极114相对于源区120具有30伏特电压的情况下，工作的垂直漏极延伸MOS晶体管的实例可以具有厚度为75至100纳米的栅极介电层116。
然后，在栅极介电层116上形成沟槽栅极114，例如，通过在栅极介电层116上的栅极沟槽中且在衬底102上方一致地形成一层多晶硅，然后从栅极沟槽以外的区域去除多余的多晶硅。可以使用其他栅极材料，包括全硅化物多晶硅、置换金属例如氮化钛。在该示例的替代版本中，本体区118可以在刻蚀栅极沟槽并形成沟槽栅极114之后形成。
图3是具有垂直漏极延伸MOS晶体管的半导体器件的剖面图。如参考图2A所描述，半导体器件300可以被形成在p型半导体衬底302之中和之上。可能如参考图2A和图2B所描述，n型掩埋层312被形成在衬底302中。可替代地，n型掩埋层312可以通过均厚n型外延工艺且随后进行p型外延工艺来形成，从而在半导体器件300中的任何地方都产生n型掩埋层。在该示例的另一个版本中，衬底302可以是具有p型外延层的n型晶片，该p型外延层被形成在n型晶片的顶表面上。
如参考图2C所描述，随后形成多个深沟槽结构304。然后形成多个相邻的n型垂直定向漂移区308，其被参考图1描述的深沟槽结构304的实例分离。沟槽栅极314和相应的栅极介电层316被形成在垂直定向漂移区308中的沟槽内，使得垂直定向漂移区308的顶部部分接触栅极介电层316的底部部分。至少一个p型本体区318被设置在垂直定向漂移区308上方的衬底302中并且接触栅极介电层316。n型源区320被设置在衬底302内与至少一个p型本体区318和栅极介电层316接触。可选的p型本体接触区322可以被设置在衬底302内与至少一个p型本体区318接触。
在该示例的至少一个版本中，可以从衬底302的底部部分去除材料以提供如图3所示的减薄衬底(例如50至250微米厚)，其中n型掩埋层312延伸至减薄衬底302的底表面。在另一个版本中，衬底302可以大体保持初始厚度。
漏极接触金属层336被形成在衬底302的底表面上。由此形成的垂直漏极延伸MOS晶体管310具有垂直配置，其中漏极连接在晶体管310的底部实现并且源极连接在晶体管310的顶部实现，这与顶侧漏极连接配置相比有利地提供了更高的漏极电流容量。
图4是具有垂直漏极延伸MOS晶体管的半导体器件的剖面图。如参考图2A所描述，半导体器件400被形成在p型半导体衬底402之中和之上。如参考图2A和图2B所描述，深沟槽结构404被设置在衬底402中以定义垂直漏极延伸MOS晶体管410的多个垂直漏极接触区406和多个垂直定向漂移区408。垂直漏极接触区406在至少两个对侧上被深沟槽结构404限制。如图4所示，每一个垂直定向漂移区408与至少一个深沟槽结构404相邻。在该示例的另一个版本中，每一个垂直定向漂移区408可以与深沟槽结构404的两个实例相邻。垂直漏极接触区406在深沟槽结构404下方延伸并且与相邻的垂直定向漂移区408接触。在该示例中，垂直漏极延伸MOS晶体管410不包含在垂直定向漂移区408下面延伸的n型掩埋层，这可以有利地简化半导体器件400的加工。
沟槽栅极414和相应的栅极介电层416被设置在垂直定向漂移区408中的沟槽内，使得垂直定向漂移区408的顶部部分接触栅极介电层416的底部部分。如图4所示，沟槽栅极414可以被限制在垂直定向漂移区408的中心部分。至少一个p型本体区418被设置在垂直定向漂移区408上方的衬底402中并接触栅极介电层416。n型源区420被设置在衬底402中与至少一个p型本体区418和栅极介电层416接触。可选的p型本体接触区422可以被设置在衬底402内与至少一个p型本体区418接触。沟槽栅极的其他配置可以被用在图4的垂直漏极延伸MOS晶体管410中。
图5是具有垂直漏极延伸MOS晶体管的半导体器件的剖面图。如参考图2A所描述，半导体器件500被形成在p型半导体衬底502之中和之上。如参考图2A和图2B所描述，深沟槽结构504被设置在衬底502中以定义垂直漏极延伸MOS晶体管510的至少一个垂直漏极接触区506和至少一个垂直定向漂移区508。垂直漏极接触区506在至少两个对侧上被深沟槽结构504限制。可选地，n型掩埋层可以被设置在衬底502中并且在垂直定向漂移区508下面延伸。
沟槽栅极514和相应的栅极介电层516被设置在垂直定向漂移区508中的沟槽内。如图5所示，沟槽栅极514可以被限定在垂直定向漂移区508的中心部分。至少一个p型本体区518被设置在垂直定向漂移区508上方的衬底502中并且与栅极介电层516接触。n型源区520被设置在衬底502中与至少一个p型本体区518和栅极介电层516接触。可选的p型本体接触区522可以被设置在衬底502中与至少一个p型本体区518接触。
在该示例中，垂直定向漂移区508位于栅极介电层516下方并且不与栅极介电层516直接接触。n型漂移区链路538被设置在栅极介电层516之下、与栅极介电层516接触并且向下延伸至垂直定向漂移区508并与垂直定向漂移区508接触。在垂直漏极延伸MOS晶体管510的操作过程中，漂移区链路538在垂直漏极接触区506与本体区518中的沟道之间提供一部分电连接。漂移区链路538可以例如在栅极沟槽被刻蚀之后且在栅极材料被形成在栅极沟槽中之前通过向衬底502中离子注入n型掺杂物而形成。在生产加工过程中图5的配置可以有利地提供垂直漏极延伸MOS晶体管510的更加可重复的栅极长度，因为栅极长度由栅极沟槽的深度和源区520的深度确定。因此，本体区518的深度变化不会引起栅极长度的明显变化。沟槽栅极的其他配置可以被用于图5的垂直漏极延伸MOS晶体管510。
图6是具有垂直漏极延伸MOS晶体管的半导体器件的剖面图。如参考图2A所描述，半导体器件600被形成在p型半导体衬底602之中和之上。如参考图2A和图2B所描述，深沟槽结构604被设置在衬底602中以定义垂直漏极延伸MOS晶体管610的至少一个垂直漏极接触区606和至少一个垂直定向漂移区608。垂直漏极接触区606在至少两个对侧上被深沟槽结构604限制。垂直漏极接触区606在深沟槽结构604下方延伸。可选地，n型掩埋层612可以被设置在衬底602中并且在垂直定向漂移区608下面延伸；垂直漏极接触区606与n型掩埋层612接触以便为垂直定向漂移区608提供漏极连接。可替代地，如参考图4所描述，每一个垂直定向漂移区608可以与至少一个深沟槽结构604相邻，从而消除对n型掩埋层612的需求。
长沟槽栅极614和相应的栅极介电层616被设置在垂直定向漂移区608中的长沟槽内，使得垂直定向漂移区608的顶部部分接触栅极介电层616的底部部分。如图6所示，长沟槽栅极616被限定到垂直定向漂移区608的中心部分。至少一个p型本体区618被设置在垂直定向漂移区608上方的衬底602中并接触栅极介电层616。n型源区620被设置在衬底602中与至少一个p型本体区618和栅极介电层616接触。长沟槽栅极614可以有利地为垂直漏极延伸MOS晶体管610提供比电阻率(specific resistivity)的期望值，即导通状态的电阻与晶体管面积的乘积。
图7是具有垂直漏极延伸MOS晶体管的半导体器件的剖面图。如参考图2A所描述，半导体器件700被形成在p型半导体衬底702之中和之上。如参考图2A和2B所描述，深沟槽结构704被设置在衬底702中以定义垂直漏极延伸MOS晶体管710的至少一个垂直漏极接触区706和至少一个垂直定向漂移区708。垂直漏极接触区706在至少两个对侧上被深沟槽结构704限制。垂直漏极接触区706在深沟槽结构704下方延伸。可选地，n型掩埋层712可以被设置在衬底702中并在垂直定向漂移区708下方延伸；垂直漏极接触区706接触n型掩埋层712以提供漏极连接至垂直定向漂移区708。可替代地，如参考图4所描述，每一个垂直定向漂移区708可以与至少一个深沟槽结构704相邻，从而消除对n型掩埋层712的需求。
沟槽栅极714和相应的栅极介电层716被设置在垂直定向漂移区708中的沟槽内，使得垂直定向漂移区708的顶部部分接触栅极介电层716的底部部分。沟槽栅极714部分地横跨垂直定向漂移区708延伸并且完全在垂直定向漂移区708的一侧上邻接深沟槽结构704。至少一个p型本体区718被设置在垂直定向漂移区708上方的衬底702中并且接触栅极介电层716。n型源区720被设置在衬底702中接触至少一个p型本体区718和栅极介电层716。可选的p型本体接触区722可以被设置在衬底702中接触至少一个p型本体区718。沟槽栅极714可以是如图7所示的短沟槽栅极，或者可以是与参考图6所描述的长沟槽栅极相似的长沟槽栅极。完全在垂直定向漂移区708的一侧上形成邻接深沟槽结构704的沟槽栅极可以提供垂直漏极延伸MOS晶体管710的工作电压与比电阻率之间的期望平衡。
图8和图9是设置在沟槽中的沟槽栅极的不同配置的剖面图。参考图8，沟槽栅极814和栅极介电层816被形成在衬底802中的栅极沟槽内。栅极介电层816和沟槽栅极814与衬底802的顶表面交叠，例如交叠500纳米，这可以简化沟槽栅极814的加工。沟槽栅极814可以通过RIE工艺利用由光刻法定义的刻蚀掩模来形成。栅极介电层816和沟槽栅极814可以与平面MOS晶体管844的晶体管栅极介电层840和晶体管栅极842同时形成。
参考图9，沟槽栅极914和栅极介电层916被形成在衬底902中的栅极沟槽内。沟槽栅极914在衬底902的顶表面上方延伸但与其并不重叠。这可以通过利用RIE工艺使用由光刻法定义的刻蚀掩模来图案化沟槽栅极914且随后进行各向同性回蚀工艺来实现。沟槽栅极914配置可以有利地减少沟槽栅极914与衬底902之间的不需要的电容量而不需要CMP工艺。栅极介电层916和沟槽栅极914可以与平面MOS晶体管944的晶体管栅极介电层940和晶体管栅极942同时形成。
图10至图12是具有垂直漏极延伸MOS晶体管的半导体器件的俯视图。图10至图12中示出的沟槽栅极被限定在参考图4所讨论的垂直定向漂移区的中心部分，但栅极的其他配置也可以用于这些示例。参考图10，半导体器件1000被形成在半导体衬底1002之中和之上，如参考图2A所描述。深沟槽结构1004包围多个相邻的垂直漂移区1008。每一个垂直漂移区1008包括至少一个栅极1014和栅极介电层1016。垂直漏极接触区1006围绕多个相邻的垂直漂移区1008。垂直漂移区1008和围绕的垂直漏极接触区1006是n型的；n型区在多个相邻的垂直漂移区1008下方延伸以提供电连接至围绕的垂直漏极接触区1006。深沟槽结构1004的另一个实例横向围绕垂直漏极延伸MOS晶体管1010。至垂直漏极接触区1006的电连接在衬底1002的顶表面处制成。将垂直漂移区1008配置为彼此相邻可以有利地减少垂直漏极延伸MOS晶体管1010的所需面积，从而降低半导体器件1000的加工成本。
参考图11，半导体器件1100被形成在半导体衬底1102之中和之上，如参考图2A所描述。具有线性配置的多个深沟槽结构1104被设置在衬底内，同时垂直漂移区1108被设置在相邻的多对线性深沟槽结构1104之间，使得每一对相邻的垂直漂移区1108完全被一个深沟槽结构1104分离。每一个垂直漂移区1108包括至少一个栅极1114和栅极介电层116。具有线性配置的垂直漏极接触区1106的实例围绕垂直漂移区1108；每一个垂直漏极接触区1106通过线性深沟槽结构1104与垂直漂移区1108分离。垂直漂移区1108和围绕的垂直漏极接触区1106是n型的；n型区在多个垂直漂移区1108下方延伸以提供电连接至围绕的垂直漏极接触区1106。深沟槽结构1104的另一个实例横向围绕垂直漏极延伸MOS晶体管1110。至垂直漏极接触区1106的电连接在衬底1102的顶表面处制成。将垂直漂移区1108配置成彼此相邻可以有利地减少垂直漏极延伸MOS晶体管1110的所需面积，从而降低半导体器件1100的加工成本。将所有深沟槽结构1104配置为不含T形分支可以合乎期望地简化半导体器件1100的加工工艺，从而有利地进一步降低加工成本。
参考图12，半导体器件1200被形成在半导体衬底1202之中和之上，如参考图2A所描述。具有线性配置的多个深沟槽结构1204被设置在衬底中，同时垂直漂移区1208被设置在相邻的多对线性深沟槽结构1204之间，使得相邻的每一对垂直漂移区1208完全被一个深沟槽结构1204分离。每一个垂直漂移区1208包括至少一个栅极1214和栅极介电层1216。具有平行于垂直漂移区1208的线性配置的垂直漏极接触区1206的实例被设置成靠近垂直漂移区1208的第一个实例和最后一个实例。这两个垂直漏极接触区1206被设置在深沟槽结构1204的两个平行线性实例之间。垂直漂移区1208和周围的垂直漏极接触区1206是n型的；n型区在多个垂直漂移区1208下方延伸以提供电连接至相邻的垂直漏极接触区1206。在该示例中，垂直漏极延伸MOS晶体管1210不具有深沟槽结构1204的围绕实例。至垂直漏极接触区1206的电连接在衬底1202的顶表面处制成。与图11中所示的配置相比，将垂直漏极延伸MOS晶体管1210配置为不具有深沟槽结构的围绕实例可以有利于减少垂直漏极延伸MOS晶体管1210的所需面积，从而降低半导体器件1200的加工成本。
在权利要求的范围内，有可能在所描述的实施例中进行修改，并且其他实施例是可能的。

Claims (11)

1.一种在半导体衬底中形成的垂直漏极延伸晶体管，其包括：
在所述半导体衬底的表面上的多个区域，其中每个所述区域由第一封闭边界和与所述第一封闭边界间隔开的第二封闭边界限定，并且所述第一封闭边界由第一沟槽限定，并且所述第二封闭边界由第二沟槽限定，并且包括：
第一导电类型的源区，其形成在所述半导体衬底的所述表面上，从所述第一封闭边界穿过所述第一封闭边界和所述第二封闭边界之间的整个区域水平延伸到所述第二封闭边界，并且在所述第一沟槽和所述第二沟槽之间垂直延伸；
第二导电类型的本体区，其形成在所述源区下方；以及
所述第一导电类型的垂直定向漂移区，其形成在所述本体区下方，其中：
所述第一沟槽包括在所述第一沟槽的侧面和底部上形成的绝缘衬层以及在所述绝缘衬层上形成并电连接到所述源区的导电材料；
所述第二沟槽包括在所述第二沟槽的侧面和底部上形成的第一栅极介电层和在所述第二沟槽中的所述第一栅极介电层上形成的第一沟槽栅极；
所述本体区接触所述第二沟槽的所述侧面处的所述第一栅极介电层；
所述垂直定向漂移区接触所述第二沟槽的所述底部处的所述第一栅极介电层；并且
所述第一沟槽比所述垂直定向漂移区的顶部深。
2.根据权利要求1所述的垂直漏极延伸晶体管，其中每个所述区域还由与所述第一封闭边界和所述第二封闭边界间隔开的第三封闭边界和第四封闭边界限定，并且所述第三封闭边界由第三沟槽限定，并且所述第四封闭边界由第四沟槽限定，并且
所述第三沟槽包括：
在所述第三沟槽的侧面和底部上形成的第二栅极介电层；以及
在所述第三沟槽中的所述第二栅极介电层上形成的第二沟槽栅极，
所述第四沟槽包括：
在所述第四沟槽的侧面和底部上形成的第三栅极介电层；以及
在所述第四沟槽中的所述第三栅极介电层上形成的第三沟槽栅极，
所述源区从所述第一封闭边界穿过所述第一封闭边界与所述第二封闭边界、所述第三封闭边界和所述第四封闭边界中的每一个之间的整个区域水平延伸到所述第二封闭边界、所述第三封闭边界和所述第四封闭边界中的每一个，并且在所述第一沟槽、所述第二沟槽、所述第三沟槽和所述第四沟槽之间垂直延伸；
所述本体区还与所述第三沟槽的所述侧面处的所述第二栅极介电层和所述第四沟槽的所述侧面处的所述第三栅极介电层接触，并且
所述垂直定向漂移区还与所述第三沟槽的所述底部处的所述第二栅极介电层和所述第四沟槽的所述底部处的所述第三栅极介电层接触。
3.根据权利要求1所述的垂直漏极延伸晶体管，其中所述半导体衬底包括外延层，并且所述第一沟槽和所述第二沟槽形成在所述外延层中。
4.根据权利要求1所述的垂直漏极延伸的晶体管，其中所述第一沟槽的宽度为0.5微米至1.5微米。
5.根据权利要求1所述的垂直漏极延伸晶体管，其中所述第一栅极介电层由二氧化硅和氮氧化铝构成。
6.一种在半导体衬底中形成的垂直漏极延伸晶体管，其包括：
连续沟槽，其限定所述半导体衬底的表面上的多个区域的外部封闭边界，其中
每个所述区域包括第一内部沟槽，所述第一内部沟槽限定每个所述区域的第一内部封闭边界，并且包括：
第一导电类型的源区，其形成在所述半导体衬底的所述表面上，从所述外部封闭边界穿过所述外部封闭边界和所述第一内部封闭边界之间的整个区域水平延伸到所述第一内部封闭边界，并且在所述连续沟槽和所述第一内部沟槽之间垂直延伸；
第二导电类型的本体区，其形成在所述源区下方；以及
所述第一导电类型的垂直定向漂移区，其形成在所述本体区下方，其中：
所述连续沟槽包括在所述连续沟槽的侧面和底部上形成的第一绝缘膜和在所述第一绝缘膜上形成的第一导电材料；
所述第一内部沟槽包括在所述第一内部沟槽的侧面和底部上形成的第二绝缘膜和在所述第一内部沟槽中的所述第二绝缘膜上形成的第二导电材料；并且
所述连续沟槽比所述垂直定向漂移区的顶部深。
7.根据权利要求6所述的垂直漏极延伸晶体管，其中每个所述区域还具有第二内部沟槽和第三内部沟槽，所述第二内部沟槽和所述第三内部沟槽限定第二内部封闭边界和第三内部封闭边界，所述第二内部封闭边界和所述第三内部封闭边界与所述外部封闭边界和所述第一内部封闭边界间隔开，并且
所述第二内部沟槽包括：
在所述第二内部沟槽的侧面和底部上形成的第三绝缘膜；以及
在所述第二内部沟槽中的所述第三绝缘膜上形成的第三导电材料，
所述第三内部沟槽包括：
在所述第三内部沟槽的侧面和底部上形成的第四绝缘膜；以及
在所述第四内部沟槽中的所述第四绝缘膜上形成的第四导电材料，并且
所述源区从所述外部封闭边界穿过所述外部封闭边界与所述第一内部封闭边界、所述第二内部封闭边界和所述第三内部封闭边界中的每一个之间的整个区域水平延伸到所述第一内部封闭边界、所述第二内部封闭边界和所述第三内部封闭边界中的每一个，并且在所述连续沟槽、所述第一沟槽、所述第二沟槽和所述第三沟槽之间垂直延伸。
8.根据权利要求6所述的垂直漏极延伸晶体管，其中所述半导体衬底包括外延层，并且所述连续沟槽和所述第一内部沟槽形成在所述外延层中。
9.根据权利要求6所述的垂直漏极延伸晶体管，其中在所述连续沟槽中的所述第一导电材料电连接到所述源区。
10.根据权利要求6所述的垂直漏极延伸晶体管，其中所述连续沟槽的宽度为0.5微米至1.5微米。
11.根据权利要求6所述的垂直漏极延伸晶体管，其中在所述第一内部沟槽中的所述第二绝缘膜由二氧化硅和氮氧化铝构成。
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