CN111316421B - 减少等离子体引起的损坏的工艺 - Google Patents

减少等离子体引起的损坏的工艺 Download PDF

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CN111316421B
CN111316421B CN201880066193.7A CN201880066193A CN111316421B CN 111316421 B CN111316421 B CN 111316421B CN 201880066193 A CN201880066193 A CN 201880066193A CN 111316421 B CN111316421 B CN 111316421B
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CN111316421A (zh
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李建恒
赵来
翟羽佳
崔寿永
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Applied Materials Inc
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Abstract

本文所描述的实施方式提供了薄膜晶体管(TFT)和工艺以减少在TFT中的等离子体引起的损坏。在一个实施方式中，缓冲层设置在衬底上方，并且半导体层设置在所述缓冲层上方。栅介质层设置在所述半导体层上方。所述栅介质层在界面处接触所述半导体层。栅电极204设置在所述栅介质层上方。所述栅介质层具有约5e10cm‑ 2eV‑1至约5e11cm‑2eV‑1的Dit和约0.10V至约0.30V的磁滞以改善所述TFT的性能能力，同时具有在约6MV/cm与约10MV/cm之间的击穿场。

Description

减少等离子体引起的损坏的工艺
背景技术
领域
本公开内容的实施方式总体涉及薄膜晶体管(TFT)和减少在TFT中的等离子体引起的损坏的工艺。
相关技术描述
平板显示器通常用于有源矩阵显示器，诸如计算机和电视机监视器。一般采用等离子体增强化学气相沉积(PECVD)在衬底(诸如用于平板显示器实现方式的透明衬底)上沉积薄膜。PECVD一般通过将前驱物气体或气体混合物引入容纳有衬底的真空腔室中来完成。前驱物气体或气体混合物典型地通过安置在腔室的与衬底相对的顶部附近的分配板被引导朝向衬底。通过将射频(RF)功率从耦接到腔室的一个或多个RF源施加到腔室来将腔室中的前驱物气体或气体混合物激励(例如，激发)成等离子体。所激发的气体或气体混合物进行反应以在所述衬底的表面上形成材料层。
通过PECVD技术处理的平坦面板典型地是大的，通常超过数平方米。特别是与用于200mm和300mm半导体晶片处理的气体分配板相比，用于在平坦面板上方提供均匀工艺气流的气体分配板(或气体扩散器板)的尺寸相对地大。此外，由于衬底是矩形的，衬底的边缘，诸如衬底的侧面和拐角，就会经历可能与在衬底的其他部分处所经历的条件不同的条件。这些不同的条件影响处理参数，诸如膜厚度、沉积均匀性和/或膜应力。
PECVD经常用于沉积用于TFT的膜。由于PECVD工艺的本质，形成了等离子体。等离子体环境可能是严苛的，并且经常导致损坏。甚至可能损坏下层(在所述下层上沉积后续的层)。
因此，需要的是具有减少的等离子体损坏的TFT和减少等离子体引起的损坏的改善的工艺。
发明内容
在一个实施方式中，提供了一种薄膜晶体管(TFT)。所述TFT包括：衬底；栅电极，所述栅电极设置在所述衬底上；栅介质层，所述栅介质层设置在所述栅电极和所述衬底上；半导体层，所述半导体层设置在所述栅介质层上；和源电极与漏电极，所述源电极和所述漏电极设置在所述半导体层上。所述栅介质层具有在约6MV/cm与约10MV/cm之间的击穿场、约5e10cm-2eV-1至约5e11cm-2eV-1的界面陷阱密度(Dit)和约0.10V至约0.30V的磁滞(hysteresis)。
在一个实施方式中，提供了一种薄膜晶体管(TFT)。所述TFT包括：衬底；缓冲层，所述缓冲层设置在所述衬底上；半导体层，所述半导体层设置在所述缓冲层上；栅介质层，所述栅介质层设置在所述半导体层上；栅电极，所述栅电极设置在所述栅介质层上；层间介电(ILD)层，所述层间介电层设置在所述栅介质层和所述栅电极上；和源电极与漏电极，所述源电极设置在所述ILD层的源电极过孔中，所述漏电极设置在所述ILD层的漏电极过孔中。所述栅介质层具有在6MV/cm与约10MV/cm之间的击穿场、约5e10cm-2eV-1至约5e11cm-2eV-1的界面陷阱密度(Dit)和约0.10V至约0.30V的磁滞。
在一个实施方式中，提供了一种制造薄膜晶体管(TFT)的方法。所述方法包括：使沉积气体以沉积气体流率流动到腔室的工艺容积中；在初始间隔内以初始功率水平将射频(RF)功率施加到所述沉积气体，从而形成栅介质层的区范围的初始区，所述初始区具有带有最小密度的区密度；和在间隔中增大所述初始功率水平，从而形成所述区范围的区，直到在最终间隔内以最终功率水平施加所述RF功率，从而形成所述区范围内的最终区，所述最终区具有带有最大密度的所述区密度，并且所形成的每个区的所述区密度具有不小于前一个区的所述区密度的密度。
附图说明
为了能够详细理解本公开内容的上述特征的方式，可以参考实施方式来获得以上简要概述的本公开内容的更具体描述，实施方式中的一些在附图中图示。然而，应注意，附图仅图示示例性实施方式，并且因此不视为对本公开内容的范围的限制，而可以允许其他等效实施方式。
图1图示根据本文所描述的实施方式的PECVD腔室的示意性横截面图。
图2图示根据一个实施方式的顶栅型TFT的示意性横截面图。
图3A图示根据一个实施方式的示例性栅介质层的示意性横截面图。
图3B图示根据一个实施方式的示例性栅介质层的示意性横截面图。
图4是根据一个实施方式的制造顶栅型TFT的方法的流程图。
为了便于理解，已经尽可能地使用相同的参考数字标示各图共有的相同元件。设想的是，一个实施方式的元素和特征可以有益地并入其他实施方式，而不进一步叙述。
具体实施方式
本文所描述的实施方式涉及具有减少的等离子体损坏的TFT和在TFT制造期间减少对衬底或已经沉积的膜的等离子体损坏的工艺。来自PECVD工艺的等离子体可能损坏已经沉积的膜。具体地，暴露表面(要通过PECVD工艺在暴露表面上沉积层)可能损坏。如本文所讨论的，公开了减少和/或消除等离子体损坏的工艺。
以下参考被配置为处理大面积衬底的PECVD系统(诸如可从加利福尼亚州圣克拉拉市应用材料公司(Applied Materials,Inc.,Santa Clara,California)的子公司AKT获得的PECVD系统)说明性地描述本文中的实施方式。设想的是，根据本文所描述的实施方式，也可以实现来自其他制造商的其他适当配置的设备。此外，应理解，本文所描述的各种实现方式在其他系统配置中是有用的，所述其他系统配置诸如蚀刻系统、其他化学气相沉积系统或其中期望在工艺腔室内分配气体的其他系统，包括被配置为处理圆形衬底的那些系统。
图1图示用于形成平板显示器的电子器件的PECVD腔室100的示意性横截面图，所述电子器件诸如薄膜晶体管(TFT)器件和有源矩阵有机发光二极管(AMOLED)器件。腔室100包括壁102、底部104和扩散器110，以上项限定了工艺容积106。更具体地，进一步由壁102的表面107限定工艺容积106。在一个实施方式中，壁102、底部104和扩散器110由金属材料制成，所述金属材料诸如铝、不锈钢和以上项的合金。例如，扩散器110可以由6061铝合金形成。在另一个实施方式中，扩散器110可以由阳极化铝材料形成。衬底支撑件130在扩散器110对面设置在工艺容积106中。通过穿过壁102形成的可密封的狭缝阀开口108进出工艺容积106，使得衬底105可以被传送进出腔室100。
衬底支撑件130包括用于支撑衬底105的衬底接收表面132，和耦接到升降系统(lift system)136以升高和降低衬底支撑件130的轴134。在操作中，在处理期间，可以将阴影框架133定位在衬底105的周边上方。升降杆138可以穿过衬底支撑件130可移动地设置，以向和从衬底接收表面132移动衬底105来便于衬底传送。衬底支撑件130还可以包括加热和/或冷却元件139，以将衬底支撑件130和定位在所述衬底支撑件上的衬底105维持在所期望的温度。衬底支撑件130还可以包括接地带131以在衬底支撑件130的周边提供RF接地。
扩散器110邻近扩散器110的周边由悬挂元件114耦接到背板112。扩散器110还可以由一个或多个中心支撑件116耦接到背板112，以帮助阻止下垂和/或控制扩散器110的直度/曲率。气源120流体地耦接到背板112，以穿过背板112将气体提供到形成在扩散器110中的多个气体通道111并最终地提供到衬底接收表面132。
真空泵109耦接到腔室100以控制工艺容积106内的压力。RF功率源122耦接到背板112和/或扩散器110，以向扩散器110提供RF功率来在扩散器110与衬底支撑件130之间产生电场。在操作中，存在于扩散器110与衬底支撑件130之间的气体被RF电场激励成等离子体。可以使用各种RF频率，诸如在约0.3MHz与约200MHz之间的频率。在一个实施方式中，RF功率源122以13.56MHz的频率向扩散器110提供功率。
远程等离子体源124也耦接在气源120与背板112之间。取决于所期望的实现方式，远程等离子体源124可以是电感耦合远程等离子体源、电容耦合远程等离子体源或微波远程等离子体源。远程等离子体源124可以用于辅助工艺气体等离子体产生和/或清洁气体等离子体产生。
在一个实施方式中，嵌入在衬底支撑件130中的加热和/或冷却元件139用于在沉积期间将衬底支撑件130和衬底105的温度维持在约200摄氏度至约500摄氏度或更低。
在沉积工艺期间在设置于衬底接收表面132上的衬底105的顶表面与扩散器110的底表面140之间的间隔可以在400密耳与约1,200密耳之间，例如在400密耳与约800密耳之间。腔室100可以用于沉积各种材料，诸如氮化硅材料、氧化硅材料、非晶硅材料，以供用于各种应用，包括层间介电膜和栅极绝缘膜等。
图2图示根据一个实施方式的顶栅型TFT 200的示意性横截面图。顶栅型TFT 200包括衬底202、缓冲层204、半导体层206、栅介质层208、栅电极210、层间介电(ILD)层212、源电极214和漏电极216。衬底202可以包括任何合适的材料，诸如基于硅的衬底、基于半导体的衬底、基于绝缘的衬底、基于锗的衬底、和一般会存在于CMOS结构中的一个或多个通用层。应理解，也设想了其他材料。
缓冲层204设置在衬底202上方，并且半导体层206设置在缓冲层204上方。在一个实施方式中，缓冲层204包括以下材料中的至少一种：含一氮化硅(SiN)的材料和含二氧化硅(SiO2)的材料。半导体层206包括半导体材料。在一个实施方式中，半导体材料包括硅、多晶硅、低温多晶硅、非晶硅、铟镓锌氧化物(IGZO)和含氮氧化锌(ZnON)的材料中的至少一种。应理解，也设想了其他材料。栅介质层208设置在半导体层206上方。在一个实施方式中，栅介质层208具有约500埃至约1500埃的厚度。栅介质层208在界面201处接触半导体层。栅介质层208包括绝缘材料。在一个实施方式中，绝缘材料包括包括一氮化硅(SiN)、四氮化三硅(Si3N4)、一氧化硅(SiO)、二氧化硅(SiO2)和含氮氧化硅(Si2N2O)的材料中的至少一种。应理解，也设想了其他材料。可以通过等离子体增强化学气相沉积(PECVD)工艺来沉积半导体层206和栅介质层208。
栅电极210设置在栅介质层208上方。ILD层212设置在栅电极210上方。源电极214设置在ILD层212的源电极过孔218中，并且漏电极216设置在ILD层212的漏电极过孔220中。栅电极210、源电极214和漏电极216各自包括导电材料，诸如铜、钛、钽或任何导电金属。应理解，也设想了其他材料。在一个实施方式中，用于栅电极210、源电极214和漏电极216的材料是相同的材料。在另一个实施方式中，用于栅电极210、源电极214和漏电极216中的至少一个的材料不同于用于其余两个电极的材料。在又一个实施方式中，用于栅电极210、源电极214和漏电极216的材料对于每个电极来说是不同的。可以通过物理气相沉积(PVD)来沉积栅电极210、源电极214和漏电极216。ILD层212可以由任何合适的介电材料(诸如氧化硅)制成。可以通过PECVD工艺来沉积缓冲层204和ILD层212。
栅介质层208具有在约6兆伏/厘米(MV/cm)与约10MV/cm之间的击穿场。击穿场是高离子轰击的结果，这一般是因在PECVD工艺中向沉积气体施加高RF功率以使栅介质层208致密而造成。在PECVD工艺中，界面201和半导体层206可能因PECVD工艺的高离子轰击而损坏。常规地，由于PECVD工艺的高离子轰击对界面210和半导体层206的损坏，栅介质层208具有大于约5e11cm-2eV-1的界面陷阱密度(Dit)和大于约0.30V的磁滞。大于约5e11cm-2eV-1的Dit和大于约0.30V的磁滞可能降低顶栅型TFT200的性能能力。
图3A是示例性栅介质层208A的示意性横截面图。示例性栅介质层208A具有约5e10cm-2eV-1至约5e11cm-2eV-1的Dit和约0.10V至约0.30V的磁滞以改善顶栅型TFT 200的性能能力，同时具有在约6MV/cm与约10MV/cm之间的击穿场。约5e10cm-2eV-1至约5e11cm-2eV-1的Dit和约0.10V至约0.30V的磁滞是穿过栅介质层208A的厚度的区范围的密度分布(profile)的结果。
栅介质层208A具有第一表面304、第二表面306和厚度308。栅介质层208A的厚度308被划分为从对应于厚度308的0％的第一表面304到对应于厚度308的100％的第二表面306测量的区范围310。每个区312具有区厚度和区密度。在一个实施方式中，每个区312具有为厚度308的约0.001％至约20％的区厚度。穿过厚度308的区范围310的密度分布具有最小密度和最大密度。在一个实施方式中，区范围310的邻近于第一表面304的初始区314具有带有最小密度的区密度，区范围310的邻近于第二表面306相邻的最终区316具有带有最大密度的区密度，并且紧接地设置在前一个区上方的每个区312的区密度不小于前一个区的区密度。在一个实施方式中，最小密度为约2.1g/cm3，并且最大密度为约2.25g/cm3。
在一个实施方式中，每个区312具有大体上相同的区厚度，并且紧接地设置在前一个区上方的每个区312具有不小于前一个区的区密度的区密度。在另一个实施方式中，区密度的增大是PECVD工艺的结果。PECVD工艺包括在初始间隔内以初始功率水平将射频(RF)功率施加到沉积气体，从而形成区范围310的初始区314，并且在间隔中增大初始功率水平，从而形成区范围310的区312，直到在最终间隔内以最终功率水平施加RF功率，从而形成区范围的最终区316。区范围310中的每个区312具有大体上相同的厚度，并且紧接地设置在前一个区上方的每个区312具有不小于前一个区的区密度的区密度。参照图2，栅介质层208A的第一表面304在界面201处与半导体层206接触。栅介质层208A具有约5e10cm-2eV-1至约5e11cm-2eV-1的Dit和约0.10V至约0.30V的磁滞。
图3B是示例性栅介质层208B的示意性横截面图。示例性栅介质层208B具有约5e10cm-2eV-1至约5e11cm-2eV-1的Dit和约0.10V至约0.30V的磁滞以改善顶栅型TFT 200的性能能力，同时具有在约6MV/cm与约10MV/cm之间的击穿场。约5e10cm-2eV-1至约5e11cm-2eV-1的Dit和约0.10V至约0.30V的磁滞是栅介质层208B的中间层具有不大于栅介质层208B的厚度的约20％的厚度和所述中间层具有不大于栅介质层208B的体层(bulk layer)的密度的密度的结果。
栅介质层208B具有第一表面304、第二表面306、中间层301、体层302和厚度308。在一个实施方式中，中间层301包括第一表面304，并且体层302包括第二表面306。体层302设置在中间层301上方。厚度308包括中间层301的厚度303和体层302的厚度305。中间层301的厚度303不大于厚度308的约20％。中间层301的密度不大于体层302的密度。在一个实施方式中，体层302的密度大于约2.15g/cm3。参照图2，栅介质层208B的第一表面304在界面201处与半导体层206接触。栅介质层208B具有约5e10cm-2eV-1至约5e11cm-2eV-1的Dit和约0.10V至约0.30V的磁滞。
图4是制造顶栅型TFT的方法400的流程图。在一个实施方式中，腔室100用于方法400。在可选的操作401处，在衬底202上形成TFT的初始层。在一个实施方式中，通过PECVD处理在衬底202上方沉积缓冲层204，并且在缓冲层204上方沉积半导体层206。在操作402处，沉积栅介质层208。
在一个实施方式中，通过单步式PECVD工艺来沉积栅介质层208A。单步式PECVD工艺包括使沉积气体以沉积气体流率流动到腔室100的工艺容积106中，并且将RF功率施加到沉积气体。在一个实施方式中，沉积气体包括硅烷(SiH4)、一氧化二氮(N2O)和氩(Ar)。沉积气体流率包括约800sccm至约1600sccm的SiH4、约30000sccm至约70000sccm的N2O和约40000sccm至约70000sccm的Ar。在一个实施方式中，RF功率源122向扩散器110提供RF功率。在初始间隔上以初始功率水平和一定频率施加RF功率。初始功率水平在间隔中增大(也被称为上升(ramp))，直到在最终间隔上以最终功率水平施加RF功率。在一个实施方式中，间隔为约0.5秒至约2秒。初始功率水平可以在间隔中逐步地、指数地或线性地增大，直到以最终功率水平施加RF功率。在一个实施方式中，RF功率为约2000瓦(W)至约16000W。例如，初始功率水平为约2000W至约5000W，而最终功率水平为约12000W至约16000W。增大初始功率造成栅介质层208A被划分为从对应于厚度308的0％的第一表面304到对应于厚度308的100％的第二表面306测量的区范围310。每个区312具有区厚度和区密度。在一个实施方式中，每个区312具有为厚度308的约0.001％至约20％的区厚度。
穿过厚度308的区范围310的密度分布具有最小密度和最大密度。在一个实施方式中，区范围310的邻近于第一表面304并且对应于初始间隔的初始区具有带有最小密度的区密度，区范围310的邻近于第二表面306并且对应于最终间隔的最终区316具有带有最大密度的区密度，并且紧接地沉积在前一个区上方的每个区312的区密度不小于前一个区的区密度。密度分布是在间隔中增大初始功率水平的结果，从而可以减少因离子轰击而对下层造成的等离子体损坏。在一个实施方式中，每个区312具有大体上相同的区厚度，并且紧接地设置在前一个区上方的每个区312具有不小于前一个区的区密度的区密度。在另一个实施方式中，区密度的增大是RF功率上升的结果。以下操作可造成区范围310中的每个区312具有大体上相同的厚度并且紧接地设置在前一个区上方的每个区312具有不小于前一个区的区密度的区密度：在初始间隔内以初始功率水平将RF功率施加到沉积气体，从而形成区范围310的初始区314，在间隔中增大初始功率水平，从而形成区范围310的区312，直到在最终间隔内以最终功率水平施加RF功率，从而形成区范围的最终区316。
在另一个实施方式中，在间隔中减小在初始间隔上的工艺容积106中的初始压力，直到在最终间隔上达到最终压力。在一个实施方式中，在间隔中使约900mTorr至约1300mTorr的初始压力减小。区范围310的对应于每个间隔的每个区312具有区厚度和区密度。区范围310的对应于初始间隔的初始区具有带有最小密度的区密度，区范围310的对应于最终间隔的最终区316具有带有最大密度的区密度，并且紧接地设置在前一个区上方的每个区的区密度具有不小于前一个区的区密度的区密度。
在一个实施方式中，通过两步式PECVD工艺来沉积栅介质层208B。两步式PECVD工艺包括使沉积气体以沉积气体流率流动到腔室100的工艺容积106中，并且将RF功率施加到沉积气体。在一个实施方式中，RF功率源122向扩散器110提供RF功率。以初始功率水平和一定频率施加RF功率，并且工艺容积106在初始间隔内具有初始压力，直到沉积栅介质层208B的中间层301。以最终功率水平施加RF功率，并且工艺容积106在最终间隔内具有最终压力，直到沉积栅介质层208B的体层302。在一个实施方式中，初始功率水平大于最终功率水平。在另一个实施方式中，最终压力小于初始压力。在一个实施方式中，RF功率为约2000瓦(W)至约16000W。例如，初始功率水平为约2000W至约5000W，而最终功率水平为约12000W至约16000W。在一个实施方式中，初始压力为约900mTorr至约1300mTorr。中间层301的厚度303不大于厚度308的约20％。中间层301的密度不大于体层302的密度。以初始功率水平沉积的中间层301减少因以最终功率水平的离子轰击沉积栅介质层208B的体层302而对下层造成的等离子体损坏。
在操作403处，形成TFT的剩余结构。在一个实施方式中，通过PVD处理在栅介质层208上方形成栅电极210。通过PECVD处理在栅电极210上方沉积ILD层212。在形成于ILD层212中的源电极过孔218中通过PVD处理形成源电极214，并且在形成于ILD层212中的漏电极过孔220中通过PVD处理形成漏电极216。
总而言之，本文描述了TFT和制造具有栅介质层的TFT的方法。栅介质层具有约5e10cm-2eV-1至约5e11cm-2eV-1的Dit和约0.10V至约0.30V的磁滞以改善顶栅型TFT 200的性能能力，同时具有在约6MV/cm与约10MV/cm之间的击穿场。单步式PECVD工艺形成具有穿过栅介质层的厚度的区范围的密度分布的栅介质层。区范围的邻近于下层的初始区具有带有最小密度的区密度，范围的最终区具有带有最大密度的区密度，并且紧接地设置在前一个区上方的每个区的区密度不小于前一个区的区密度。密度分布是在间隔中增大初始功率水平的结果，从而减少因离子轰击而对下层造成的等离子体损坏。两步式PECVD工艺形成具有中间层和体层的栅介质层。中间层具有不大于栅介质层的厚度的约20％的厚度并具有不大于体层的密度的密度。以初始功率水平沉积的中间层减少以沉积栅介质的体层的最终功率水平的离子轰击对下层造成的等离子体损坏。
尽管前述内容针对的是本公开内容的示例，但是在不脱离本公开内容的基本范围的情况下，可以设想本公开内容的其他和进一步的示例，并且本公开内容的范围由所附权利要求书确定。

Claims (16)

1.一种薄膜晶体管(TFT)，包括：
衬底；
缓冲层，所述缓冲层设置在所述衬底上；
半导体层，所述半导体层设置在所述缓冲层上；
栅介质层，所述栅介质层设置在所述半导体层上，所述栅介质层在界面处接触所述半导体层，所述栅介质层具有在6MV/cm与10MV/cm之间的击穿场、5e10 cm-2eV-1至5e11 cm-2eV-1的界面陷阱密度(Dit)和0.10V至0.30V的磁滞；
栅电极，所述栅电极设置在所述栅介质层上；
层间介电(ILD)层，所述层间介电层设置在所述栅介质层和所述栅电极上；和
源电极与漏电极，所述源电极设置在所述ILD层的源电极过孔中，所述漏电极设置在所述ILD层的漏电极过孔中。
2.如权利要求1所述的TFT，其中所述栅介质层包括：
第一表面，所述第一表面在所述界面处接触所述半导体层；
第二表面，所述第二表面接触所述栅电极和所述ILD层；
厚度，所述厚度被划分成从对应于所述厚度的0％的所述第一表面到对应于所述厚度的100％的所述第二表面的区范围，所述区范围的每个区具有区厚度和区密度；和
密度分布，所述密度分布穿过所述区范围，所述密度分布具有最小密度和最大密度，其中：
所述区范围的邻近于所述第一表面的初始区具有带有所述最小密度的所述区密度；并且
所述区范围的邻近于所述第二表面的最终区具有带有所述最大密度的所述区密度，紧接地设置在前一个区上方设置的每个区的所述区密度不小于所述前一个区的所述区密度。
3.如权利要求2所述的TFT，其中所述区厚度为所述厚度的0.001％至20％。
4.如权利要求1所述的TFT，其中所述栅介质层包括：
中间层，所述中间层具有第一表面，所述第一表面在与所述第一表面的所述界面处接触所述半导体层；
体层，所述体层具有第二表面，所述第二表面接触所述栅电极和所述ILD层；和
厚度，所述厚度基本上由所述中间层和所述体层组成，所述中间层不大于所述厚度的约20％并且具有不大于所述体层的密度的密度。
5.如权利要求1所述的TFT，其中所述栅介质层具有500埃至1500埃的厚度。
6.如权利要求1所述的TFT，其中所述缓冲层包括以下材料中的至少一种：含一氮化硅(SiN)的材料和含二氧化硅(SiO2)的材料。
7.如权利要求1所述的TFT，其中所述半导体层包括硅、多晶硅、非晶硅、铟镓锌氧化物(IGZO)和含氮氧化锌(ZnON)的材料中的至少一种。
8.如权利要求7所述的TFT，其中所述多晶硅是低温多晶硅。
9.如权利要求1所述的TFT，其中所述栅介质层包括SiN、四氮化三硅(Si3N4)、一氧化硅(SiO)、二氧化硅SiO2和含氮氧化硅Si2N2O的材料中的至少一种。
10.如权利要求1所述的TFT，其中所述栅电极、所述源电极和所述漏电极各自包括铜、钛和含钽材料中的至少一种。
11.一种薄膜晶体管(TFT)，包括：
衬底；
缓冲层，所述缓冲层设置在所述衬底上；
半导体层，所述半导体层设置在所述缓冲层上；
栅介质层，所述栅介质层设置在所述半导体层上，所述栅介质层具有第一表面和第二表面，所述第一表面在界面处接触所述半导体层，所述栅介质层具有6MV/cm至10MV/cm的击穿场、5e10 cm-2eV-1至5e11cm-2eV-1的界面陷阱密度(Dit)和0.10V至0.30V的磁滞，所述栅介质层包括：
中间层，所述中间层具有第一表面，所述第一表面在与所述第一表面的所述界面处接触所述半导体层；
体层，所述体层具有第二表面，所述第二表面接触栅电极和ILD层；和
厚度，所述厚度基本上由所述中间层和所述体层组成，所述中间层不大于所述厚度的约20％并且具有不大于所述体层的密度的密度；
栅电极，所述栅电极设置在所述栅介质层上，所述栅电极接触所述栅介质层的所述第二表面；
层间介电(ILD)层，所述层间介电层设置在所述栅介质层和所述栅电极上；和
源电极与漏电极，所述源电极设置在所述ILD层的源电极过孔中，所述漏电极设置在所述ILD层的漏电极过孔中。
12.如权利要求11所述的TFT，其中所述栅介质层包括SiN、四氮化三硅(Si3N4)、一氧化硅(SiO)、二氧化硅(SiO2)和含氮氧化硅(Si2N2O)的材料中的至少一种。
13.一种制造薄膜晶体管(TFT)的方法，包括：
使沉积气体以沉积气体流率流动到腔室的工艺容积中；
在初始间隔内以初始功率水平将射频(RF)功率施加到所述沉积气体，从而形成栅介质层的中间层，所述中间层具有第一表面，所述第一表面在与半导体层的界面处接触所述半导体层；和
增大所述初始功率水平，直到在最终间隔内以最终功率水平施加所述RF功率，从而形成所述栅介质层的体层，所述栅介质层包括厚度，所述厚度基本上由所述中间层和所述体层组成，所述中间层不大于所述厚度的约20％并且具有不大于所述体层的密度的密度。
14.如权利要求13所述的方法，进一步包括：在使所述沉积气体以所述沉积气体流率流动之前，在衬底上形成所述TFT的初始层；和在所述最终间隔内以所述最终功率水平施加所述RF功率之后，形成所述TFT的剩余结构。
15.如权利要求13所述的方法，其中使所述沉积气体以初始压力在所述初始间隔上流动，并且降低所述初始压力，直到在所述最终间隔上达到最终压力。
16.如权利要求13所述的方法，其中所述RF功率为2000瓦(W)至16000W，所述初始功率水平为2000W至5000W，并且所述最终功率水平为12000W至16000W。
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US11380801B2 (en) 2022-07-05
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US11670722B2 (en) 2023-06-06
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US20240088301A1 (en) 2024-03-14
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WO2019074674A1 (en) 2019-04-18
CN116960162A (zh) 2023-10-27
US10804408B2 (en) 2020-10-13
US20220293793A1 (en) 2022-09-15
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US20190115475A1 (en) 2019-04-18
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