CN111312835A - 单电子传输雪崩光电二极管结构及制作方法 - Google Patents

单电子传输雪崩光电二极管结构及制作方法 Download PDF

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CN111312835A
CN111312835A CN202010101878.XA CN202010101878A CN111312835A CN 111312835 A CN111312835 A CN 111312835A CN 202010101878 A CN202010101878 A CN 202010101878A CN 111312835 A CN111312835 A CN 111312835A
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黄晓峰
张承
王立
唐艳
高新江
莫才平
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Abstract

本发明公开了一种单电子传输雪崩光电二极管结构，包括衬底,在衬底上依次生长有P型InAlGaAs接触层、P型InGaAs吸收层、非故意掺杂InGaAlAs渐变层、P型InAlAs场控层、非故意掺杂InAlAs倍增层、N型InAlAs场控层、N型InAlAs缓冲层和N型InGaAs接触层；本发明还公开了该单电子传输雪崩光电二极管结构的制作方法以及另一单电子传输雪崩光电二极管结构及其制作方法。本发明将InGaAs吸收层设计为P型掺杂，光生空穴为多子，其以驰豫过程参与载流子传输，发生载流子迁移的只有电子，通过高迁移率的电子极大的增加了器件的频率和饱和特性。

Description

单电子传输雪崩光电二极管结构及制作方法
技术领域
本发明涉及半导体器件领域，特别涉及一种单电子传输雪崩光电二极管结构及制作方法。
背景技术
雪崩光电二极管(APD)器件参数中带宽、增益与过载光功率是互为抑制的物理特性，随着传输速率的不断提高，在25Gb/s NRZ和56Gb/s PAM4应用中，APD带宽与过载光功率的矛盾更加突出；APD发展至今，都采用吸收、渐变、电荷、倍增分离的(SAGCM)结构，传统的SAGCM结构无法同时满足器件高速工作时带宽与过载光功率的要求。
目前InGaAs/InP基APD结构中，载流子传输采用电子和空穴，空穴迁移率比电子迁移率低，容易在PN界面或者能带不连续处产生积累，产生空间电荷屏蔽效应，限制器件频率(速率)和饱和(过载光功率)特性。
另外，传统台面型探测器器件侧壁采用等离子增强化学气相淀积(PECVD)生长二氧化硅(SiO2)、氮化硅(SiNx)或者涂覆聚酰亚胺(PI)、苯并环丁烯(BCB)进行钝化，过高的工艺温度或者较低的介质致密性会使等离子体轰击时破坏化合物半导体表面的悬挂键，造成表面态不稳定，增加漏电流，使其在实际应用中效果不佳。
发明内容
本发明要解决的技术问题是提供了一种高速率高过载光功率的单电子传输雪崩光电二极管结构及制作方法。
本发明的技术方案如下：
一种单电子传输雪崩光电二极管结构，包括InP半绝缘衬底,在所述InP半绝缘衬底上依次生长有P型InAlGaAs接触层、P型In0.53Ga0.47As吸收层、非故意掺杂InGaAlAs渐变层、P型In0.52Al0.48As场控层、非故意掺杂In0.52Al0.48As倍增层、N型In0.52Al0.48As场控层、N型In0.52Al0.48As缓冲层和N型In0.53Ga0.47As接触层；所述N型In0.53Ga0.47As接触层连接有N型电极，所述P型InAlGaAs接触层连接有P型电极。
进一步的，所述光电二极管结构为四层台面的同心圆结构，第一层台面为N型In0.53Ga0.47As接触层的上表面，第二层台面位于N型In0.52Al0.48As缓冲层的上表面，第三层台面位于非故意掺杂In0.52Al0.48As倍增层的上表面，第四层台面位于P型InAlGaAs接触层的上表面，所述N型电极覆盖在N型In0.53Ga0.47As接触层的上表面，所述P型电极覆盖在第四层台面上，在第二层台面、第三层台面和第四层台面上设有钝化层，所述钝化层的上表面与第一层台面齐平。
进一步的，所述P型In0.53Ga0.47As吸收层为P型重掺杂，掺杂元素为碳，掺杂浓度为0.5×1018cm-3～5×1018cm-3或者为0.5×1018cm-3至5×1018cm-3渐变浓度掺杂，厚度为500～1500nm。
进一步的，所述非故意掺杂InGaAlAs渐变层的截止波长为1.1～1.5μm，掺杂浓度≤1×1016cm-3；所述P型In0.52Al0.48As场控层的掺杂元素为碳，掺杂浓度为5×1017cm-3～10×1017cm-3；所述非故意掺杂In0.52Al0.48As倍增层的掺杂浓度≤1×1016cm-3；所述N型In0.52Al0.48As场控层的掺杂元素为硅，掺杂浓度为1×1018cm-3～5×1018cm-3；所述N型In0.52Al0.48As缓冲层为非故意掺杂，掺杂浓度≤1×1016cm-3。
一种单电子传输雪崩光电二极管制作方法，包括以下步骤：
步骤S101、采用金属有机物化学气相淀积或分子束外延在InP半绝缘衬底上依次生长P型InAlGaAs接触层、P型In0.53Ga0.47As吸收层、非故意掺杂InGaAlAs渐变层、P型In0.52Al0.48As场控层、非故意掺杂In0.52Al0.48As倍增层、N型In0.52Al0.48As场控层、N型In0.52Al0.48As缓冲层和N型In0.53Ga0.47As接触层；
步骤S102、采用光刻剥离工艺利用电子束蒸发或磁控溅射在N型In0.53Ga0.47As接触层的上表面制作N型电极；
步骤S103、采用干法刻蚀或湿法刻蚀将N型In0.53Ga0.47As接触层上表面的外沿向下刻蚀至N型In0.52Al0.48As缓冲层的上表面，形成第二层台面；
步骤S104、采用干法刻蚀或湿法刻蚀将第二层台面的外沿向下刻蚀至非故意掺杂In0.52Al0.48As倍增层的上表面，形成第三层台面；
步骤S105、采用干法刻蚀或湿法刻蚀将第三层台面的外沿向下刻蚀至P型InAlGaAs接触层的上表面，形成第四层台面；
步骤S106、在第二层台面、第三层台面和第四层台面上采用原子层沉积淀积三氧化二铝介质进行钝化，形成钝化层；
步骤S107、通过光刻工艺在第四层台面上定义出光敏面、电极孔，采用光刻剥离工艺利用电子束蒸发或磁控溅射在第四层台面上制作P型电极；
步骤S108、采用化学机械抛光的方式将P型电极和N型电极的外延片背面减薄后，解理成单元芯片。
一种单电子传输雪崩光电二极管结构，包括InP半绝缘衬底,在所述InP半绝缘衬底上依次生长有N型In0.52Al0.48As接触层、非故意掺杂In0.52Al0.48As倍增层、P型In0.52Al0.48As场控层、非故意掺杂InGaAlAs渐变层、P型In0.53Ga0.47As吸收层和P型In0.53Ga0.47As接触层，所述P型In0.53Ga0.47As接触层连接有P型电极，所述N型In0.52Al0.48As接触层连接有N型电极。
进一步的，所述光电二极管结构为三层台面的同心圆结构，第一层台面为P型In0.53Ga0.47As接触层的上表面，第二层台面位于P型In0.53Ga0.47As吸收层的上表面，第三层台面位于N型In0.52Al0.48As接触层的上表面，所述P型电极覆盖在P型In0.53Ga0.47As接触层的上表面，所述N型电极覆盖在第三层台面上，在所述第二层台面和第三层台面上设有钝化层。
进一步的，所述P型In0.53Ga0.47As吸收层为P型重掺杂，掺杂元素为碳，掺杂浓度为0.5×1018cm-3～5×1018cm-3或者为0.5×1018cm-3至5×1018cm-3渐变浓度掺杂。
进一步的，所述非故意掺杂In0.52Al0.48As倍增层的掺杂浓度≤1×1016cm-3；所述非故意掺杂In0.52Al0.48As倍增层的掺杂浓度≤1×1016cm-3，所述P型In0.52Al0.48As场控层的掺杂元素为碳，掺杂浓度为5×1017cm-3～10×1017cm-3，所述非故意掺杂InGaAlAs渐变层的截止波长为1.1～1.5μm，掺杂浓度≤1×1016cm-3。
一种单电子传输雪崩光电二极管制作方法，包括以下步骤：
步骤S201、采用金属有机物化学气相淀积或分子束外延在所述InP半绝缘衬底上依次生长N型In0.52Al0.48As接触层、非故意掺杂In0.52Al0.48As倍增层、P型In0.52Al0.48As场控层、非故意掺杂InGaAlAs渐变层、P型In0.53Ga0.47As吸收层和P型In0.53Ga0.47As接触层；
步骤S202、采用光刻剥离工艺利用电子束蒸发或磁控溅射在P型In0.53Ga0.47As接触层的上表面制作P型电极；
步骤S203、采用干法刻蚀或湿法刻蚀将P型In0.53Ga0.47As接触层上表面的外沿向下刻蚀至P型In0.53Ga0.47As吸收层上表面，形成第二层台面；
步骤S204、采用干法刻蚀或湿法刻蚀将第二层台面的外沿向下刻蚀至N型In0.52Al0.48As接触层的上表面，形成第三层台面；
步骤S205、在第二层台面和第三层台面上采用原子层沉积淀积三氧化二铝介质进行钝化，形成钝化层；
步骤S206、通过光刻工艺在第三层台面上定义出光敏面、电极孔，采用光刻剥离工艺利用电子束蒸发或磁控溅射在第三层台面上制作N型电极；
步骤S207、采用化学机械抛光的方式将P型电极和N型电极的外延片背面减薄后，解理成单元芯片。
本发明的有益效果如下：
1、将单行载流子的理念引入SAGCM结构中，将InGaAs吸收层设计为P型掺杂，光生空穴为多子，其以驰豫过程参与载流子传输，发生载流子迁移的只有电子，通过高迁移率的电子极大的增加了器件的频率和饱和特性；
2、采用多层同心圆台面结构，稀释了台面侧壁电场强度，减小了表面漏电流，降低了器件暗电流，提高了可靠性；
3、采用原子层沉积的方式淀积三氧化二铝介质层对台面进行钝化，降低了器件表面漏电流，提高了器件可靠性。
附图说明
图1为本发明单电子传输雪崩光电二极管结构一个实施例的结构示意图；
图2为本发明单电子传输雪崩光电二极管结构一个实施例去掉钝化层后的俯视图；
图3为本发明单电子传输雪崩光电二极管结构一个实施例的制作流程图；
图4为本发明单电子传输雪崩光电二极管结构另一实施例的结构示意图；
图5为本发明单电子传输雪崩光电二极管结构另一实施例去掉钝化层后的俯视图；
图6为本发明单电子传输雪崩光电二极管结构另一实施例的制作流程图。
具体实施方式
下面结合附图对本发明作进一步说明。
在本发明的描述中，除非另有规定和限定，需要说明的是，术语“连接”应做广义理解，例如，可以是机械连接或电连接，也可以是两个元件内部的连通，可以是直接相连，也可以通过中间媒介间接相连，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。
实施例1：
如图1和图2所示，本发明单电子传输雪崩光电二极管结构的一个实施例包括InP半绝缘衬底1,在所述InP半绝缘衬底1上依次生长有P型InAlGaAs接触层2、P型In0.53Ga0.47As吸收层3、非故意掺杂InGaAlAs渐变层4、P型In0.52Al0.48As场控层5、非故意掺杂In0.52Al0.48As倍增层6、N型In0.52Al0.48As场控层7、N型In0.52Al0.48As缓冲层8和N型In0.53Ga0.47As接触层9；所述N型In0.53Ga0.47As接触层9连接有N型电极10，所述P型InAlGaAs接触层2连接有P型电极11。
所述光电二极管结构为四层台面的同心圆结构，第一层台面为N型In0.53Ga0.47As接触层9的上表面，第二层台面位于N型In0.52Al0.48As缓冲层8的上表面，第三层台面位于非故意掺杂In0.52Al0.48As倍增层6的上表面，第四层台面位于P型InAlGaAs接触层2的上表面，所述N型电极10覆盖在N型In0.53Ga0.47As接触层9的上表面，所述P型电极11覆盖在第四层台面上，在第二层台面、第三层台面和第四层台面上设有钝化层12。采用多层同心圆台面结构，稀释了台面侧壁电场强度，减小了表面漏电流，降低了器件暗电流，提高了可靠性。
所述P型InAlGaAs接触层2的厚度为500～1500nm，截止波长为1.0～1.1μm,掺杂元素为碳(C)，掺杂浓度≥1×1019cm-3。
所述P型In0.53Ga0.47As吸收层3的厚度为500～1500nm，掺杂元素为碳(C)，掺杂浓度为0.5×1018cm-3～5×1018cm-3或者为0.5×
1018cm-3至5×1018cm-3渐变浓度掺杂。将In0.53Ga0.47As吸收层3设计为P型掺杂，光生空穴为多子，其以驰豫过程参与载流子传输，发生载流子迁移的只有电子，通过高迁移率的电子极大的增加了器件的频率和饱和特性。
所述非故意掺杂InGaAlAs渐变层4的厚度为20～100nm，截止波长1.1～1.5μm，掺杂浓度≤1×1016cm-3。
所述P型In0.52Al0.48As场控层5厚度为50～200nm，掺杂元素为碳(C)，掺杂浓度为5×1017cm-3～10×1017cm-3。
所述非故意掺杂In0.52Al0.48As倍增层6的厚度为50～300nm，掺杂浓度≤1×1016cm-3。
所述N型In0.52Al0.48As场控层7的厚度为50～300nm，掺杂元素为硅(Si)，掺杂浓度为1×1018cm-3～5×1018cm-3。
所述非故意掺杂In0.52Al0.48As缓冲层8的厚度为50～200nm，掺杂浓度≤1×1016cm-3。
所述N型In0.53Ga0.47As接触层9的厚度为50～100nm，掺杂元素为硅(Si)，掺杂浓度为5×1018cm-3～10×1018cm-3。
所述N型电极10的厚度为
Figure BDA0002387129880000091
金层为AuGeNi/Au。
所述P型电极11的厚度为
Figure BDA0002387129880000092
金层为Cr/Au或Ti/Pt/Au。
所述钝化层12采用三氧化二铝(Al2O3)，厚度为
Figure BDA0002387129880000093
如图3所示，本实施例的单电子传输雪崩光电二极管结构的制作方法包括以下步骤：
步骤S101、采用金属有机物化学气相淀积或分子束外延在InP半绝缘衬底1上依次生长P型InAlGaAs接触层2、P型In0.53Ga0.47As吸收层3、非故意掺杂InGaAlAs渐变层4、P型In0.52Al0.48As场控层5、非故意掺杂In0.52Al0.48As倍增层6、N型In0.52Al0.48As场控层7、N型In0.52Al0.48As缓冲层8和N型In0.53Ga0.47As接触层9；
步骤S102、采用光刻剥离工艺利用电子束蒸发或磁控溅射在N型In0.53Ga0.47As接触层9的上表面制作N型电极10；
步骤S103、采用干法刻蚀或湿法刻蚀将N型In0.53Ga0.47As接触层9竖直向下刻蚀至N型In0.52Al0.48As缓冲层8的上表面，形成第二层台面；
步骤S104、采用干法刻蚀或湿法刻蚀将第二层台面竖直向下刻蚀至非故意掺杂In0.52Al0.48As倍增层6的上表面，形成第三层台面；
步骤S105、采用干法刻蚀或湿法刻蚀将第三层台面竖直向下刻蚀至P型InAlGaAs接触层2的上表面，形成第四层台面；
步骤S106、在第二层台面、第三层台面和第四层台面上采用原子层沉积淀积三氧化二铝介质进行钝化，形成钝化层12，厚度为
Figure BDA0002387129880000101
采用原子层沉积的方式淀积三氧化二铝介质层对台面进行钝化，降低了器件表面漏电流，提高了器件可靠性；
步骤S107、通过光刻工艺在第四层台面上定义出光敏面、电极孔，采用光刻剥离工艺利用电子束蒸发或磁控溅射在第四层台面上制作P型电极11；
步骤S108、采用化学机械抛光的方式将P型电极11和N型电极10的外延片背面减薄至100～150μm后，解理成单元芯片。
所述干法刻蚀优选采用ICP干法刻蚀或RIE干法刻蚀；所述湿法刻蚀优选采用溴基溶液进行刻蚀。
实施例2：
如图4和图5所示，本发明单电子传输雪崩光电二极管结构的另一实施例包括InP半绝缘衬底1’,在所述InP半绝缘衬底1’上依次生长有N型In0.52Al0.48As接触层9’、非故意掺杂In0.52Al0.48As倍增层6’、P型In0.52Al0.48As场控层5’、非故意掺杂InGaAlAs渐变层4’、P型In0.53Ga0.47As吸收层3’和P型In0.53Ga0.47As接触层20，所述P型In0.53Ga0.47As接触层20连接有P型电极11’，所述N型In0.52Al0.48As接触层9’连接有N型电极10’。
所述光电二极管结构为三层台面的同心圆结构，第一层台面为P型In0.53Ga0.47As接触层20的上表面，第二层台面位于P型In0.53Ga0.47As吸收层3’的上表面，第三层台面位于N型In0.52Al0.48As接触层9’的上表面，所述P型电极11’覆盖在P型In0.53Ga0.47As接触层20的上表面，所述N型电极10’覆盖在第三层台面上，在所述第二层台面和第三层台面上设有钝化层12’。采用多层同心圆台面结构，稀释了台面侧壁电场强度，减小了表面漏电流，降低了器件暗电流，提高了可靠性。
所述N型In0.52Al0.48As接触层9’的厚度为50～300nm，掺杂元素为硅(Si)，掺杂浓度为5×1018cm-3～10×1018cm-3。
所述非故意掺杂In0.52Al0.48As倍增层6’的厚度为50～300nm，掺杂浓度≤1×1016cm-3。
所述P型In0.52Al0.48As场控层5’的厚度为50～200nm，掺杂元素为碳(C)，掺杂浓度为5×1017cm-3～10×1017cm-3。
所述非故意掺杂InGaAlAs渐变层4’的厚度为20～100nm，截止波长为1.1～1.5μm，掺杂浓度≤1×1016cm-3。
所述P型In0.53Ga0.47As吸收层3’的厚度为500～1500nm，掺杂元素为碳(C)，掺杂浓度为0.5×1018cm-3～5×1018cm-3或者为0.5×1018cm-3至5×1018cm-3渐变浓度掺杂；将In0.53Ga0.47As吸收层设计为P型掺杂，光生空穴为多子，其以驰豫过程参与载流子传输，发生载流子迁移的只有电子，通过高迁移率的电子极大的增加了器件的频率和饱和特性。
所述P型In0.53Ga0.47As接触层20的厚度为50～100nm，掺杂元素为碳(C)，掺杂浓度≥1×1019cm-3。
所述P型电极11’的厚度为
Figure BDA0002387129880000111
金层为Cr/Au或Ti/Pt/Au。
所述N型电极10’的厚度为
Figure BDA0002387129880000112
金层为AuGeNi/Au。
所述钝化层12’采用三氧化二铝(Al2O3)，厚度为
Figure BDA0002387129880000121
如图6所示，本实施例的单电子传输雪崩光电二极管结构的制作方法包括以下步骤：
步骤S201、采用金属有机物化学气相淀积或分子束外延在所述InP半绝缘衬底1’上依次生长N型In0.52Al0.48As接触层9’、非故意掺杂In0.52Al0.48As倍增层6’、P型In0.52Al0.48As场控层5’、非故意掺杂InGaAlAs渐变层4’、P型In0.53Ga0.47As吸收层3’和P型In0.53Ga0.47As接触层20；
步骤S202、采用光刻剥离工艺利用电子束蒸发或磁控溅射在P型In0.53Ga0.47As接触层20上制作P型电极11’；
步骤S203、采用干法刻蚀或湿法刻蚀将P型In0.53Ga0.47As接触层20的外沿竖直向下刻蚀至P型In0.53Ga0.47As吸收层3’的上表面，形成第二层台面；
步骤S204、采用干法刻蚀或湿法刻蚀将第二层台面的外沿竖直向下刻蚀至N型In0.52Al0.48As接触层9’的上表面，形成第三层台面；
步骤S205、在第二层台面和第三层台面上采用原子层沉积淀积三氧化二铝介质进行钝化，形成钝化层12’，厚度为
Figure BDA0002387129880000122
采用原子层沉积的方式淀积三氧化二铝介质层对台面进行钝化，降低了器件表面漏电流，提高了器件可靠性；
步骤S206、通过光刻工艺在第三层台面上定义出光敏面、电极孔，采用光刻剥离工艺利用电子束蒸发或磁控溅射在第三层台面上制作N型电极10’；
步骤S207、采用化学机械抛光的方式将P型电极11’和N型电极10’的外延片背面减薄至100～150μm后，解理成单元芯片。
所述干法刻蚀优选采用ICP干法刻蚀或RIE干法刻蚀；所述湿法刻蚀优选采用溴基溶液进行刻蚀。
本发明未描述部分与现有技术一致，在此不做赘述。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构，直接或间接运用在其他相关的技术领域，均同理在本发明的专利保护范围之内。

Claims (10)

1.一种单电子传输雪崩光电二极管结构，包括InP半绝缘衬底,其特征在于，在所述InP半绝缘衬底上依次生长有P型InAlGaAs接触层、P型In0.53Ga0.47As吸收层、非故意掺杂InGaAlAs渐变层、P型In0.52Al0.48As场控层、非故意掺杂In0.52Al0.48As倍增层、N型In0.52Al0.48As场控层、N型In0.52Al0.48As缓冲层和N型In0.53Ga0.47As接触层；所述N型In0.53Ga0.47As接触层连接有N型电极，所述P型InAlGaAs接触层连接有P型电极。
2.根据权利要求1所述的单电子传输雪崩光电二极管结构，其特征在于，所述光电二极管结构为四层台面的同心圆结构，第一层台面为N型In0.53Ga0.47As接触层的上表面，第二层台面位于N型In0.52Al0.48As缓冲层的上表面，第三层台面位于非故意掺杂In0.52Al0.48As倍增层的上表面，第四层台面位于P型InAlGaAs接触层的上表面，所述N型电极覆盖在N型In0.53Ga0.47As接触层的上表面，所述P型电极覆盖在第四层台面上，在第二层台面、第三层台面和第四层台面上设有钝化层。
3.根据权利要求1所述的单电子传输雪崩光电二极管结构，其特征在于，所述P型In0.53Ga0.47As吸收层为P型重掺杂，掺杂元素为碳，掺杂浓度为0.5×1018cm-3～5×1018cm-3或者为0.5×1018cm-3至5×1018cm-3渐变浓度掺杂，厚度为500～1500nm。
4.根据权利要求1所述的单电子传输雪崩光电二极管结构，其特征在于，所述非故意掺杂InGaAlAs渐变层的截止波长为1.1～1.5μm，掺杂浓度≤1×1016cm-3；所述P型In0.52Al0.48As场控层的掺杂元素为碳，掺杂浓度为5×1017cm-3～10×1017cm-3；所述非故意掺杂In0.52Al0.48As倍增层的掺杂浓度≤1×1016cm-3；所述N型In0.52Al0.48As场控层的掺杂元素为硅，掺杂浓度为1×1018cm-3～5×1018cm-3；所述N型In0.52Al0.48As缓冲层为非故意掺杂，掺杂浓度≤1×1016cm-3。
5.一种单电子传输雪崩光电二极管制作方法，其特征在于，包括以下步骤：
步骤S101、采用金属有机物化学气相淀积或分子束外延在InP半绝缘衬底上依次生长P型InAlGaAs接触层、P型In0.53Ga0.47As吸收层、非故意掺杂InGaAlAs渐变层、P型In0.52Al0.48As场控层、非故意掺杂In0.52Al0.48As倍增层、N型In0.52Al0.48As场控层、N型In0.52Al0.48As缓冲层和N型In0.53Ga0.47As接触层；
步骤S102、采用光刻剥离工艺利用电子束蒸发或磁控溅射在N型In0.53Ga0.47As接触层的上表面制作N型电极；
步骤S103、采用干法刻蚀或湿法刻蚀将N型In0.53Ga0.47As接触层上表面的外沿向下刻蚀至N型In0.52Al0.48As缓冲层的上表面，形成第二层台面；
步骤S104、采用干法刻蚀或湿法刻蚀将第二层台面的外沿向下刻蚀至非故意掺杂In0.52Al0.48As倍增层的上表面，形成第三层台面；
步骤S105、采用干法刻蚀或湿法刻蚀将第三层台面的外沿向下刻蚀至P型InAlGaAs接触层的上表面，形成第四层台面；
步骤S106、在第二层台面、第三层台面和第四层台面上采用原子层沉积淀积三氧化二铝介质进行钝化，形成钝化层；
步骤S107、通过光刻工艺在第四层台面上定义出光敏面、电极孔，采用光刻剥离工艺利用电子束蒸发或磁控溅射在第四层台面上制作P型电极；
步骤S108、采用化学机械抛光的方式将P型电极和N型电极的外延片背面减薄后，解理成单元芯片。
6.一种单电子传输雪崩光电二极管结构，包括InP半绝缘衬底,其特征在于，在所述InP半绝缘衬底上依次生长有N型In0.52Al0.48As接触层、非故意掺杂In0.52Al0.48As倍增层、P型In0.52Al0.48As场控层、非故意掺杂InGaAlAs渐变层、P型In0.53Ga0.47As吸收层和P型In0.53Ga0.47As接触层，所述P型In0.53Ga0.47As接触层连接有P型电极，所述N型In0.52Al0.48As接触层连接有N型电极。
7.根据权利要求6所述的单电子传输雪崩光电二极管结构，其特征在于，所述光电二极管结构为三层台面的同心圆结构，第一层台面为P型In0.53Ga0.47As接触层的上表面，第二层台面位于P型In0.53Ga0.47As吸收层的上表面，第三层台面位于N型In0.52Al0.48As接触层的上表面，所述P型电极覆盖在P型In0.53Ga0.47As接触层的上表面，所述N型电极覆盖在第三层台面上，在所述第二层台面和第三层台面上设有钝化层。
8.根据权利要求6所述的单电子传输雪崩光电二极管结构，其特征在于，所述P型In0.53Ga0.47As吸收层为P型重掺杂，掺杂元素为碳，掺杂浓度为0.5×1018cm-3～5×1018cm-3或者为0.5×1018cm-3至5×1018cm-3渐变浓度掺杂。
9.根据权利要求6所述的单电子传输雪崩光电二极管结构，其特征在于，所述非故意掺杂In0.52Al0.48As倍增层的掺杂浓度≤1×1016cm-3；所述非故意掺杂In0.52Al0.48As倍增层的掺杂浓度≤1×1016cm-3，所述P型In0.52Al0.48As场控层的掺杂元素为碳，掺杂浓度为5×1017cm-3～10×1017cm-3，所述非故意掺杂InGaAlAs渐变层的截止波长为1.1～1.5μm，掺杂浓度≤1×1016cm-3。
10.一种单电子传输雪崩光电二极管制作方法，其特征在于，包括以下步骤：
步骤S201、采用金属有机物化学气相淀积或分子束外延在所述InP半绝缘衬底上依次生长N型In0.52Al0.48As接触层、非故意掺杂In0.52Al0.48As倍增层、P型In0.52Al0.48As场控层、非故意掺杂InGaAlAs渐变层、P型In0.53Ga0.47As吸收层和P型In0.53Ga0.47As接触层；
步骤S202、采用光刻剥离工艺利用电子束蒸发或磁控溅射在P型In0.53Ga0.47As接触层的上表面制作P型电极；
步骤S203、采用干法刻蚀或湿法刻蚀将P型In0.53Ga0.47As接触层上表面的外沿向下刻蚀至P型In0.53Ga0.47As吸收层上表面，形成第二层台面；
步骤S204、采用干法刻蚀或湿法刻蚀将第二层台面的外沿向下刻蚀至N型In0.52Al0.48As接触层的上表面，形成第三层台面；
步骤S205、在第二层台面和第三层台面上采用原子层沉积淀积三氧化二铝介质进行钝化，形成钝化层；
步骤S206、通过光刻工艺在第三层台面上定义出光敏面、电极孔，采用光刻剥离工艺利用电子束蒸发或磁控溅射在第三层台面上制作N型电极；
步骤S207、采用化学机械抛光的方式将P型电极和N型电极的外延片背面减薄后，解理成单元芯片。
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