CN111308194A - Frequency characteristic tester - Google Patents
Frequency characteristic tester Download PDFInfo
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- CN111308194A CN111308194A CN201911242471.2A CN201911242471A CN111308194A CN 111308194 A CN111308194 A CN 111308194A CN 201911242471 A CN201911242471 A CN 201911242471A CN 111308194 A CN111308194 A CN 111308194A
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
- G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
Abstract
The application discloses frequency characteristic tester, including the host computer, FPGA control module, transmission module, AD acquisition module and DA conversion module, the host computer is configured with dot-frequency signal production module, frequency characteristic analysis module, dot-frequency signal production module passes through MATLAB and generates dot-frequency signal, frequency characteristic analysis module receives FPGA module's data and carries out frequency characteristic analysis through MATLAB, FPGA control module realizes the buffer memory of communication protocol and data of each module, transmission module, be configured as the data transmission passageway between frequency characteristic analysis module and the FPGA control module, AD acquisition module, be configured as analog signal conversion digital signal, DA conversion module, be configured as digital signal conversion analog signal. The frequency characteristic tester disclosed by the invention can realize high-speed processing and analysis of data, and can visually observe the waveform, thereby facilitating the analysis of data results.
Description
Technical Field
The present disclosure relates to the field of frequency testing technology, and more particularly, to a frequency characteristic tester.
Background
Currently, frequency characteristic measuring instruments can be roughly classified into two types: one is traditional equipment, is easy to break down and complex to operate, and cannot meet the requirements of field tests of engineering personnel; the other is a novel device integrating data acquisition and operation, which is generally an imported product, and is expensive and difficult to maintain. The FPGA (Field-Programmable-Gate-Array) device has rich internal resources and high integration level, and a user can customize a circuit through programming, so that the flexibility is good; the input, the compiling synthesis and the simulation test can be conveniently designed through special design software of a computer, and a preset circuit is designed; the parallel operation mode is adopted in the chip, the operation of large data volume can be rapidly completed, but signals in a hardware circuit are output in a binary mode, the visibility is poor, and result analysis is inconvenient.
Disclosure of Invention
In view of this, the present disclosure provides a frequency characteristic tester, which includes an upper computer, an FPGA control module, a transmission module, an AD acquisition module, and a DA conversion module; the upper computer is provided with a dot frequency signal generating module and a frequency characteristic analyzing module;
the first input and output end of the FPGA control module is electrically connected with the transmission module and is in data communication with the upper computer through the transmission module;
the output end of the FPGA control module is electrically connected with the input end of the DA conversion module, and the output end of the DA conversion module is suitable for being electrically connected with a system to be tested;
the input end of the FPGA control module is electrically connected with the output end of the AD acquisition module, and the input end of the AD acquisition module is suitable for being electrically connected with the system to be tested;
the dot frequency signal generating module is configured to generate dot frequency signals through MATLAB and output the dot frequency signals to the FPGA control module through the transmission module; the step, the sampling point, the sampling frequency, the starting frequency and the ending frequency of the dot frequency signal are set values;
the FPGA control module is configured to receive the dot frequency signal output by the dot frequency signal generation module through the transmission module and input the dot frequency signal to the DA conversion module;
the DA conversion module is configured to receive the dot frequency signal output by the FPGA control module and convert the dot frequency signal into an analog signal to be input to the system to be tested;
the AD acquisition module is configured to receive a response signal output by the system to be tested, convert the response signal into a digital signal and transmit the digital signal to the FPGA control module;
the FPGA control module is further configured to receive the digital signal output by the AD acquisition module and input the digital signal to the frequency characteristic analysis module through the transmission module;
the frequency characteristic analysis module is configured to receive the digital signal output by the FPGA module through the transmission module and perform frequency characteristic analysis through MATLAB.
In one possible implementation manner, the DA conversion module includes a digital-to-analog conversion unit, a filter unit, and an amplitude adjustment unit;
the digital-to-analog conversion unit is electrically connected with the output end of the FPGA control module;
the input end of the filter unit is electrically connected with the output end of the digital-to-analog conversion unit;
the output end of the filter unit is electrically connected with the input end of the amplitude adjusting unit;
the output end of the amplitude adjusting unit is suitable for being electrically connected with the system to be tested;
the digital-to-analog conversion unit is configured to receive the dot frequency signal output by the FPGA control module, convert the dot frequency signal into the analog signal, and output the analog signal to the filter unit;
the filter unit is configured to receive the analog signal output by the digital-to-analog conversion unit, remove noise of the analog signal, and output the analog signal to the amplitude adjustment unit;
the amplitude adjusting unit is configured to receive the analog signal output by the filter unit, adjust the amplitude of the analog signal to a first specific value, and output the analog signal to the system under test; wherein the range of first specific values is: -5V.
In one possible implementation manner, the AD acquisition module includes an AD conversion unit and an attenuation circuit unit;
the input end of the attenuation circuit unit is suitable for being electrically connected with the system to be tested;
the input end of the AD conversion unit is electrically connected with the output end of the attenuation circuit unit;
the output end of the AD conversion unit is electrically connected with the FPGA control module;
the attenuation circuit unit is configured to receive a response signal of the system under test, convert the level of the response signal to a second specific value, and output the response signal to the AD conversion unit;
the AD conversion unit is configured to receive the response signal output by the attenuation circuit unit, convert the response signal into a digital signal, and output the digital signal to the FPGA control module;
wherein, the AD conversion unit comprises an AD conversion chip, and the range of the second specific value is as follows: 1V-3V.
In one possible implementation, the attenuation circuit unit includes a first capacitor group, a diode group, an operational amplifier group, and a first resistor group;
the first resistor group comprises a first resistor part, a second resistor part and a third resistor part;
the operational amplifier group comprises a first operational amplifier, a second operational amplifier and a third operational amplifier;
the first resistance portion is electrically connected to the AD conversion unit;
the second resistance portion is electrically connected to the first operational amplifier;
the third resistive portion is electrically connected to the third operational amplifier;
the first capacitor bank is electrically connected with the AD conversion unit;
the diode group is electrically connected with the first operational amplifier.
In one possible implementation manner, the amplitude adjusting unit includes a second capacitor set, an inductor set, a second resistor set, and a fourth operational amplifier;
the second resistor group comprises a fourth resistor part and a fifth resistor part;
the inductance group comprises a first inductance part and a second inductance part;
the second capacitance group comprises a first capacitance part and a second capacitance part;
the fourth resistance portion is electrically connected with the positive input end of the fourth operational amplifier;
the first inductance part is electrically connected with the positive input end of the fourth operational amplifier;
the first capacitor part is electrically connected with the positive input end of the fourth operational amplifier;
the fifth resistance part is electrically connected with the negative input end of the fourth operational amplifier;
the second inductance part is electrically connected with the negative input end of the fourth operational amplifier;
the second capacitance section is electrically connected to a negative input terminal of the fourth operational amplifier.
In one possible implementation, the transmission module includes a USB interface;
the USB interface is a USB3.0 interface;
the USB interface is of a Micro B interface type.
In one possible implementation manner, the frequency characteristic analysis module includes an amplitude-frequency characteristic analysis unit, a phase-frequency characteristic analysis unit, and a GUI unit;
the amplitude-frequency characteristic analysis unit is configured to detect the amplitude of the input signal;
the phase-frequency characteristic analysis unit is configured to detect a difference value of phases of an output signal and an input signal;
and the GUI unit is configured to display the analysis results of the amplitude-frequency characteristics and the phase-frequency characteristics through a graphical interface of the MATLAB.
In a possible implementation manner, the system further comprises an SMA interface and a BNC interface;
the SMA interface receives a voltage signal of-5V and inputs the voltage signal into the AD acquisition module.
In one possible implementation manner, the digital-to-analog conversion unit includes a DA conversion chip; the filter unit is a butterworth low-pass filter.
In one possible implementation, the communication protocol includes a GPIF II protocol.
The utility model discloses a frequency characteristic tester, including the host computer, FPGA control module, transmission module, AD acquisition module and DA conversion module, the host computer is configured with dot-frequency signal generation module, frequency characteristic analysis module, dot-frequency signal generation module, be configured to generate dot-frequency signal through MATLAB, frequency characteristic analysis module, be configured to receive FPGA module's data and carry out frequency characteristic analysis through MATLAB, FPGA control module, be configured to realize the communication protocol of each module and the buffer memory of data, transmission module, be configured as the data transmission passageway between frequency characteristic analysis module and the FPGA control module, AD acquisition module, be configured to convert analog signal into digital signal, DA conversion module, be configured to convert digital signal into analog signal. The frequency characteristic tester disclosed by the invention can realize high-speed processing and analysis of data, and can visually observe the waveform, thereby facilitating the analysis of data results.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.
Fig. 1 shows a block diagram of a frequency characteristic tester of an embodiment of the present disclosure;
FIG. 2 shows a schematic diagram of a frequency characteristic tester of an embodiment of the present disclosure;
fig. 3 shows a hardware device block diagram of a frequency characteristic tester of an embodiment of the present disclosure;
FIG. 4 illustrates a schematic diagram of a transmission module of a frequency characteristic tester of an embodiment of the present disclosure;
fig. 5 shows a state transition diagram of a USB interface of the frequency characteristic tester of the embodiment of the present disclosure;
FIG. 6 shows a GPIF II interface configuration diagram for a frequency characteristic tester of an embodiment of the present disclosure;
fig. 7 shows an attenuation circuit of the frequency characteristic tester of the embodiment of the present disclosure;
fig. 8 shows an amplitude adjustment circuit of the frequency characteristic tester of the embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.
Fig. 1 shows a schematic diagram of a frequency characteristic tester 100 according to an embodiment of the present disclosure. As shown in fig. 1, the frequency characteristic tester 100 includes:
the system comprises an upper computer, an FPGA control module 140, a transmission module 130, an AD acquisition module 160 and a DA conversion module 150; the upper computer is provided with a dot frequency signal generating module 110 and a frequency characteristic analyzing module 120, a first input/output end of the FPGA control module 140 is electrically connected with the transmission module 130 and is in data communication with the upper computer through the transmission module 130, an output end of the FPGA control module 140 is electrically connected with an input end of the DA conversion module 150, an output end of the DA conversion module 150 is suitable for being electrically connected with a system to be tested, an input end of the FPGA control module 140 is electrically connected with an output end of the AD acquisition module 160, an input end of the AD acquisition module 160 is suitable for being electrically connected with the system to be tested, and the dot frequency signal generating module 110 is configured to generate a dot frequency signal through MATLAB and output the dot frequency signal to the DA conversion module 150 through the; wherein, the step, the sampling point, the sampling frequency, the start frequency and the end frequency of the dot frequency signal are set values, the FPGA control module 140 is configured to receive the dot frequency signal output by the dot frequency signal generating module 110 through the transmission module 130, and inputs the dot frequency signal to the DA conversion module 150, the DA conversion module 150 is configured to receive the dot frequency signal output by the FPGA control module 140 and convert the dot frequency signal into an analog signal to be input to the system under test, the AD acquisition module 160 is configured to receive a response signal from the system under test, and converts the response signal into a digital signal and transmits the digital signal to the FPGA control module 140, and is further configured to receive the digital signal output by the AD collecting module 160, and inputs the digital signal to the frequency characteristic analysis module 120 through the transmission module 130, and the frequency characteristic analysis module 120 is configured to receive the digital signal output by the FPGA module through the transmission module 130 and perform frequency characteristic analysis through MATLAB.
The frequency characteristic tester 100 of the present disclosure includes an upper computer, an FPGA control module 140, a transmission module 130, an AD acquisition module 160, and a DA conversion module 150, wherein the upper computer is configured with a dot frequency signal generation module 110 and a frequency characteristic analysis module 120. The system comprises a dot frequency signal generating module 110 configured to generate dot frequency signals through MATLAB, a frequency characteristic analyzing module 120 configured to receive data of the FPGA module and perform frequency characteristic analysis through the MATLAB, an FPGA control module 140 configured to implement communication protocols of the modules and buffer of the data, a transmission module 130 configured to be a data transmission channel between the frequency characteristic analyzing module 120 and the FPGA control module 140, an AD acquisition module 160 configured to convert analog signals into digital signals, and a DA conversion module 150 configured to convert digital signals into analog signals. The frequency characteristic tester 100 of the present disclosure can realize high-speed processing and analysis of data, and can visually observe a waveform, facilitating analysis of a data result.
Referring to fig. 1, the upper computer includes a dot frequency signal generation module 110 configured to generate a dot frequency signal by MATLAB; the step, the sampling point, the sampling frequency, the starting frequency and the ending frequency of the dot frequency signal are set values.
In one possible implementation, the parameters of the dot frequency signal to be transmitted, including the step, the sampling point, the sampling frequency, the start frequency, and the end frequency, are set in a personal computer in which MATLAB is installed.
It should be noted that, when measuring the system frequency characteristic, the center frequency output of the dot frequency signal should be adjusted according to the measured system passband, so that the range of the dot frequency signal covers the measured system passband.
Further, the upper computer further includes a frequency characteristic analysis module 120 configured to receive the output data of the FPGA module and perform frequency characteristic analysis through MATLAB.
In one possible implementation, the frequency characteristic analysis module 120 includes an amplitude-frequency characteristic analysis unit configured to detect an amplitude of the input signal, a phase-frequency characteristic analysis unit configured to detect a difference value of phases of the output signal and the input signal, and a GUI unit configured to display analysis results of the amplitude-frequency characteristic and the phase-frequency characteristic through a graphical interface of MATLAB. Referring to fig. 2, the frequency characteristic tester 100 of the present disclosure performs frequency characteristic detection by using a digital method, and since an excitation signal of a system under test is generated by an upper computer (i.e., a personal computer equipped with MATLAB), and is not required to be digitized, only a response signal output by the system needs to be acquired by an ADC (analog-to-digital converter) and transmitted to the upper computer. Since the amplitude-frequency characteristic is the ratio of the amplitudes of the response signal to the excitation signal over a certain frequency range, a central problem for the amplitude-frequency characteristic analysis in MATLAB is signal amplitude detection. The amplitude of a signal in a certain frequency range is detected in MATLAB, which is characterized in that an extreme point of signal waveform change is analyzed, a value corresponding to the maximum point is the peak position of the signal of the current frequency, a value corresponding to the minimum point is the trough position of the signal of the current frequency, and the difference between the adjacent maximum value and the adjacent minimum value is the peak-to-peak value of the signal. The method comprises the steps of detecting a difference value of phases of a system output signal and an input signal in a certain frequency range in MATLAB, essentially detecting a time difference between two signal peak values, and converting the time difference into a phase difference. For example: the MATLAB program can be divided into the following steps: data normalization processing, sine fitting, conversion and communication delay compensation, amplitude gain calibration, zero-crossing moment judgment and interpolation processing. The conversion and communication delay compensation, that is, the output voltage of the DA conversion module 150 and the data in the AD acquisition module 160 at the same time are obtained, the phase difference is analyzed according to the output voltage and the acquired data, and the phase difference is also considered while analyzing the phase, where the delay in the hardware includes: the conversion time of the DA conversion module 150, the acquisition time of the AD acquisition module 160, the communication time of the FPGA control module with the AD acquisition module 160 and the DA conversion module 150, and the transmission time of the modules. The amplitude gain calibration, that is, different voltages are required for different circuits to be tested, in order to ensure the accuracy of the DA conversion module 150, a voltage adjustment point positioner may be used at the output end of the DA conversion module 150, and after the adjustment is completed, the amplification factor of the signal from the DA conversion module 150 to the AD acquisition module 160 is recalibrated. The zero-crossing time is determined and interpolated, that is, in the phase difference analysis, the phase of the signal passing through the DA conversion module 150 and the phase of the signal in the AD acquisition module 160 need to be obtained, the phase of the signal in the DA conversion module 150 is known, the signal in the AD acquisition module 160 is a discrete time signal, the occurrence of the zero-crossing condition (the rising zero-crossing is 0 degree, and the falling zero-crossing is 180 degrees) in the two sampling intervals can be analyzed, and in the two sampling intervals, the accurate zero-crossing time is calculated by analyzing the data averaged by the pole point, the inflection point and the interpolation after data fitting, so as to obtain the phase in the AD acquisition module 160.
It should be noted that the normalization and sine fitting of the data are performed by a common method, i.e. by using a self-contained function in MATLAB, and are not described herein again.
Referring to fig. 1, the hardware module includes an FPGA control module 140, a transmission module 130, an AD collection module 160 and a DA conversion module 150, wherein the transmission module 130 is electrically connected to a first input/output end of the FPGA control module 140, and performs data communication with an upper computer through the transmission module 130, an output end of the FPGA control module 140 is electrically connected to an input end of the DA conversion module 150, an output end of the DA conversion module 150 is adapted to be electrically connected to a system to be tested, an input end of the FPGA control module 140 is electrically connected to an output end of the AD collection module 160, and an input end of the AD collection module 160 is adapted to be electrically connected to the system to.
The FPGA control module 140 is configured to receive the dot frequency signal output by the dot frequency signal generating module 110 through the transmission module 130 and input the dot frequency signal to the DA converting module 150, and is further configured to receive the digital signal output by the AD collecting module 160 and input the digital signal to the frequency characteristic analyzing module 120 through the transmission module 130.
In one possible implementation, the FPGA control module includes RAM1 and RAM2, such as: the data transmission between the PC end and the FPGA is realized by adopting a Slave FIFO interface design, the FPGA reads data sent by the PC end through the Slave FIFO interface and caches the data into an RAM1 inside the FPGA, then the data cached in the RAM1 is converted and transmitted to a system to be tested through a DAC (digital-to-analog converter), response signals are collected by the ADC and cached into the RAM2, the write-in operation of the Slave FIFO is initiated after the collection is finished, and finally the collected data is sent to the PC end for analysis and processing.
Referring to fig. 1, the transmission module 130 is configured as a data transmission channel between the dot frequency signal generation module and the FPGA control module 140, and is also configured as a data transmission channel between the frequency characteristic analysis module and the FPGA control module 140, and the transmission module 130 is electrically connected to the upper computer.
In one possible implementation manner, referring to fig. 3, the transmission module 130 includes a USB interface, where the USB interface is a USB3.0 interface, and the USB interface is a Micro B interface.
The READ/write state transition of the USB controller is as shown in fig. 5, the initial state is FXS _ REST, and then the state is FXS _ IDLE, when the READ flag bit is valid, the state is FXS _ READ to READ data, when the data is READ, the state is FXS _ RDLY delayed slightly, then the state is FXS _ RSOP to stay for one clock cycle, then the state is FXS _ WAIT to WAIT for all data to be transmitted to the system under test and processed, and then the state is returned to FXS _ IDLE. The write flag bit is valid when data processing is complete, enters FXS _ WRIT state, see FIG. 4, writes the just read data into the SlaveFIFO of FX3, then enters FXS _ RSOP state for one clock cycle, and finally returns to FX3_ IDLE state.
Referring to FIG. 4, the present design selects FX3 synchronous SlaveFIFO transfer mode to meet the high throughput requirement and increase the data transfer rate. The GPIF II interface configuration is as shown in fig. 6, where the data width is set to 32 bits, the flag bit is set to the Current _ thread _ DMA _ Ready mode, and the flag bit is set to the Current _ thread _ DMA _ WaterMark mode. The FX3 clock signal is generated and provided by the FPGA, and is set to 100Mhz here; the SLOE is an interface enabling signal, and when the SLOE signal is enabled, the FX3 is in communication connection with the FPGA device; the SLCS signal is a slave device selection signal, a high level indicates that the slave device is selected; SLWR is a write enable signal that FX3 can write data to the FPGA device when enabled; SLRD is a read enable signal that FX3 may read data from the FPGA device when enabled; PKEND is a short packet sending signal, when the signal is enabled, any data volume smaller than the maximum transmission packet is supported to be transmitted, and FLAGA and FLAGB are used for marking whether the FIFO of the FPGA is full or empty.
Referring to fig. 1, the AD acquisition module 160 is configured to receive a response signal from the system under test, convert the response signal into a digital signal, and transmit the digital signal to the FPGA control module 140.
In one possible implementation manner, referring to fig. 3, the AD acquisition module 160 includes an AD conversion unit 1601, an attenuation circuit unit 1602, the AD conversion unit 1601 configured to convert an analog signal into a digital signal through an AD conversion chip, the attenuation circuit unit 1602 configured to convert a received analog signal into a second specific value; wherein the range of the second specific value is: 1V-3V. For example: the AD conversion chip can be AD9226, and after the analog signal passes through the attenuation circuit, the voltage range of the signal is within 1V-3V and enters AS 9226.
Further, referring to fig. 7, the attenuation circuit unit 1602 includes a first capacitor group including a first capacitor C30, a second capacitor C31, a third capacitor C32, a fourth capacitor C33, a fifth capacitor C34 and a sixth capacitor C35, a diode group including a first diode D4 and a second diode D5, an operational amplifier group including a first operational amplifier U4, a second operational amplifier U6A and a third operational amplifier U6B, and a first resistor group including a first resistor R19, a second resistor R20, a third resistor R18, a fourth resistor R21, a fifth resistor R22, a sixth resistor R23, a seventh resistor R24, an eighth resistor R25 and a ninth resistor R27. One end of a first resistor R19 is electrically connected to the output pin of the first operational amplifier U4, the other end of the first resistor R19 is electrically connected to the AD conversion chip, one end of a second resistor R20 is electrically connected to the first capacitor C30, the other end of the second resistor R20 is electrically connected to the AD conversion chip, one end of a third resistor R18 is electrically connected to the positive input terminal of the first operational amplifier U4, the other end of the third resistor R18 is electrically connected to the system under test, one end of a fourth resistor R21 is electrically connected to the positive input terminal of the first operational amplifier U4, the other end of the fourth resistor R21 is electrically connected to the ground terminal, one end of a fifth resistor R22 is electrically connected to the ground terminal, the other end of the fifth resistor R22 is electrically connected to the AD conversion chip, one end of a sixth resistor R23 is electrically connected to the output pin of the first operational amplifier U4, the other end of the sixth resistor R23 is electrically connected to the negative input terminal of, one end of a seventh resistor R24 is electrically connected to the negative input terminal of the first operational amplifier U4, the other end of the seventh resistor R24 is electrically connected to the output pin of the third operational amplifier U6B, one end of an eighth resistor R25 is electrically connected to the output pin of the second operational amplifier U6A, the other end of the eighth resistor R25 is electrically connected to the negative input terminal of the third operational amplifier U6B, one end of a ninth resistor R27 is electrically connected to the negative input terminal of the third operational amplifier U6B, a ninth resistor R27 is electrically connected to the output pin of the third operational amplifier U6B, a first capacitor C30 and a second capacitor C31 are connected in parallel between the ground terminal and the AD conversion chip, a third capacitor C32 and a fourth capacitor C33 are connected in parallel between one end of a sixth capacitor C35 and the AD conversion chip, a fourth capacitor C33 is connected in parallel between the ground terminal and the AD conversion chip, one end of a fifth capacitor C34 is electrically connected to the ground terminal, the other end of the fifth capacitor C34 is electrically connected to the fourth capacitor C33, one end of a sixth capacitor C35 is electrically connected to the AD conversion chip, the other end of the sixth capacitor C35 is electrically connected to the ground, the cathode of the first diode D4 is electrically connected to the positive input terminal of the first operational amplifier U4, the anode of the first diode D4 is electrically connected to the negative input terminal of the first operational amplifier U4, the cathode of the second diode D5 is electrically connected to the negative input terminal of the first operational amplifier U4, the anode of the second diode D5 is electrically connected to the positive input terminal of the first operational amplifier U4, the positive input terminal of the second operational amplifier U6A is electrically connected to the AD conversion chip, the negative input terminal of the second operational amplifier U6A is electrically connected to the output pin of the second operational amplifier U6A, and the positive input terminal of the third operational amplifier U6B is electrically connected to the ground.
In addition, referring to fig. 3, the AD acquisition module 160 further includes an SMA interface 1603, where the SMA interface 1603 is mainly responsible for transmitting a voltage signal between +5V and-5V; when the signal is input into a system, the signal is processed by an attenuation circuit, so that the amplitude of the signal is changed into 1V-3V to meet the input voltage requirement of an AD9226 chip; finally, the AD9226 analog-to-digital conversion chip converts the input analog signal into a digital signal for the analysis and processing of the FPGA control module 140.
Referring to fig. 1, the DA conversion module 150 is configured to receive the dot frequency signal output by the FPGA control module 140 and convert the dot frequency signal into an analog signal to be input to the system under test.
In one possible implementation, referring to fig. 3, the DA conversion module 150 includes a digital-to-analog conversion unit 1501, a filter unit 1502, and an amplitude adjustment unit 1503, wherein the digital-to-analog conversion unit 1501 is configured to convert a digital signal into an analog signal, the filter unit 1502 is configured to remove noise of the analog signal, and the amplitude adjustment unit 1503 is configured to adjust an amplitude of the analog signal to a first specific value; wherein the range of the first specific value is: -5V. For example: the DA conversion chip may be AD9708, and the filter unit 1502 is a seven-order butterworth low pass filter. Differential signals are output from the IOUTA and IOUTB pins of the DA conversion chip, and in order to prevent the differential signals from being interfered by noise, the differential signals are connected into a seven-order Butterworth low-pass filter and finally connected into an amplitude adjusting unit 1503.
Further, referring to fig. 8, the amplitude adjusting unit 1503 includes a second capacitor group, an inductor group, a second resistor group, and a fourth operational amplifier U12, wherein the second capacitor group includes a seventh capacitor C42, an eighth capacitor C43, a ninth capacitor C44, a tenth capacitor C45, an eleventh capacitor C47, a twelfth capacitor C48, a thirteenth capacitor C48, and a fourteenth capacitor C48, the inductor group includes a first inductor L48, a second inductor L48, a third inductor L48, a fourth inductor L48, a fifth inductor L48, and a sixth inductor L48, the second resistor group includes a tenth resistor R48, an eleventh resistor R48, a twelfth resistor R48, a thirteenth resistor R48, a fourteenth resistor R48, a fifteenth resistor R48, a sixteenth resistor R48, a seventeenth resistor R48, and an eighteenth resistor R48, the tenth resistor R48, the seventh resistor R48, the eighth resistor C48, the eleventh capacitor C48, the tenth capacitor C48, the, a fifteenth resistor R46, an eleventh capacitor C47, a twelfth capacitor C48, a thirteenth capacitor C49, a fourteenth capacitor C50 and a sixteenth resistor R45 are connected in parallel between the DA conversion chip and one end of a seventeenth resistor R44, the other end of the twelfth resistor R41 is electrically connected to the positive input terminal of the fourth operational amplifier U12, the other end of the seventeenth resistor R44 is electrically connected to the negative input terminal of the fourth operational amplifier U12, one end of the thirteenth resistor R40 is electrically connected to the positive input terminal of the fourth operational amplifier U12, the other end of the thirteenth resistor R40 is electrically connected to the ground terminal, one end of the eighteenth resistor R47 is electrically connected to the negative input terminal of the fourth operational amplifier U12, the other end of the eighteenth resistor R47 is electrically connected to the output pin of the fourth operational amplifier U12, one end of the fourteenth resistor R43 is electrically connected to the output pin of the fourth operational amplifier U12, and the other end of the fourteenth resistor R43 is electrically connected to the system under test. In addition, a BNC interface 1504 is included, and the BNC interface 1504 receives the analog signal and transmits the analog signal to an amplitude adjustment unit 1503.
It should be noted that, although the frequency characteristic tester 100 of the present disclosure has been described above as an example, those skilled in the art will appreciate that the present disclosure should not be limited thereto. In fact, the user can flexibly set the frequency characteristic tester 100 according to personal preference and/or actual application scenarios as long as the desired functions are achieved.
In this way, the frequency characteristic tester 100 of the present disclosure includes an upper computer, an FPGA control module 140, a transmission module 130, an AD acquisition module 160, and a DA conversion module 150, wherein the upper computer is configured with a dot frequency signal generation module 110 and a frequency characteristic analysis module 120. The system comprises a dot frequency signal generating module 110 configured to generate dot frequency signals through MATLAB, a frequency characteristic analyzing module 120 configured to receive data of the FPGA module and perform frequency characteristic analysis through the MATLAB, an FPGA control module 140 configured to implement communication protocols of the modules and buffer of the data, a transmission module 130 configured to be a data transmission channel between the frequency characteristic analyzing module 120 and the FPGA control module 140, an AD acquisition module 160 configured to convert analog signals into digital signals, and a DA conversion module 150 configured to convert digital signals into analog signals. The frequency characteristic tester 100 of the present disclosure can realize high-speed processing and analysis of data, and can visually observe a waveform, facilitating analysis of a data result.
Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (10)
1. A frequency characteristic tester is characterized by comprising an upper computer, an FPGA control module, a transmission module, an AD acquisition module and a DA conversion module; the upper computer is provided with a dot frequency signal generating module and a frequency characteristic analyzing module;
the first input and output end of the FPGA control module is electrically connected with the transmission module and is in data communication with the upper computer through the transmission module;
the output end of the FPGA control module is electrically connected with the input end of the DA conversion module, and the output end of the DA conversion module is suitable for being electrically connected with a system to be tested;
the input end of the FPGA control module is electrically connected with the output end of the AD acquisition module, and the input end of the AD acquisition module is suitable for being electrically connected with the system to be tested;
the dot frequency signal generating module is configured to generate dot frequency signals through MATLAB and output the dot frequency signals to the FPGA control module through the transmission module; the step, the sampling point, the sampling frequency, the starting frequency and the ending frequency of the dot frequency signal are set values;
the FPGA control module is configured to receive the dot frequency signal output by the dot frequency signal generation module through the transmission module and input the dot frequency signal to the DA conversion module;
the DA conversion module is configured to receive the dot frequency signal output by the FPGA control module and convert the dot frequency signal into an analog signal to be input to the system to be tested;
the AD acquisition module is configured to receive a response signal output by the system to be tested, convert the response signal into a digital signal and transmit the digital signal to the FPGA control module;
the FPGA control module is further configured to receive the digital signal output by the AD acquisition module and input the digital signal to the frequency characteristic analysis module through the transmission module;
the frequency characteristic analysis module is configured to receive the digital signal output by the FPGA module through the transmission module and perform frequency characteristic analysis through MATLAB.
2. The frequency characteristic tester of claim 1, wherein the DA conversion module includes a digital-to-analog conversion unit, a filter unit, and an amplitude adjustment unit;
the digital-to-analog conversion unit is electrically connected with the output end of the FPGA control module;
the input end of the filter unit is electrically connected with the output end of the digital-to-analog conversion unit;
the output end of the filter unit is electrically connected with the input end of the amplitude adjusting unit;
the output end of the amplitude adjusting unit is suitable for being electrically connected with the system to be tested;
the digital-to-analog conversion unit is configured to receive the dot frequency signal output by the FPGA control module, convert the dot frequency signal into the analog signal, and output the analog signal to the filter unit;
the filter unit is configured to receive the analog signal output by the digital-to-analog conversion unit, remove noise of the analog signal, and output the analog signal to the amplitude adjustment unit;
the amplitude adjusting unit is configured to receive the analog signal output by the filter unit, adjust the amplitude of the analog signal to a first specific value, and output the analog signal to the system under test; wherein the range of first specific values is: -5V.
3. The frequency characteristic tester of claim 2, wherein the AD acquisition module includes an AD conversion unit, an attenuation circuit unit;
the input end of the attenuation circuit unit is suitable for being electrically connected with the system to be tested;
the input end of the AD conversion unit is electrically connected with the output end of the attenuation circuit unit;
the output end of the AD conversion unit is electrically connected with the FPGA control module;
the attenuation circuit unit is configured to receive a response signal of the system under test, convert the level of the response signal to a second specific value, and output the response signal to the AD conversion unit;
the AD conversion unit is configured to receive the response signal output by the attenuation circuit unit, convert the response signal into a digital signal, and output the digital signal to the FPGA control module;
wherein, the AD conversion unit comprises an AD conversion chip, and the range of the second specific value is as follows: 1V-3V.
4. The frequency characteristic tester of claim 3, wherein the attenuation circuit unit includes a first capacitor group, a diode group, an operational amplifier group, and a first resistor group;
the first resistor group comprises a first resistor part, a second resistor part and a third resistor part;
the operational amplifier group comprises a first operational amplifier, a second operational amplifier and a third operational amplifier;
the first resistance portion is electrically connected to the AD conversion unit;
the second resistance portion is electrically connected to the first operational amplifier;
the third resistive portion is electrically connected to the third operational amplifier;
the first capacitor bank is electrically connected with the AD conversion unit;
the diode group is electrically connected with the first operational amplifier.
5. The frequency characteristic tester of claim 2, wherein the amplitude adjustment unit includes a second capacitance group, an inductance group, a second resistance group, and a fourth operational amplifier;
the second resistor group comprises a fourth resistor part and a fifth resistor part;
the inductance group comprises a first inductance part and a second inductance part;
the second capacitance group comprises a first capacitance part and a second capacitance part;
the fourth resistance portion is electrically connected with the positive input end of the fourth operational amplifier;
the first inductance part is electrically connected with the positive input end of the fourth operational amplifier;
the first capacitor part is electrically connected with the positive input end of the fourth operational amplifier;
the fifth resistance part is electrically connected with the negative input end of the fourth operational amplifier;
the second inductance part is electrically connected with the negative input end of the fourth operational amplifier;
the second capacitance section is electrically connected to a negative input terminal of the fourth operational amplifier.
6. The frequency characteristic tester of claim 1, wherein the transmission module includes a USB interface;
the USB interface is a USB3.0 interface;
the USB interface is of a Micro B interface type.
7. The frequency characteristic tester as claimed in claim 1, wherein the frequency characteristic analyzing module includes an amplitude-frequency characteristic analyzing unit, a phase-frequency characteristic analyzing unit, and a GUI unit;
the amplitude-frequency characteristic analysis unit is configured to detect the amplitudes of the output signal and the input signal;
the phase-frequency characteristic analysis unit is configured to detect a difference value of phases of an output signal and an input signal;
and the GUI unit is configured to display the analysis results of the amplitude-frequency characteristics and the phase-frequency characteristics through a graphical interface of the MATLAB.
8. The frequency characteristic tester of claim 1, further comprising an SMA interface and a BNC interface;
the SMA interface receives a voltage signal of-5V and inputs the voltage signal into the AD acquisition module.
9. The frequency characteristic tester of claim 2, wherein the digital-to-analog conversion unit includes a DA conversion chip; the filter unit is a butterworth low-pass filter.
10. The frequency characteristic tester of claim 1, wherein the communication protocol comprises a GPIF II protocol.
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| CN201911242471.2A CN111308194A (en) | 2019-12-06 | 2019-12-06 | Frequency characteristic tester |
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| CN201911242471.2A CN111308194A (en) | 2019-12-06 | 2019-12-06 | Frequency characteristic tester |
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