CN111293102A - 一种基板混合薄膜多层布线制作方法 - Google Patents

一种基板混合薄膜多层布线制作方法 Download PDF

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CN111293102A
CN111293102A CN202010107752.3A CN202010107752A CN111293102A CN 111293102 A CN111293102 A CN 111293102A CN 202010107752 A CN202010107752 A CN 202010107752A CN 111293102 A CN111293102 A CN 111293102A
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丁蕾
陈靖
刘凯
陈韬
马军伟
李虎
王立春
宋晓东
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Shanghai Aerospace Electronic Communication Equipment Research Institute
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Abstract

本发明公开了一种基板混合薄膜多层布线制作方法,该制造方法包括以下步骤:提供一基板,薄膜沉积铝复合膜层,进行铝选择性阳极氧化,在多孔氧化铝结构中形成铝布线绝缘层,在铝膜中形成芯片散热结构和金属铝柱阵列;再次进行薄膜沉积铝膜,进行铝选择性阳极氧化,依次重复,制备出Al2O3/Al薄膜多层布线层;在其上薄膜沉积铜复合膜层,采用光刻工艺制作铜薄膜导带,制作BCB介质膜通孔;再采用薄膜沉积、光刻工艺制作顶层薄膜导带和焊盘,以制备出BCB/Cu薄膜多层布线层。克服薄膜布线层数无法增加,BCB应力累积造成的互连可靠性差、软基材组装困难等问题,并且在基板上进行高密度布线互连,可满足高功率芯片和大规模集成电路等小型化、高可靠集成需求。

Description

一种基板混合薄膜多层布线制作方法
技术领域
本发明属于微电子封装领域,尤其涉及一种基板混合薄膜多层布线制作方法。
背景技术
现代电子技术的迅猛发展,要求电子系统朝着小型化、高性能、高可靠的方向发展。特别是航天领域以及民用电子产品对系统集成的需求更加迫切。随着超大规模集成电路的发展和所集成对象的电学功能复杂性的增加,使得可集成多种功能的系统级封装技术成为研究热点。
系统级封装可将数字电路、模拟电路和微波电路等有源器件,以及各类无源器件进行一体化集成。其系统复杂度的增加导致了系统内有源、无源器件数目的急剧增加,使得封装基板面临着严峻的挑战。一方面,系统庞大的数据实时处理需求,必须提高传输速率,增加封装基板互连的布线密度,提高芯片IO与基板互连效率,目前一个大规模芯片上可引出1000个I/O引脚数,并随着芯片数的增加,基板的布线线宽/间距需要减小到25μm/25μm,使得PCB板、LTCC基板很难满足高密度布线要求;同时,系统复杂的功能集成需求,导致系统功耗成倍增加,必须提高封装基板的散热能力,降低芯片工作结温;再次,系统的高速性能的提高,使得工作频率进入到微波频段,由信号路径产生的寄生参数的提高将直接导致信号的传输延迟,必须降低封装基板的传输损耗。
在一封装基板上进行薄膜多层布线,可显著提高系统的传输速率,降低传输损耗,并可制造高功率电路,整个系统封装结构都具有系统级功能突出的特点,并在机载、星载航天领域系统中得到广泛应用。但是薄膜多层布线基板与其他PCB、LTCC基板相比,具有明显的缺点就是薄膜布线层数受到限制;并且其薄膜介质(如PI、BCB)会随着膜层增加,而出现应力累积,影响系统的高可靠性能,因此迫切需要克服薄膜多层布线的不足。
目前,针对上述问题,通过采用将薄膜多层技术和其他多层电路技术(如厚膜技术、HTCC、LTCC等)结合起来进行基板制作。例如中国专利局公开的发明专利申请号CN200910251523.2的一种在LTCC基板上实现薄膜多层布线的方法,CN201210303440.5的一种基于LTCC基板薄膜多层布线制作方法。这些方法可以一定程度上改善薄膜多层布线层数低的不足,但是会受到PCB、HTCC、LTCC等孔间距,以及平面收缩和曲翘的限制,影响了衬底通孔与薄膜图形匹配精度,进而影响薄膜布线的扇出能力,同时其界面结合力也需要待改善,难以保证系统的高可靠性能。
发明内容
本发明要解决的技术问题是提供一种基板混合薄膜多层布线制作方法,以克服薄膜布线层数无法增加,以及BCB应力累积造成的互连可靠性差、软基材组装困难等问题。
为解决上述问题,本发明的技术方案为:
本发明的一种基板混合薄膜多层布线制作方法,包括以下步骤:
a1:提供一表面抛光清洗后的基板,并置于氮气气氛下进行热处理;
a2:在所述基板上表面上薄膜沉积钽和铝复合膜层,并在所述钽和铝复合膜层上光刻制作出选择性阳极氧化光刻图形;
a3:将所述基板置于阳极氧化电解液中进行选择性阳极氧化,阳极氧化部分形成铝布线绝缘层,未氧化部分形成芯片散热结构和金属铝柱阵列;
a4:去除光刻胶;
a5:在去除光刻胶的所述基板上表面上薄膜沉积钽和铝复合膜层,进行光刻、选择性阳极氧化,并制作出铝布线绝缘层、芯片散热结构、金属铝柱阵列和铝薄膜导带;
a6:去除光刻胶;
a7:在去除光刻胶的所述基板上表面上旋涂BCB介质膜,静置,光刻制作出BCB介质膜通孔,高温氮气气氛下进行预固化;
a8:在预固化的所述BCB介质膜上薄膜沉积铜复合膜层,光刻形成铜薄膜导带光刻图形;
a9:采用湿法刻蚀制作出铜薄膜导带,去除光刻胶;
a10:在去除光刻胶的所述基板上表面上旋涂BCB介质膜,光刻制作出BCB介质膜通孔,高温氮气气氛下进行完全固化;
a11:在所述BCB介质膜表面薄膜沉积顶层铜复合膜层,图形电镀Cu/Ni/Au金属层,去除光刻胶,采用湿法刻蚀制作出顶层薄膜导带和焊盘;
a12:依次重复a2至a6步骤,形成Al2O3/Al薄膜多层布线层,依次重复a7至a11步骤,形成BCB/Cu薄膜多层布线层,完成基板混合薄膜多层布线的制作。
本发明的基板混合薄膜多层布线制作方法,在步骤a1中,所述基板的材料为金刚石或AlN陶瓷或AlSi、AlSiC或WuCu或MoCu。
本发明的基板混合薄膜多层布线制作方法,在步骤a2和步骤a5中,所述钽膜的厚度范围为
Figure BDA0002388958690000031
所述铝膜的厚度范围为1μm~4μm。
本发明的基板混合薄膜多层布线制作方法,步骤a3和步骤a5中的选择性阳极氧化均包括如下步骤,
第一步:进行Al膜的选择性阳极氧化,氧化电压为40V~60V,制作出Al2O3绝缘层;
第二步:进行Ta膜的选择性阳极氧化,氧化电压为120V~150V,制作出Ta2O5绝缘层。
本发明的基板混合薄膜多层布线制作方法,步骤(a4)和(a6)中的去除光刻胶均为等离子刻蚀,刻蚀气体为Ar和O2,功率200W~500W。
本发明的基板混合薄膜多层布线制作方法,在步骤a7中的旋涂BCB介质膜为将BCB渗入多孔氧化铝结构中,进行封孔工艺;其中,光敏BCB的粘度为350cSt,膜厚为3.5μm~7.5μm,静置时间为8h~24h;
本发明的基板混合薄膜多层布线制作方法,在步骤a8中,铜复合膜层为TiW/Cu/TiW或Ti/Cu/Ti或Cr/Cu/Cr;其中,TiW或Ti或Cr膜厚度范围为
Figure BDA0002388958690000032
Cu膜厚度范围为1μm~4μm。
本发明的基板混合薄膜多层布线制作方法,在步骤a11中,顶层铜复合膜层可以为TiW/Cu或Ti/Cu或Cr/Cu;其中,TiW或Ti或Cr膜厚度范围为
Figure BDA0002388958690000041
Cu膜厚度范围为1μm~2μm。
本发明由于采用以上技术方案,使其与现有技术相比具有以下的优点和积极效果:
1、本发明一实施例通过Al2O3/Al可实现高层数薄膜布线,可大幅减少BCB/Cu薄膜布线层数,显著降低BCB应力累积,避免由于BCB的软介质材料过厚而引起后续组装困难等问题,薄膜混合多层布线质量可靠,适用于复杂系统中各种基板上的混合薄膜多层布线的制作。
2、本发明一实施例采用选择性铝阳极氧化技术,一次性制作出Al2O3布线绝缘层、芯片散热结构、金属铝柱阵列和铝薄膜导带,可实现平坦化的薄膜多层数、高密度布线,并可实现信号的电磁屏蔽性能。
3、本发明一实施例利用低介电BCB介质膜制作BCB/Cu薄膜多层布线,可显著降低信号延迟,减少信号传输损耗。
4、本发明一实施例采用高导热材料作为基板衬底,有利于高功率芯片及大规模集成电路的热传导,并降低器件结温。
附图说明
图1为本发明的基板混合薄膜多层布线制作方法的流程示意图;
图2a~2l为图1方法的各步骤对应所形成的基板的结构示意图;
图3为本发明的基板在封装过程中的结构示意图。
附图标记说明:100:基板;101:Ta层;102:Al层;103:光刻胶;104:Ta2O5绝缘层;105:Al2O3绝缘层;106:BCB介质膜;107:铜复合膜;108:顶层薄膜导带;109:芯片散热结构;110:金属铝柱阵列;111:铝薄膜导带;112:填充环氧树脂;113:焊球;114:倒装芯片;115:芯片;116:金丝。
具体实施方式
以下结合附图和具体实施例对本发明提出的一种基板混合薄膜多层布线制作方法作进一步详细说明。根据下面说明和权利要求书,本发明的优点和特征将更清楚。
参看图1,在一个实施例中,一种基板混合薄膜多层布线制作方法,包括以下步骤:
a1:提供一表面抛光清洗后的基板,并置于氮气气氛下进行热处理;
a2:在基板上表面上薄膜沉积钽和铝复合膜层,并在钽和铝复合膜层上光刻制作出选择性阳极氧化光刻图形;
a3:将基板置于阳极氧化电解液中进行选择性阳极氧化,阳极氧化部分形成铝布线绝缘层,未氧化部分形成芯片散热结构和金属铝柱阵列;
a4:去除光刻胶;
a5:在去除光刻胶的基板上表面上薄膜沉积钽和铝复合膜层,进行光刻、选择性阳极氧化,并制作出铝布线绝缘层、芯片散热结构、金属铝柱阵列和铝薄膜导带;
a6:去除光刻胶;
a7:在去除光刻胶的基板上表面上旋涂BCB介质膜,静置,光刻制作出BCB介质膜通孔,高温氮气气氛下进行预固化;
a8:在预固化的BCB介质膜上薄膜沉积铜复合膜层,光刻形成铜薄膜导带光刻图形;
a9:采用湿法刻蚀制作出铜薄膜导带,去除光刻胶;
a10:在去除光刻胶的基板上表面上旋涂BCB介质膜,光刻制作出BCB介质膜通孔,高温氮气气氛下进行完全固化;
a11:在BCB介质膜表面薄膜沉积顶层铜复合膜层,图形电镀Cu/Ni/Au金属层,去除光刻胶,采用湿法刻蚀制作出顶层薄膜导带和焊盘;
a12:依次重复a2至a6步骤,形成Al2O3/Al薄膜多层布线层,依次重复a7至a11步骤,形成BCB/Cu薄膜多层布线层,完成基板混合薄膜多层布线的制作。
本实施例通过依次重复制作薄膜沉积铝膜和进行铝选择性阳极氧化,可制备出Al2O3/Al薄膜多层布线层,在其上薄膜沉积铜复合膜层,采用光刻工艺制作铜薄膜导带,利用BCB光敏特性,制作BCB介质膜通孔,再次采用薄膜沉积、光刻工艺制作顶层薄膜导带和焊盘,以制备出BCB/Cu薄膜多层布线层。其中,Al2O3/Al可实现高层数薄膜布线,可大幅减少BCB/Cu薄膜布线层数,显著降低BCB应力累积,避免由于BCB的软介质材料过厚而引起后续组装困难等问题,薄膜混合多层布线质量可靠,适用于复杂系统中各种基板上的混合薄膜多层布线的制作,可满足高功率芯片和大规模集成电路等小型化、高可靠集成需求。
具体的,下面结合图1和图2a~2k将各步骤进行详细描述。
参看图1和图2a,在步骤(a1)中,提供一表面抛光清洗后的高导热基板100,置于氮气气氛下进行热处理。高导热基板100材料可以为热导率高的衬底材料,如金刚石、AlN陶瓷、AlSi、AlSiC复合材料,以及WuCu或MoCu金属材料。采用高导热材料作为基板衬底,有利于高功率芯片及大规模集成电路的热传导,并降低器件结温。
参看图1和图2b,在步骤(a2)中,在高导热基板110上表面薄膜沉积钽层111和铝层112的复合膜层,使用光刻胶103光刻制作出选择性阳极氧化光刻图形。其中Ta膜厚度范围为
Figure BDA0002388958690000061
Al膜厚度范围为1μm~4μm。
参看图1和图2c,在步骤(a3)中,将高导热基板110置于阳极氧化电解液中进行选择性阳极氧化,选择性阳极氧化分两步进行,第一步进行Al层112的选择性阳极氧化,氧化电压为40V~60V,制作出Al2O3绝缘层105。第二步进行Ta层111的选择性阳极氧化,氧化电压为120V~150V,制作出Ta2O5绝缘层104,从而阳极氧化部分形成铝布线绝缘层,未氧化部分形成芯片散热结构109和金属铝柱阵列110。
参看图1和图2d,在步骤(a4)中,去除光刻胶103。去除光刻胶103方法是等离子刻蚀,刻蚀气体为Ar和O2,功率200W~500W。
参看图1和图2e,在步骤(a5)中,在高导热基板110上表面薄膜沉积钽层111和铝层112的复合膜层,使用光刻胶103光刻,选择性阳极氧化,选择性阳极氧化分两步进行,第一步进行Al层112的选择性阳极氧化,氧化电压为40V~60V,制作出Al2O3绝缘层105;第二步进行Ta层111的选择性阳极氧化,氧化电压为120V~150V,制作出Ta2O5绝缘层104,从而阳极氧化部分形成铝布线绝缘层,未氧化部分形成铝布线绝缘层、芯片散热结构109,金属铝柱阵列110和铝薄膜导带111。采用选择性铝阳极氧化技术,一次性制作出Al2O3布线绝缘层、芯片散热结构、金属铝柱阵列和铝薄膜导带,可实现平坦化的薄膜多层数、高密度布线,并可实现信号的电磁屏蔽性能
参看图1和图2f,在步骤(a6)中,去除光刻胶103。去除光刻胶103方法是等离子刻蚀,刻蚀气体为Ar和O2,功率200W~500W。
参看图1和图2g,在步骤(a7)中,在其上表面旋涂BCB介质膜106,静置,将BCB渗入多孔氧化铝结构中,进行封孔工艺,以降低阳极氧化膜的孔隙率和吸附能力,然后光刻制作出BCB介质膜通孔,高温氮气气氛下进行预固化。其中光敏BCB的粘度为350cSt,膜厚为3.5μm~7.5μm,静置时间为8h~24h。
参看图1和图2h,在步骤(a8)中,薄膜沉积铜复合膜层107,光刻形成铜薄膜导带光刻图形。其中铜复合膜层可以为TiW/Cu/TiW、Ti/Cu/Ti或Cr/Cu/Cr,TiW、Ti、Cr膜厚度范围为
Figure BDA0002388958690000071
Cu膜厚度范围为1μm~4μm。
参看图1和图2i,在步骤(a9)中,采用湿法刻蚀制作出铜薄膜导带,去除光刻胶103。
参看图1和图2j,步骤(a10)中,在其上表面旋涂BCB介质膜106,光刻制作出BCB介质膜通孔,高温氮气气氛下进行完全固化。
参看图1和图2k,在步骤(a11)中,在BCB介质膜表面薄膜沉积顶层铜复合膜层107,图形电镀Cu/Ni/Au金属层,去除光刻胶,采用湿法刻蚀制作出顶层薄膜导带108和焊盘。其中顶层铜复合膜层可以为TiW/Cu、Ti/Cu或Cr/Cu,TiW、Ti、Cr膜厚度范围为
Figure BDA0002388958690000072
Cu膜厚度范围为1μm~2μm。利用低介电BCB介质膜制作BCB/Cu薄膜多层布线,可显著降低信号延迟,减少信号传输损耗
参看图1和图2l,在步骤(a12)中,依次重复(a2)至(a6)步骤,形成Al2O3/Al薄膜多层布线层,依次重复(a7)至(a11)步骤,形成BCB/Cu薄膜多层布线层,包含芯片散热结构109,金属铝柱阵列110,以及铝薄膜导带111,最终完成高导热基板混合薄膜多层布线的制作。
参看图3所示的是高导热基板在封装过程中的结构示意图,倒装芯片114通过焊球113与顶层焊盘互连,并通过填充环氧树脂112得到加固,通过金丝116实现与芯片115的互连,从而得到高导热基板薄膜混合多层互连封装结构。
本实施例采用高导热材料作为基板衬底,克服薄膜布线层数无法增加,以及BCB应力累积造成的互连可靠性差、软基材组装困难等问题,并且在高导热基板上进行高密度布线互连,可满足高功率芯片和大规模集成电路等小型化、高可靠集成需求,并且薄膜混合多层布线质量可靠,适用于复杂系统中各种基板上的混合薄膜多层布线的制作。
上面结合附图对本发明的实施方式作了详细说明,但是本发明并不限于上述实施方式。即使对本发明作出各种变化,倘若这些变化属于本发明权利要求及其等同技术的范围之内,则仍落入在本发明的保护范围之中。

Claims (8)

1.一种基板混合薄膜多层布线制作方法,其特征在于,包括以下步骤:
a1:提供一表面抛光清洗后的基板,并置于氮气气氛下进行热处理;
a2:在所述基板上表面上薄膜沉积钽和铝复合膜层,并在所述钽和铝复合膜层上光刻制作出选择性阳极氧化光刻图形;
a3:将所述基板置于阳极氧化电解液中进行选择性阳极氧化,阳极氧化部分形成铝布线绝缘层,未氧化部分形成芯片散热结构和金属铝柱阵列;
a4:去除光刻胶;
a5:在去除光刻胶的所述基板上表面上薄膜沉积钽和铝复合膜层,进行光刻、选择性阳极氧化,并制作出铝布线绝缘层、芯片散热结构、金属铝柱阵列和铝薄膜导带;
a6:去除光刻胶;
a7:在去除光刻胶的所述基板上表面上旋涂BCB介质膜,静置,光刻制作出BCB介质膜通孔,高温氮气气氛下进行预固化;
a8:在预固化的所述BCB介质膜上薄膜沉积铜复合膜层,光刻形成铜薄膜导带光刻图形;
a9:采用湿法刻蚀制作出铜薄膜导带,去除光刻胶;
a10:在去除光刻胶的所述基板上表面上旋涂BCB介质膜,光刻制作出BCB介质膜通孔,高温氮气气氛下进行完全固化;
a11:在所述BCB介质膜表面薄膜沉积顶层铜复合膜层,图形电镀Cu/Ni/Au金属层,去除光刻胶,采用湿法刻蚀制作出顶层薄膜导带和焊盘;
a12:依次重复a2至a6步骤,形成Al2O3/Al薄膜多层布线层,依次重复a7至a11步骤,形成BCB/Cu薄膜多层布线层,完成基板混合薄膜多层布线的制作。
2.如权利要求1所述的基板混合薄膜多层布线制作方法,其特征在于,在步骤a1中,所述基板的材料为金刚石或AlN陶瓷或AlSi、AlSiC或WuCu或MoCu。
3.如权利要求1所述的基板混合薄膜多层布线制作方法,其特征在于,在步骤a2和步骤a5中,所述钽膜的厚度范围为
Figure FDA0002388958680000011
所述铝膜的厚度范围为1μm~4μm。
4.如权利要求1所述的基板混合薄膜多层布线制作方法,其特征在于,步骤a3和步骤a5中的选择性阳极氧化均包括如下步骤,
第一步:进行Al膜的选择性阳极氧化,氧化电压为40V~60V,制作出Al2O3绝缘层;
第二步:进行Ta膜的选择性阳极氧化,氧化电压为120V~150V,制作出Ta2O5绝缘层。
5.如权利要求1所述的基板混合薄膜多层布线制作方法,其特征在于,步骤(a4)和(a6)中的去除光刻胶均为等离子刻蚀,刻蚀气体为Ar和O2,功率200W~500W。
6.如权利要求1所述的基板混合薄膜多层布线制作方法,其特征在于,在步骤a7中的旋涂BCB介质膜为将BCB渗入多孔氧化铝结构中,进行封孔工艺;其中,光敏BCB的粘度为350cSt,膜厚为3.5μm~7.5μm,静置时间为8h~24h。
7.如权利要求1所述的基板混合薄膜多层布线制作方法,其特征在于,在步骤a8中,铜复合膜层为TiW/Cu/TiW或Ti/Cu/Ti或Cr/Cu/Cr;其中,TiW或Ti或Cr膜厚度范围为
Figure FDA0002388958680000021
Cu膜厚度范围为1μm~4μm。
8.如权利要求1所述的基板混合薄膜多层布线制作方法,其特征在于,在步骤a11中,顶层铜复合膜层可以为TiW/Cu或Ti/Cu或Cr/Cu;其中,TiW或Ti或Cr膜厚度范围为
Figure FDA0002388958680000022
Cu膜厚度范围为1μm~2μm。
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