CN111261515B - Electronic device surface treatment method - Google Patents
Electronic device surface treatment method Download PDFInfo
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- CN111261515B CN111261515B CN202010061425.9A CN202010061425A CN111261515B CN 111261515 B CN111261515 B CN 111261515B CN 202010061425 A CN202010061425 A CN 202010061425A CN 111261515 B CN111261515 B CN 111261515B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01Q—SCANNING-PROBE TECHNIQUES OR APPARATUS; APPLICATIONS OF SCANNING-PROBE TECHNIQUES, e.g. SCANNING PROBE MICROSCOPY [SPM]
- G01Q30/00—Auxiliary means serving to assist or improve the scanning probe techniques or apparatus, e.g. display or data processing devices
- G01Q30/20—Sample handling devices or methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Abstract
The invention relates to the technical field of micro-nano scale material sample preparation, in particular to a surface treatment method of an electronic device. The electronic device comprises a substrate layer and a device structure layer arranged on the substrate layer, wherein a conducting layer and a gate dielectric layer are arranged in the device structure layer, and metal material layers are arranged in the conducting layer and the gate dielectric layer; the processing method comprises the following steps: thinning the device structure layer to expose the metal material layer on the surface of the device structure layer to obtain a first processing product; and etching the first processing product to obtain a second processing product. According to the electronic device surface treatment method, the device structure layer is thinned, so that the internal metal material layer is exposed out of the device structure, and then the metal material layer is removed through etching, so that the subsequent representation and analysis of the three-dimensional atom probe technology are guaranteed, and the success rate of analysis of the three-dimensional atom probe technology sample is improved.
Description
Technical Field
The invention relates to the technical field of material sample preparation, in particular to a surface treatment method for an electronic device.
Background
With the continuous development of the advanced technology of integrated circuits, the process and material structure of the mainstream Transistor Fin-Effect Transistor (FinFET) become more and more complex. How to manufacture a FinFET device with better and more stable performance requires a more precise selective etching process and a stricter metal purity control process, and realizes a complex work function metal film process. Therefore, for the research of the small-sized FinFET device, a high-precision characterization technique is required to perform three-dimensional structure-component analysis, distribution analysis of trace doping elements in a feature structure, analysis of a multi-layer metal surface and an interface, analysis of a material structure defect caused in a process, and the like. Three-dimensional Atom Probe Technology (APT) is considered to be the most powerful means for FinFET device research and analysis.
The main principle of the three-dimensional atom probe technology is that an analyzed device structure is prepared into a needle point-shaped sample, so that the material structure is peeled layer by layer from the top end of a needle point under the condition of electric field evaporation, the device structure is reconstructed through excited atom information, and the structure-component analysis of atomic resolution is finally realized. Therefore, the primary factor of the three-dimensional atom probe technical characterization analysis is to prepare a proper needle tip sample, and the preparation state of the three-dimensional atom probe technical sample is one of the key factors and difficulties which directly cause the success of the three-dimensional atom probe technical characterization result. The focused ion beam needle point sampling is mainly positioned on a FinFET structural layer, namely a front-end process structure of a FinFET technical chip, and a multilayer copper interconnection structure is arranged on the upper layer of the FinFET structure. Because of FinFET front end technology, a Gate structure (Gate) and a conducting layer (Contact) both adopt tungsten materials, and tungsten is a material which is not easy to evaporate in a field and is very easy to cause a needle point sample needle breakage phenomenon in the representation analysis of a three-dimensional atom probe technology.
Disclosure of Invention
The invention aims to solve the technical problem that metal materials in a gate structure and a conducting layer of a FinFET device are not easy to evaporate in the three-dimensional atom probe technical characterization analysis.
In order to solve the technical problem, the embodiment of the application discloses a surface treatment method of an electronic device, wherein the electronic device comprises a substrate layer and a device structure layer arranged on the substrate layer, a conducting layer and a gate dielectric layer are arranged in the device structure layer, and metal material layers are arranged in the conducting layer and the gate dielectric layer;
the processing method comprises the following steps:
thinning the device structure layer to expose the metal material layer on the surface of the device structure layer to obtain a first processing product;
and etching the first processing product to obtain a second processing product.
Further, the metal material layer is a tungsten metal material layer.
Furthermore, an etching method adopted for etching the first processing product is a chemical etching method.
Further, the etching method comprises the following steps:
heating the etching solution to a preset temperature;
placing the first treatment product into the etching solution;
and preserving the temperature of the etching solution for a preset time.
Further, the etching solution is hydrogen peroxide solution.
Further, the processing method further comprises: and depositing a protective layer on the surface of the second treatment product, wherein the protective layer is far away from the substrate layer.
Furthermore, the protective layer is made of a non-metallic compound.
Furthermore, the protective layer is made of a metal compound.
Furthermore, the method for depositing the protective layer is a chemical vapor deposition method or a physical vapor deposition method.
Further, the thickness of the protective layer is 10nm-10000nm.
By adopting the technical scheme, the electronic device surface treatment method has the following beneficial effects:
according to the electronic device surface treatment method, the device structure layer is thinned, the internal metal material layer is exposed out of the device structure, then the metal material layer is removed through etching, guarantee is provided for subsequent three-dimensional atom probe technical characterization analysis, and the success rate of three-dimensional atom probe technical sample analysis is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
FIG. 2 is a schematic illustration of the structure of a first processed product according to one embodiment of the present application;
FIG. 3 is a schematic structural view of a second processed product according to one embodiment of the present application;
FIG. 4 is a schematic view of the structure of the treated product of a surface protective cover according to one embodiment of the present application;
the following figures are provided to supplement the description:
10-a substrate layer; 20-a device structure layer; 21-a gate structure; 22-source/drain; 23-a layer of metallic material; 30-a conductor layer; 40-protective layer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the present application. In the description of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.
How to manufacture a FinFET device with better and more stable performance requires mastering the following key processes and material techniques; 1) In order to meet the requirements of FinFET device Fin channel carrier high mobility, short channel effect control, integration level and the like, the technology of Fin edge smoothness, fin size fineness and accuracy is required to be realized; 2) The silicon substrate of the FinFET adopts doping or non-doping with very low concentration, and doping elements (Ge, B, P and the like) need to be effectively selected and the distribution and the uniformity of doping components are controlled, which is particularly important for the performance of a device; 3) The threshold voltage adjustment of the FinFET device is realized by adopting metal materials (Al, ti, ta, hf and the like) with different work functions on a grid electrode, so that a more accurate selective etching process and a stricter metal purity control process are required, and a complex work function metal film process is realized. Therefore, three-dimensional atom probe technology is needed for characterization and analysis thereof.
As shown in fig. 1 to 3, embodiments of the present application provide an electronic device surface treatment method, which is used for surface treatment of an electronic device in a three-dimensional atom probe technology sample preparation process, so that a treated electronic device structure is easy for three-dimensional atom probe technology sample preparation and analysis. As shown in fig. 1, the electronic device includes a substrate layer 10 and a device structure layer 20 disposed on the substrate layer 10, a conducting layer and a gate dielectric layer are disposed in the device structure layer 20, and a metal material layer 23 is disposed in both the conducting layer and the gate dielectric layer;
the processing method comprises the following steps: thinning the device structure layer 20 to expose the metal material layer 23 on the surface of the device structure layer 20 to obtain a first processing product; and etching the first processing product to obtain a second processing product.
The method for processing the surface of the electronic device can be applied to the processing of the FinFET device structure in industrial practical application. On an electronic device, a structure needing sample preparation is found through the previous accurate positioning, and then the structure is processed. And (3) preparing a sample by the focused ion beam needle point, wherein the pretreatment of the surface layer of the device is matched, the multi-layer copper interconnection line and the metal material layer 23 are removed, and a good protective layer 40 after surface treatment is formed, so that the preparation of a high-quality needle point sample by the focused ion beam method is ensured. As shown in fig. 1, first, the wiring layer 30 above the device structure layer 20 of the FinFET is removed, and the wiring layer 30 is a copper interconnect multilayer structure and is used for circuit connection in an integrated circuit. The conductor layer 30 is removed using a thinning sampling technique. Optionally, removing copper metal in the wire layer 30 by polishing and grinding; optionally, the dielectric layer between the copper interconnection lines in the conductor layer 30 is removed by plasma etching. And removing the copper interconnection line layer by layer until reaching the conducting layer. As shown in fig. 1, in the embodiment of the present application, since the height of the conductive layer is higher than that of the top layer of the gate structure 21, the conductive layer needs to be thinned to the same height as that of the top layer of the gate structure 21, so as to ensure that the metal material layer 23 in the top layer of the gate structure 21 and the conductive layer are both exposed, no barrier layer covers the metal material layer 23, and a first processed product obtained after the thinning process is as shown in fig. 2. As shown in fig. 3, the metal material layer 23 is removed by etching by a physical method or a chemical method, so as to obtain a device structure which is easy for the three-dimensional atom probe technology sampling and analysis. It should be noted that the method described in the embodiments of the present application is not limited to processing finfets, but is also applicable to other electronic devices with similar structures.
The metal material layer 23 is a tungsten metal material layer 23.
As shown in fig. 1, in the embodiment of the present application, the metal material layer 23 is used to extract the gate or the source/drain 22, and the metal material layer 23 extracting the gate and the metal material layer 23 extracting the source/drain 22 may be the same or different. Optionally, the metal material layer 23 is made of metal such as nickel, molybdenum, tungsten, gold, platinum, zirconium, titanium, and the like.
The etching method adopted for etching the first processing product is a chemical etching method.
As shown in fig. 3, in the embodiment of the present application, the thinned electronic device structure is etched, and optionally, a chemical etching method is used for etching. When etching the metallic material layer 23, the etchant is selected to remove only the metallic material layer 23 without etching other structures of the electronic device.
The etching method comprises the following steps: heating the etching solution to a preset temperature; placing the first processed product into an etching solution; and preserving the temperature of the etching solution for a preset time.
The etching solution is a hydrogen peroxide solution.
In the embodiment of the present application, the exposed conductive layer and the metal material layer 23 in the gate structure 21 are removed by a chemical selective etching method. In the embodiment of the present application, a method for removing the metal material layer 23 is described by taking tungsten metal as an example, and it should be understood that, for metal material layers 23 of other materials, the metal material layer 23 may also be removed by etching with a suitable etchant according to the embodiment of the present application.
In the examples of the present application, chemical reagent H was selected 2 O 2 As an etchant, H 2 O 2 The concentration of (2) is 50%. Taking a proper amount of H 2 O 2 Pouring the solution into a measuring cup, and then dripping 1-2 drops of NH by using a dropper 4 OH to H 2 O 2 In solution, the above reagents are heated to 80 ℃ to boiling and then placed in the first treated product. The chemical reagent reacts with tungsten metal to generate W + H 2 O 2 +4NH 3 ·H 2 O═[W(NH 3 ) 4 ](OH) 2 +4H 2 And O, after reacting for a period of time, taking out the first treatment product, heating the reagent again, and repeating the process to ensure that the tungsten metal is removed completely. Only the tungsten metal is chemically etched in the whole process. The matrix structure of the electronic device is completely reserved, and the subsequent three-dimensional atom probe technical characterization analysis is facilitated.
The processing method further comprises the following steps: a protective layer 40 is deposited on the surface of the second process product, the protective layer 40 being arranged remote from the substrate layer 10.
As shown in fig. 4, in the embodiment of the present application, after the tungsten metal is removed, a cavity is left in the original structure position, the structure strength is relatively low, and the tip structure is prone to fracture during the three-dimensional atom probe technology sample preparation process, so in some embodiments, after the metal structure layer is removed by etching, a protective layer 40 may be further covered on the surface of the thinned sample where the metal structure layer is removed by the chemical etching. The protective layer 40 not only protects the sample surface from contamination, but also facilitates subsequent focused ion beam sampling and three-dimensional atom probe technique field evaporation testing.
The material of the protection layer 40 is a non-metallic compound.
The material of the protection layer 40 is a metal compound.
The protective layer 40 is deposited by chemical vapor deposition or physical vapor deposition.
The thickness of the protective layer 40 is 10nm to 10000nm.
In the embodiment of the present application, the material of the protection layer 40 may be a non-metal compound or a metal compound, and optionally, the non-metal compound is silicon monoxide, silicon dioxide, silicon nitride, or the like, and the metal compound is a germanium antimony compound, or the like. The protective layer 40 is deposited by chemical vapor deposition or physical vapor deposition. Optionally, a chemical vapor deposition method is used to deposit silicon monoxide as the protective layer 40, and the deposition thickness is 10nm to 1000nm, preferably 100nm. The SiO protective layer 40 can penetrate the electron beam during the sample preparation process with focused ion beam, and is suitable for searching a target position on the surface of a sample and accurately positioning the sample preparation. The protective layer 40 of silicon monoxide can also be retained on the top end of the final needle tip sample to protect the structural integrity of the needle tip during the sample preparation process, and the silicon monoxide layer is easy to be evaporated by a field in the laser mode of the three-dimensional atom probe technology, so the protective layer 40 is beneficial to the sample preparation and the test of the three-dimensional atom probe technology. In some embodiments, the germanium antimony compound Sb is deposited by physical vapor deposition 2 Te 3 The protective layer 40 has a thickness of 0.1 μm to 10 μm, preferably 1 μm. The protective layer 40 is opaque to the electron beam during the focused ion beam sampling process, i.e., cannot position the sample on the surface of the sample, but is suitable for random position sampling. Moreover, the protective layer 40 is susceptible to field evaporation in the non-laser mode of three-dimensional atom probe technology, and thus the protective layer 40 is advantageous for the sampling and testing of three-dimensional atom probe technology.
The method for processing the surface of the electronic device, provided by the embodiment of the application, provides a very critical sample preprocessing method for accurately positioning focused ion beams and preparing samples by the focused ion beams for the analysis of chip products with small size less than 22nm and FinFET device structures of the chip products. The method is used for manufacturing a complete sample with a small-size structure, and provides more powerful technical support for the subsequent research and analysis work of electronic devices. The needle point sample prepared by the method is very suitable for the technical test conditions of the three-dimensional atom probe, so that the success rate of analyzing the technical sample of the three-dimensional atom probe is greatly improved.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (7)
1. The electronic device surface treatment method is characterized in that the electronic device surface treatment method is used for surface treatment of an electronic device in a three-dimensional atom probe technology sample preparation process; the electronic device comprises a substrate layer (10) and a device structure layer (20) arranged on the substrate layer (10), wherein a conducting layer and a gate dielectric layer are arranged in the device structure layer (20), and metal material layers (23) are arranged in the conducting layer and the gate dielectric layer;
the processing method comprises the following steps:
thinning the device structure layer (20) to expose the metal material layer (23) on the surface of the device structure layer (20) to obtain a first processing product;
etching the first processing product to remove the metal material layer (23) to obtain a second processing product;
depositing a protective layer (40) on the surface of the second treatment product, the protective layer (40) being arranged away from the substrate layer (10);
the etching method adopted for etching the first processing product is a chemical etching method; the etching method comprises the following steps:
heating the etching solution to a preset temperature;
placing the first processed product into the etching solution;
and preserving the temperature of the etching solution for a preset time.
2. The electronic device surface treatment method according to claim 1, wherein the metal material layer (23) is a tungsten metal material layer (23).
3. The method of claim 1, wherein the etching solution is a hydrogen peroxide solution.
4. The method of claim 1, wherein the protective layer (40) is made of a non-metallic compound.
5. The method of claim 4, wherein the protective layer (40) is made of a metal compound.
6. The electronic device surface treatment method according to claim 4 or 5, wherein the protective layer (40) is deposited by a chemical vapor deposition method or a physical vapor deposition method.
7. The electronic device surface treatment method according to claim 6, wherein the protective layer (40) has a thickness of 10nm to 10000nm.
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| US11088036B2 (en) * | 2018-07-31 | 2021-08-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Atom probe tomography specimen preparation |
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