CN111258933A - Solid state disk controller circuit using Gen-Z bus structure protocol and solid state disk - Google Patents
Solid state disk controller circuit using Gen-Z bus structure protocol and solid state disk Download PDFInfo
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- CN111258933A CN111258933A CN202010133340.7A CN202010133340A CN111258933A CN 111258933 A CN111258933 A CN 111258933A CN 202010133340 A CN202010133340 A CN 202010133340A CN 111258933 A CN111258933 A CN 111258933A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
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- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
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- Computer Hardware Design (AREA)
- Bus Control (AREA)
Abstract
The invention discloses a solid state disk controller circuit and a solid state disk using a Gen-Z bus structure protocol, which comprises: the Gen-Z logic interface is connected with an external Gen-Z swing and used for finishing data exchange with the outside; the flash memory control unit is used for being connected with a flash memory so as to receive data sent by the flash memory or transmit data to the flash memory; and the conversion buffer unit is connected with the Gen-Z logic interface and the flash memory control unit and is used for converting the data transmitted by the interface conversion unit and sending the data to the interface conversion unit after the buffer processing. In the invention, the Gen-Z structure directly copies the data of the memory to the SSD array, thereby greatly accelerating the speed when the personal-level and enterprise-level hard disks transmit the data.
Description
Technical Field
The invention relates to the technical field of solid state disks, in particular to a solid state disk controller circuit using a Gen-Z bus structure protocol and a solid state disk.
Background
The Solid State Drives (Solid State Drives), referred to as fixed disks for short, are hard disks made of Solid State Drive (Solid State Drives) by using Solid electronic storage chip arrays, and are composed of a control unit and a storage unit (FLASH chip, DRAM chip). The specification, definition, function and use method of the interface of the solid state disk are completely the same as those of the traditional hard disk, the appearance and size of the product are completely the same as those of the traditional hard disk, and the I/O performance is greatly improved compared with that of the traditional hard disk. The method is widely applied to the fields of military affairs, vehicle-mounted, industrial control, video monitoring, network terminals, electric power, medical treatment, aviation, navigation equipment and the like.
The working temperature range of the chip is very wide, and the commercial product (0-70 ℃) is industrial standard product (-40-85 ℃). Although the cost is high, it is gradually spreading to the DIY market. Since solid state disk technology is different from traditional hard disk technology, a number of emerging memory vendors have emerged. The manufacturer can manufacture the solid state disk by only purchasing the NAND memory and matching with a proper control chip. The new generation of solid state disk generally adopts SATA-3 interface, M.2 interface, MSATA interface, PCI-E interface, SAS interface, CFast interface and SFF-8639 interface.
The existing solid state disk interface generally adopts an electronic Integrated Drive (IDE) or a Serial Advanced Technology Attachment (SATA) or a high speed Serial computer extension (PCI-e) interface, and has the following problems: because IDE adopts parallel bus interface, so the storage and reading speed is slow, SATA is half duplex and the speed is slow, PCI-e is used to connect central processor, internal memory and image processor. The SSD array is connected into PCIe Switch through a host bus adapter. When data is transmitted, information in the memory needs to be rolled for multiple times through a path of the memory-central processing unit-PCIe Switch-HBA-solid state disk to store the data, so that the performance is greatly influenced, and therefore improvement is needed.
Disclosure of Invention
The present invention is directed to a solid state disk controller circuit and a solid state disk using a Gen-Z bus structure protocol, so as to solve the problems of the background art.
In order to achieve the purpose, the invention provides the following technical scheme: a solid state hard disk controller circuit using a Gen-Z bus architecture protocol, comprising: the Gen-Z logic interface is connected with an external Gen-Z swing and used for finishing data exchange with the outside;
the flash memory control unit is used for being connected with a flash memory so as to receive data sent by the flash memory or transmit data to the flash memory;
and the conversion buffer unit is connected with the Gen-Z logic interface and the flash memory control unit and is used for converting the data transmitted by the interface conversion unit and sending the data to the interface conversion unit after the buffer processing.
Preferably, a plurality of controller interface connection modules are arranged in the flash memory control unit, and the flash memory control unit is connected with a plurality of external flash memories.
Preferably, the Gen-Z logic interface includes a logic conversion module, the logic conversion module includes a serial-parallel conversion module, an unpacking processing module, a parallel-serial conversion module and a packing processing module, the serial-parallel conversion module is connected to the unpacking processing module, and the parallel-serial conversion module is connected to the packing processing module.
Preferably, the conversion buffer unit includes a receiving buffer conversion module and a sending buffer conversion module.
Preferably, the solid state disk includes the solid state disk controller circuit.
Compared with the prior art, the invention has the beneficial effects that: in the invention, the Gen-Z structure directly copies the data of the memory to the SSD array, thereby greatly accelerating the speed when the personal-level and enterprise-level hard disks transmit the data.
Drawings
FIG. 1 is a schematic diagram of a circuit implementation of a solid state hard disk controller according to the present invention;
FIG. 2 is a further detailed schematic diagram;
FIG. 3 is a schematic diagram of a further refined Gen-Z interface conversion unit;
fig. 4 is a schematic structural diagram of the solid state disk implementation of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-4, the present invention provides a technical solution: a solid state hard disk controller circuit using a Gen-Z bus architecture protocol, comprising: a Gen-Z logic interface 1 connected with an external Gen-Z switch 2 and used for completing data exchange with the outside;
the flash memory control unit 3 is used for connecting with a flash memory 4 to receive data sent by the flash memory or transmit data to the flash memory;
and the conversion buffer unit 5 is connected with the Gen-Z logic interface 1 and the flash memory control unit 6, and is used for performing conversion processing on the data transmitted by the interface conversion unit and sending the data to the interface conversion unit after the buffer processing.
In the invention, a plurality of controller interface connection modules 7 are arranged in a flash memory control unit 3, and the flash memory control unit 3 is connected with a plurality of external flash memories 4.
In the invention, the Gen-Z logic interface 1 comprises a logic conversion module 8, wherein the logic conversion module 8 comprises a serial-parallel conversion module 9, an unpacking processing module 10, a parallel-serial conversion module 11 and a packing processing module 12, the serial-parallel conversion module 9 is connected with the unpacking processing module 10, and the parallel-serial conversion module 11 is connected with the packing processing module 12. When data is written in or sent out from the solid state disk through the controller circuit, the Gen-Z interface conversion unit can identify or store the data from the Gen-Z Switch for the flash memory after the data is subjected to serial-parallel conversion and unpacking processing.
In the present invention, the conversion buffer unit 5 includes a receiving buffer conversion module 13 and a transmitting conversion buffer module 14. The receiving buffer conversion module is used for receiving data sent by the Gen-Z and sending the data to the controller interface unit after carrying out buffer processing on the data, and the sending conversion buffer module caters to the data sent by the user receiving controller interface unit and sends the data to the Gen-Z interface conversion unit after carrying out buffer processing on the data.
In addition, the invention also discloses a solid state disk, which comprises the solid state disk controller circuit.
In the invention, the Gen-Z structure directly copies the data of the memory to the SSD array, thereby greatly accelerating the speed when the personal-level and enterprise-level hard disks transmit the data.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (5)
1. A solid state hard disk controller circuit using a Gen-Z bus architecture protocol, characterized by: the method comprises the following steps: a Gen-Z logic interface (1) connected with an external Gen-Z swing (2) and used for completing data exchange with the outside;
the flash memory control unit (3) is connected with a flash memory (4) to receive data sent by the flash memory or transmit data to the flash memory;
and the conversion buffer unit (5) is connected with the Gen-Z logic interface (1) and the flash memory control unit (3) and is used for performing conversion processing on the data transmitted by the interface conversion unit, and sending the data to the interface conversion unit after the buffer processing.
2. The solid state hard disk controller circuitry using a Gen-Z bus structure protocol of claim 1, wherein: the flash memory control unit (3) is internally provided with a plurality of controller interface connection modules (7), and the flash memory control unit (3) is connected with a plurality of external flash memories (4).
3. The solid state hard disk controller circuitry using a Gen-Z bus structure protocol of claim 1, wherein: the Gen-Z logic interface (1) comprises a logic conversion module (8), the logic conversion module (8) comprises a serial-parallel conversion module (9), an unpacking processing module (10), a parallel-serial conversion module (11) and a packing processing module (12), the serial-parallel conversion module (9) is connected with the unpacking processing module (10), and the parallel-serial conversion module (11) is connected with the packing processing module (12).
4. The solid state hard disk controller circuitry using a Gen-Z bus structure protocol of claim 1, wherein: the conversion buffer unit (5) comprises a receiving buffer conversion module (13) and a sending conversion buffer module (14).
5. A solid state disk, characterized in that: the solid state disk comprises the solid state disk controller circuitry of any of claims 1-4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010133340.7A CN111258933A (en) | 2020-03-01 | 2020-03-01 | Solid state disk controller circuit using Gen-Z bus structure protocol and solid state disk |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010133340.7A CN111258933A (en) | 2020-03-01 | 2020-03-01 | Solid state disk controller circuit using Gen-Z bus structure protocol and solid state disk |
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| Publication Number | Publication Date |
|---|---|
| CN111258933A true CN111258933A (en) | 2020-06-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010133340.7A Withdrawn CN111258933A (en) | 2020-03-01 | 2020-03-01 | Solid state disk controller circuit using Gen-Z bus structure protocol and solid state disk |
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| CN (1) | CN111258933A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112328517A (en) * | 2020-11-10 | 2021-02-05 | 西安紫光国芯半导体有限公司 | Memory data communication device and method based on three-dimensional chip and related equipment |
| CN112445430A (en) * | 2020-11-09 | 2021-03-05 | 苏州浪潮智能科技有限公司 | Equipment supporting multiple flash memory type solid state disk and operation method |
-
2020
- 2020-03-01 CN CN202010133340.7A patent/CN111258933A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112445430A (en) * | 2020-11-09 | 2021-03-05 | 苏州浪潮智能科技有限公司 | Equipment supporting multiple flash memory type solid state disk and operation method |
| CN112445430B (en) * | 2020-11-09 | 2023-01-10 | 苏州浪潮智能科技有限公司 | Equipment supporting multi-flash-memory solid state disk and operation method |
| CN112328517A (en) * | 2020-11-10 | 2021-02-05 | 西安紫光国芯半导体有限公司 | Memory data communication device and method based on three-dimensional chip and related equipment |
| CN112328517B (en) * | 2020-11-10 | 2024-04-02 | 西安紫光国芯半导体有限公司 | Memory data communication device and method based on three-dimensional chip and related equipment |
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