CN111257711A - Gate-level resistor automatic switching circuit and double-pulse automatic testing circuit - Google Patents
Gate-level resistor automatic switching circuit and double-pulse automatic testing circuit Download PDFInfo
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- CN111257711A CN111257711A CN201811459594.7A CN201811459594A CN111257711A CN 111257711 A CN111257711 A CN 111257711A CN 201811459594 A CN201811459594 A CN 201811459594A CN 111257711 A CN111257711 A CN 111257711A
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention discloses an automatic switching circuit of a gate-level resistor, which comprises a gate-level resistor array, a controllable switch array and a push-pull circuit, wherein the controllable switch array and the push-pull circuit are connected with the gate-level resistor array in series; the push-pull circuit is used for separating and decoupling the on-resistance array and the off-resistance array. The invention also discloses a double-pulse automatic test circuit. The invention realizes the full-automatic switching of the resistance in the double-pulse test mode, improves the test efficiency and the safety, supports higher instantaneous gate-level current and realizes the free adjustment of the on-off resistance.
Description
Technical Field
The invention relates to a double-pulse testing technology, in particular to a gate-level resistor automatic switching circuit and a double-pulse automatic testing circuit.
Background
The double pulse test is one of the most important test methods for testing the switching characteristics of power devices. In the double pulse test, the switching speed and the voltage stress of the device are often adjusted by adjusting the gate resistance.
The traditional mode is to switch the resistance of a gate-level resistor in a manual welding mode, the mode is long in time consumption, low in efficiency and easy to make mistakes, and a lot of inconvenience and potential safety hazards are brought in some high-temperature test scenes.
In the patent application nos.: CN201611240202.9 discloses an IGBT test circuit with continuously adjustable gate resistance and capacitance, which can realize automatic resistance switching. The following disadvantages still exist: (1) the mode that it adopted the light relay can not support higher conduction current to restrict the condition and the scope of test greatly, (2) the light relay volume is also often bigger, and a plurality of light relays can lead to the gate level return circuit bigger, and then causes the test result and actually have great deviation, (3) its gate level resistance combination's mode does not have the decoupling of resistance and the shutoff resistance of opening, and the tester can't be free adjusts respectively and opens and the shutoff resistance, thereby can bring very big inconvenience for the test.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a gate-level resistor automatic switching circuit and a double-pulse automatic test circuit which support higher conduction current and realize free adjustment of on-resistance and off-resistance and the like.
In order to achieve the purpose, the invention provides the following technical scheme: an automatic switching circuit of gate-level resistors comprises a gate-level resistor array, a controllable switch array, an isolation control chip array and a push-pull circuit, wherein,
the gate-level resistor array is connected in series with the controllable switch array and comprises an on-resistor array and an off-resistor array which are isolated, the on-resistor array comprises n +1 on-resistors which are connected in parallel, and the on-resistor array can generate 2 at most under the control of the controllable switch arraynEach open gate level resistor array combination; the turn-off resistor array comprises m +1 turn-off resistors connected in parallel, and can generate 2 at most under the control of the controllable switch arraymThe gate-off resistor array combination is arranged, wherein n and m are positive integers;
the controllable switch array comprises a first controllable switch array and a second controllable switch array which are isolated, and the first controllable switch array is connected with the switching-on resistor array in series and used for controlling the switching-on resistor array; the second controllable switch array is connected with the turn-off resistor array in series and used for controlling the turn-off resistor array;
the isolation control chip array is used for controlling the on and off of the controllable switch array;
the push-pull circuit is used for separating and decoupling the on-resistance array and the off-resistance array and comprises a first transistor and a second transistor which have different polarities, wherein the first transistor is connected with the on-resistance array, and the second transistor is connected with the off-resistance array.
Preferably, the isolation control chip array comprises a first isolation control chip array connected to the first controllable switch array and a second isolation control chip array connected to the second controllable switch array.
Preferably, the first controllable switch array comprises n first controllable switches connected in parallel, and each first controllable switch is connected in series with each corresponding on-resistance; the second controllable switch array comprises m second controllable switches connected in parallel, and each second controllable switch is connected with each corresponding turn-off resistor in series.
Preferably, the first isolation control chip array comprises n first isolation control chips, and each first isolation control chip is connected with each corresponding first controllable switch; the second isolation control chip array comprises m second isolation control chips, and each second isolation control chip is connected with each corresponding second controllable switch.
Preferably, the first controllable switch and the second controllable switch are MOSFET transistors or mechanical switches.
Preferably, the controllable switch array is arranged in a gate-level loop, and the isolation control chip array is arranged outside the gate-level loop.
Preferably, the first isolation control chip and the second isolation control chip are isolation optocouplers or digital isolators.
Preferably, the push-pull circuit is a triode push-pull amplifying circuit.
The invention also discloses another technical scheme: a double-pulse automatic test circuit comprises a control computer, an embedded controller in two-way communication with the control computer, a test drive board connected with the embedded controller and a power circuit connected with the test drive board, wherein the test drive board is integrated with a gate-level resistor automatic switching circuit; or sending a PWM instruction of the double-pulse test to the test driving board through the embedded controller.
The invention has the beneficial effects that:
1. the gate-level resistor array is designed to be connected with the controllable switch devices in series, automatic and remote control over the controllable switches is achieved by adopting an embedded controller, an isolation control chip and the like, full-automatic switching of resistors is achieved, no interference exists in the testing process, and testing efficiency and safety are improved.
2. An independent MOSFET or mechanical switch is used as a controllable switch, the instantaneous maximum current is supported to be more than 20A, and the requirement of gate-level instantaneous current of most power devices on the market is met; and the occupied area of the MOSFET is smaller, so that a gate-level loop is smaller, and the influence on a test result is smaller.
3. And a small-packaged MOSFET or a mechanical switch is selected to be arranged in the gate-level loop, and the isolation control chip is placed outside the gate-level loop, so that the consistency of the gate-level loop and an application scene is ensured as much as possible, and the reliability of a test result is ensured.
4. The gate-level on-resistance and the gate-level off-resistance are completely separated by adopting the triode push-pull circuit, so that the on-resistance and the off-resistance are decoupled, and a tester can completely and freely adjust the on-resistance and the off-resistance respectively.
Drawings
FIG. 1 is a schematic diagram of the gate-level resistor auto-switching circuit according to the present invention;
FIG. 2 is a schematic diagram of a double-pulse automatic test circuit according to the present invention.
Reference numerals:
1. the device comprises a gate-level resistor array, 11, an on resistor array, 12, an off resistor array, 2, a controllable switch array, 21, a first controllable switch array, 22, a second controllable switch array, 3, a push-pull circuit, 31, a first transistor, 32, a second transistor, 4, an isolation control chip array, 41, a first isolation control chip array, 42, a second isolation control chip array, 5, a control computer, 6, an embedded controller, 7, a test driving board, 8 and a power circuit.
Detailed Description
The technical solution of the embodiment of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention.
The gate-level resistor automatic switching circuit and the double-pulse automatic testing circuit disclosed by the invention can realize full-automatic switching of resistors in a double-pulse testing mode, have no interference in the testing process, and improve the testing efficiency and safety.
Referring to fig. 1 and 2, an automatic gate-level resistor switching circuit according to an embodiment of the present invention includes a gate-level resistor array 1, a controllable switch array 2, a push-pull circuit 3, and an isolation control chip array 4, where the gate-level resistor array 1 includes an on-resistor array 11 and an off-resistor array 12, where the on-resistor array 11 includes n +1 on-resistors connected in parallel, and the on-resistor array 11 can generate at most 2 under the control of the controllable switch array 2nEach open gate level resistor array combination; the turn-off resistor array 12 comprises m +1 turn-off resistors connected in parallel, and the turn-off resistor array 12 can generate 2 at most under the control of the controllable switch array 2mAnd the gate-off resistor array combination is formed, wherein n and m are positive integers.
The controllable switch array 2 is connected with the gate resistor array 1 in series, and gate resistors with different resistance values are generated through different combinations of the switches. In this embodiment, the controllable switch array 2 includes a first controllable switch array 21 and a second controllable switch array 22, which are isolated from each other, corresponding to the gate-level resistor array 1, where the first controllable switch array 21 is connected in series with the turn-on resistor array 11 for controlling the turn-on resistor array 11 to generate the number of combinations of the turn-on gate-level resistor array. Specifically, the first controllable switch array 21 includes n first controllable switches connected in parallel, and each first controllable switch corresponds to and is connected in series with an on-resistance.
The second controllable switch array 22 is connected in series with the turn-off resistor array 12, and is used for controlling the turn-off resistor array 12 to generate the combination number of the turn-off gate-level resistor array. In particular, the second controllable switch array 22 comprises m second controllable switches connected in parallel, each second controllable switch corresponding to and being connected in series with an off-resistance. In implementation, the first controllable switch and the second controllable switch can be MOSFET (metal oxide semiconductor field effect transistor) tubes or mechanical switches, the highest supporting instantaneous current can reach 20A, and the requirement of most power device gate-level instantaneous current in the market is met; and the occupied area of the MOSFET is smaller, so that a gate-level loop is smaller, and the influence on a test result is smaller.
The principle of the gate-level resistor combination will be described below by taking the example of turning on and off each of 3 controllable switches, i.e. there are 3 first controllable switches S in the gate-level loopon1、Son2、Son3Each controllable switch Son1、Son2、Son3Each is connected with a switching-on resistor Ron _1, Ron _2 and Ron _ 3; and 3 second controllable switches Soff1、Soff2、Soff3Each controllable switch Soff1、Soff2、Soff3Each connected to an off-resistor Roff _1, Roff _2, and Roff _ 3. Taking an on-resistance array as an example, 3 switching devices in an on-loop can be controlled to generate 23Combining gate-level resistor arrays:
1. controllable switch Son1，Son2，Son3Are all in an off state, where Rgon (gate on resistance) is equal to Ron _ 0;
2. controllable switch Son1Conduction, Son2，Son3Open, where Rgon equals the parallel resistance of Ron _0 and Ron _ 1;
3. controllable switch Son2Conduction, Son1，Son3Open, where Rgon equals the parallel resistance of Ron _0 and Ron _ 2;
4. controllable switch Son3Conduction, Son1，Son2Open, where Rgon equals the parallel resistance of Ron _0 and Ron _ 3;
5. controllable switch Son3Conduction, Son1，Son2Open, where Rgon equals the parallel resistance of Ron _0 and Ron _ 3;
6. controllable switch Son1，Son3Conduction, Son2Open, where Rgon equals Ron _0, Ron _1 and Ron _3 in parallel;
7. controllable switch Son2，Son3Conduction, Son1Open, where Rgon equals Ron _0, Ron _2, and Ron _3 resistance in parallel;
8. controllable switch Son1，Son2And Son3Are on, where Rgon equals the resistance of Ron _0, Ron _1, Ron _2, and Ron _3 in parallel.
The same strategy is adopted for the turn-off resistor, and 8 resistance values can be generated by combining 3 switches.
The push-pull circuit 3 is used for separating and decoupling the on-resistance array 11 and the off-resistance array 12, so that the adjustment between the on-resistance and the off-resistance is not interfered with each other. In this embodiment, the push-pull circuit 3 includes a first transistor 31 and a second transistor 32 with two different polarities, where the first transistor 31 is connected to the on resistor array 11, and the second transistor 32 is connected to the off resistor array 12. In practice, the push-pull circuit 3 may be a triode push-pull circuit, that is, the first transistor 31 and the second transistor 32 are two triodes with different polarities, such as an NPN-type triode and a PNP-type triode, respectively.
The isolation control chip array 4 is connected to the controllable switch array 2, and specifically, the isolation control chip array 4 includes a first isolation control chip array 41 connected to the first controllable switch array 21 and a second isolation control chip array 42 connected to the second controllable switch array 22. In this embodiment, the first isolation control chip array 41 includes n first isolation control chips, and each first isolation control chip is correspondingly connected to a first controllable switch; the second isolation control chip array 42 includes m second isolation control chips, and each second isolation control chip is correspondingly connected to a second controllable switch. When the isolation control circuit is implemented, the first isolation control chip and the second isolation control chip are at least isolation optocouplers or digital isolators.
Preferably, the controllable switch array 2 is arranged in a gate-level loop, and the isolation control chip array 4 is arranged outside the gate-level loop, so that the consistency between the gate-level loop and an application scene can be ensured as much as possible, and the reliability of a test result can be ensured.
As shown in fig. 2, the double-pulse automatic test circuit disclosed in the embodiment of the present invention includes a control computer 5, an embedded controller 6 in bidirectional communication with the control computer 5, a test driver board 7 connected to the embedded controller 6, and a power circuit 8 connected to the test driver board 7, wherein the control computer 5 is mainly used for human-computer interaction; the embedded controller 6 is used for sending a PWM (pulse width modulation) signal and a switch control signal; the gate-level resistor automatic switching circuit is integrated on the test drive board 7; the power circuit 8 is a power circuit for a double pulse test.
In the automatic test mode, the control computer 5 isolates the switch control signal through the embedded operator 6 and then sends the isolated switch control signal to the controllable switch array 2 on the test driving board 7, and then the gate-level resistor array 1 is automatically switched to present a corresponding resistance value. The control computer 5 then sends the PWM commands for the double pulse test to the test driver board 7 via the embedded operator 6.
Therefore, the scope of the present invention should not be limited to the disclosure of the embodiments, but includes various alternatives and modifications without departing from the scope of the present invention, which is defined by the claims of the present patent application.
Claims (9)
1. A gate-level resistor automatic switching circuit is characterized in that,
comprises a gate-level resistor array, a controllable switch array, an isolation control chip array and a push-pull circuit,
the gate-level resistor array and the controllable switchThe switch arrays are connected in series and comprise an on-resistance array and an off-resistance array which are isolated, the on-resistance array comprises n +1 on-resistances which are connected in parallel, and the on-resistance array can generate 2 at most under the control of the controllable switch arraynEach open gate level resistor array combination; the turn-off resistor array comprises m +1 turn-off resistors connected in parallel, and can generate 2 at most under the control of the controllable switch arraymThe gate-off resistor array combination is arranged, wherein n and m are positive integers;
the controllable switch array comprises a first controllable switch array and a second controllable switch array which are isolated, and the first controllable switch array is connected with the switching-on resistor array in series and used for controlling the switching-on resistor array; the second controllable switch array is connected with the turn-off resistor array in series and used for controlling the turn-off resistor array;
the isolation control chip array is used for controlling the on and off of the controllable switch array;
the push-pull circuit is used for separating and decoupling the on-resistance array and the off-resistance array and comprises a first transistor and a second transistor which have different polarities, wherein the first transistor is connected with the on-resistance array, and the second transistor is connected with the off-resistance array.
2. The gate-level resistor automatic switching circuit of claim 1, wherein the array of isolation control chips comprises a first array of isolation control chips coupled to the first array of controllable switches and a second array of isolation control chips coupled to the second array of controllable switches.
3. The gate-level automatic resistance switching circuit of claim 2, wherein the first controllable switch array comprises n first controllable switches connected in parallel, each of the first controllable switches being connected in series with a corresponding one of the on-resistors; the second controllable switch array comprises m second controllable switches connected in parallel, and each second controllable switch is connected with each corresponding turn-off resistor in series.
4. The gate-level resistor automatic switching circuit according to claim 3, wherein the first isolation control chip array comprises n first isolation control chips, and each first isolation control chip is connected with each corresponding first controllable switch; the second isolation control chip array comprises m second isolation control chips, and each second isolation control chip is connected with each corresponding second controllable switch.
5. The gate-level resistor automatic switching circuit of claim 3, wherein the first controllable switch and the second controllable switch are MOSFET transistors or mechanical switches.
6. The gate-level resistor automatic switching circuit of claim 2, wherein the controllable switch array is disposed in a gate-level loop, and the isolation control chip array is disposed outside the gate-level loop.
7. The gate-level resistor automatic switching circuit according to claim 4, wherein the first isolation control chip and the second isolation control chip are isolation optocouplers or digital isolators.
8. The gate-level resistor automatic switching circuit according to claim 1, wherein the push-pull circuit is a triode push-pull amplifying circuit.
9. A double-pulse automatic test circuit is characterized in that,
comprises a control computer, an embedded controller in bidirectional communication with the control computer, a test driving board connected with the embedded controller, and a power circuit connected with the test driving board,
the gate-level resistor automatic switching circuit as claimed in any one of claims 1 to 8 is integrated on the test driving board, the control computer sends a switch control signal to the controllable switch array on the test driving board through the embedded controller, and the gate-level resistor array is controlled to automatically switch to present a corresponding resistance value; or sending a PWM instruction of the double-pulse test to the test driving board through the embedded controller.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811459594.7A CN111257711A (en) | 2018-11-30 | 2018-11-30 | Gate-level resistor automatic switching circuit and double-pulse automatic testing circuit |
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| CN201811459594.7A CN111257711A (en) | 2018-11-30 | 2018-11-30 | Gate-level resistor automatic switching circuit and double-pulse automatic testing circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111985171A (en) * | 2020-08-28 | 2020-11-24 | 上海华力微电子有限公司 | Resistor parallel structure with high utilization rate |
| CN113671340A (en) * | 2021-10-21 | 2021-11-19 | 佛山市联动科技股份有限公司 | Switch parameter testing device of IGBT |
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Application publication date: 20200609 |