JP2009290287A - Switching circuit and driving circuit of transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To minimize delay of rising of gate voltage potential in a switching circuit having circuitry for maintaining the gate voltage potential of a transistor below a threshold potential. <P>SOLUTION: A switching circuit comprises a voltage controlled main transistor, a sub-transistor connected with the ground terminal and having a drain-source voltage at on time which is lower than the gate threshold voltage of the main transistor, a first power line provided with a first resistor and connecting the gate of the main transistor with a terminal which is connected with a power supply, a second power line which allows a current flowing from the gate of the main transistor to the sub-transistor selectively, and a third power line provided with a second resistor and connecting the terminal with the sub-transistor, wherein the resistance of the second resistor is smaller than a value obtained by dividing the product of the capacity of the main transistor and the resistance of the first resistor by the capacity of the sub-transistor. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a switching circuit that operates by applying a voltage to the gate of a voltage-controlled transistor, and a transistor drive circuit that forms part of the switching circuit.

  2. Description of the Related Art In recent years, voltage-controlled transistors, particularly IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), are widely used in semiconductor devices that form part of an inverter. In these transistors, the gate is connected to a power source via a switch or a voltage adjusting resistor, and when the gate potential becomes equal to or higher than the threshold potential by driving the switch, a current flows between the collector and the emitter (or between the source and the drain). (Hereinafter, referred to as a main current) flows. Conversely, when controlling the main current not to flow, the gate is connected to a low potential terminal (generally a ground terminal) via a resistor by driving the switch, and the gate potential becomes less than the threshold potential. Like that.

  In these transistors, a phenomenon is known in which a part of the current flows into the gate when the main current changes (particularly when the transistors of the upper and lower arms of the inverter are switched on and off). In the above configuration, the current flowing into the gate flows through the resistor to the ground terminal. When the current flowing into the gate is large, the gate potential is the threshold potential even though the switch is on the ground terminal side. The problem of being maintained as described above arises. As a result, an arm short circuit or the like in which the transistors in the same arm of the inverter are simultaneously turned on may occur and the transistors may be destroyed. For this reason, it is desirable to have a mechanism for quickly reducing the gate potential to less than the threshold potential at a desired timing.

An invention relating to a protection circuit for a semiconductor device in consideration of such problems has been disclosed (for example, see Patent Document 1). This protection circuit is configured to automatically connect the gate of the main transistor to the emitter when the detection voltage that rises as the main current increases exceeds the threshold voltage. Control is performed so that the gate potential of the main transistor is forcibly made lower than the threshold potential when the voltage increases.
JP-A-10-145206

  However, the protection circuit described in Patent Document 1 has a configuration in which a transistor for connecting the gate of the main transistor to the emitter (hereinafter referred to as an off-holding transistor) is connected to the power supply device in parallel with the main transistor. It is. Therefore, due to the drain-source capacitance of the off-holding transistor, there arises a problem that the time from the start of voltage application until the gate potential of the main transistor reaches the threshold potential is increased. If this time becomes long, not only the responsiveness of the whole semiconductor device is deteriorated, but also the heat generation of the main transistor becomes large, and sufficient heat dissipation must be ensured. For this reason, if the size of the main transistor is increased or the rated current is decreased, the cost of the device is increased and the performance is lowered. Further, since this time depends on the drain-source capacitance of the off-holding transistor, there is a problem that the design of the entire circuit becomes troublesome.

  The present invention is for solving such a problem, and a main object of the present invention is to suppress a delay in rising of the gate potential in a switching circuit having a configuration for maintaining the gate potential of the transistor below the threshold potential. And

In order to achieve the above object, the first aspect of the present invention provides:
A voltage controlled main transistor;
A sub-transistor connected to the ground terminal and having a drain-source voltage lower than the gate threshold voltage of the main transistor when on;
A first power line provided with a first resistor and connecting a terminal connected to a power supply device and the gate of the main transistor;
A second power line that selectively allows current to flow from the gate of the main transistor to the sub-transistor;
A second resistor, a third power line connecting the terminal and the sub-transistor,
The resistance value of the second resistor is a value smaller than a value obtained by dividing the product of the capacitance of the main transistor and the resistance value of the first resistor by the capacitance of the sub-transistor.
It is a switching circuit.

  According to the first aspect of the present invention, the delay in rising of the gate potential can be suppressed as compared with the conventional configuration for maintaining the gate potential of the transistor below the threshold potential.

The second aspect of the present invention is:
A voltage controlled main transistor;
A sub-transistor connected to the ground terminal and having a drain-source voltage lower than the gate threshold voltage of the main transistor when on;
A first power line provided with a first resistor and connecting a terminal connected to a power supply device and the gate of the main transistor;
A second power line that selectively allows current to flow from the gate of the main transistor to the sub-transistor;
A second resistor, a third power line connecting the terminal and the sub-transistor,
The resistance value of the second resistor is smaller than the resistance value of the first resistor.
It is a switching circuit.

  According to the second aspect of the present invention, the delay in rising of the gate potential can be suppressed as compared with the conventional configuration for maintaining the gate potential of the transistor below the threshold potential.

  In the first or second aspect of the present invention, it is preferable that the third power line selectively allows a current flowing from the second terminal to the sub-transistor.

The third aspect of the present invention is:
A transistor driving circuit for voltage-controlling a main transistor,
A sub-transistor connected to the ground terminal;
A first power line provided with a first resistor and connecting a terminal connected to a power supply device and the gate of the main transistor;
A second power line that selectively allows current to flow from the gate of the main transistor to the sub-transistor;
A third power line provided with a second resistor connecting the terminal and the sub-transistor;
A driving circuit of a transistor having

  According to the present invention, in a switching circuit having a configuration for maintaining the gate potential of a transistor below a threshold potential, a delay in rising of the gate potential can be suppressed.

  Hereinafter, the best mode for carrying out the present invention will be described with reference to the accompanying drawings.

  Hereinafter, a switching circuit 1 according to an embodiment of the present invention will be described.

[Constitution]
FIG. 1 is a diagram illustrating an example of the overall configuration of the switching circuit 1. The switching circuit 1 is connected to a voltage-controlled IGBT (Insulated Gate Bipolar Transistor) 10, resistors Rg, Rgp, Rgn, Rb, diodes Ds, Db, terminals MP, MN, SoutD, and these as main components. A power line and a transistor 30 are provided. The IGBT 10 corresponds to a “main transistor” in the claims, and the transistor 30 corresponds to a “sub-transistor” in the claims. Further, a circuit obtained by removing the IGBT 10 from the switching circuit 1 corresponds to a “transistor driving circuit” in the claims.

  The IGBT 10 is a bipolar transistor in which a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is incorporated in the gate portion, and when the potential of the gate 10A (gate potential) becomes a threshold potential (for example, 3 [V] or the like) It operates so that a current flows between the collector and the emitter. The main transistor is not limited to the IGBT, and other types of voltage controlled transistors such as MOSFETs may be used.

  For example, a positive electrode of a power source such as a battery having a rated voltage of 15 [V] is connected to the terminal MP via a switching element Qp. The terminal MN is connected to a negative electrode of a power source such as a battery and a ground terminal (0 [V]) via a switching element Qn. The switching elements Qp and Qn are controlled by a control device (not shown) so that only one of them is turned on.

  The negative terminal of the power source and the ground terminal are connected to the terminal SoutD via the transistor 30. The transistor 30 is, for example, a MOSFET, and is controlled by a control device (not shown) so as to be turned on when a current flowing between the collector and the emitter of the IGBT 10 (hereinafter referred to as a main current) changes greatly. Further, the present invention is not limited to this, and control may be performed so that the switching elements Qp and Qn are periodically turned on in synchronization with the on / off of the switching elements Qp and Qn.

  Resistors Rgp and Rg are sequentially provided on a power line (corresponding to a “first power line” in the claims) from the terminal MP to the gate 10A.

  A power line (corresponding to a “second power line” in the claims) from the gate 10A to the terminal SoutD is provided with a diode Ds, and selectively allows current flowing from the output terminal MG to the terminal SoutD. It is supposed to be.

  A power line (corresponding to a “third power line” in the claims) from the terminal MP to the terminal SoutD is provided with a resistor Rb and a diode Db, and selectively selects a current flowing from the terminal MP to the terminal SoutD. Is tolerated.

  Also, a resistor Rgn is provided on the power line that branches from between the resistor Rgp and the resistor Rg in the power line from the terminal MP to the gate 10A and reaches the terminal MN.

  The resistance value of the resistor Rb is smaller than a value obtained by dividing the sum of the resistance values of the resistors Rg and Rgp by the gate-emitter capacitance Cs of the IGBT 10 by the drain-source capacitance Cm of the transistor 30. This significance will be described later.

[Conventional issues]
Here, problems that occur in the conventional apparatus will be described. FIG. 2 is a simplified diagram showing a configuration of a conventional semiconductor device. In this semiconductor device, a sub-transistor for forcibly lowering the gate potential of the main transistor to the ground potential is connected to the power supply device in parallel with the main transistor. Between the power supply and these transistors. A resistor Rj is provided.

  In such a configuration, the time from when the power supply device is turned on until the gate potential of the main transistor becomes equal to or higher than the threshold potential depends on the capacitance of the sub-transistor (drain-source capacitance if the sub-transistor is a MOSFET) Csj, This is longer than when no sub-transistor is provided. FIG. 3 is a diagram showing such a state. In this figure, the capacity of the main transistor is denoted as Cmj. As a result, not only the responsiveness of the whole semiconductor device is deteriorated but also the heat generation of the main transistor is increased, and sufficient heat dissipation must be ensured. For this reason, it is conceivable to increase the size of the main transistor or reduce the rated current, but this is not preferable because it increases the cost of the device and decreases the performance. Further, since this time depends on the drain-source capacitance of the off-holding transistor, there is a problem that the design of the entire circuit becomes troublesome.

[Operation of switching circuit 1]
On the other hand, in the switching circuit 1 of this embodiment, the resistor Rb is provided on the power line from the terminal MP to the terminal SoutD where the potential rises earliest after the switching element Qp is turned on. In parallel with the increase in the gate potential, the gate potential of the gate 10A increases. Therefore, a delay in rising of the gate potential can be suppressed as compared with the conventional configuration. Further, since only a resistor and a diode are added to the conventional configuration, power consumption does not increase. It should be noted that a transistor 30 having a sufficiently small equivalent resistance is used so that the gate potential of the gate 10A does not exceed the threshold voltage due to the current expected to flow into the gate when the main current flowing between the collector and emitter of the IGBT 10 changes. ing.

  In addition, the switching circuit 1 includes a diode Ds between the gate 10A and the transistor 30. This prevents the current to be supplied to the transistor 30 from going to the gate 10A and raising the potential of the gate 10A. Therefore, the rise of the potential of the gate 10A depends on the gate-emitter capacitance Cm and the resistors Rgp and Rg of the IGBT 10, and the design of the entire circuit can be facilitated.

  Further, the switching circuit 1 is obtained by dividing the resistance value of the resistor Rb by the sum of the resistance values of the resistors Rg and Rgp and the gate-emitter capacitance Cm of the IGBT 10 by the drain-source capacitance Cs of the transistor 30. It is set to a smaller value. As a result, the drain potential of the transistor 30 rises earlier than the potential of the gate 10A. Therefore, it is possible to avoid the inconvenience that the potential of the gate 10A rises first, whereby a current flows from the gate 10A to the transistor 30 and the potential of the gate 10A becomes unstable (for example, vibration or the like occurs).

  FIG. 4 is a diagram showing characteristics of the gate potential of the IGBT 10 and the drain potential of the transistor 30 realized by these configurations.

  Note that the diode Db is configured such that when the switching element Qp is turned off and the Qn is turned on when the transistor 30 is turned off (when the normal IGBT 10 is turned off), the current flowing from the gate 10A causes the resistors Rg and Rgn to flow. This is to reach the terminal MN through. When there is no diode Db, there is a power path from the gate 10A through the diode Ds, resistors Rb, Rgp, and Rgn to the terminal MN in order, so that the response when the potential of the gate 10A is lowered is optimized. It becomes difficult to design the entire circuit (actually, determination of the resistance ratio, etc.). By providing the diode Db, it becomes easy to optimally determine the ratio of the resistors Rg, Rgp, Rgn and the like.

[Usage example]
The switching circuit 1 is used as a part of an inverter 50 as shown in FIG. 5, for example. The inverter 50 has three arms 51, 52, and 53, and two IGBTs 10 are attached to each arm. The IGBT 10 in each arm is controlled by a control device (not shown) so that if one is on, the other is off. The IGBT 10 attached to each arm is on / off controlled with a phase shift of 120 degrees, for example, and the motor 60 is rotationally controlled. At this time, since the IGBT 10 is connected to the configuration for quickly reducing the potential of the gate 10A at a desired timing as described above, it is possible to prevent the occurrence of an arm short circuit in which the transistors of the same arm are simultaneously turned on. Is done.

[Summary]
According to the switching circuit 1 of the present embodiment described above, since the resistor Rb is provided on the power line from the terminal MP to the terminal SoutD, the gate potential of the gate 10A is increased in parallel with the rise of the drain potential of the transistor 30. To rise. Therefore, it is possible to suppress the delay of the rise of the gate potential without significantly increasing the power consumption as compared with the conventional configuration.

  Further, since the diode Ds is provided between the gate 10A and the transistor 30, the rise of the potential of the gate 10A depends on the resistors Rgp and Rg, and the design of the entire circuit can be facilitated. Furthermore, the resistance value of the resistor Rb is set to a value smaller than the value obtained by dividing the sum of the resistance values of the resistors Rg and Rgp by the gate-emitter capacitance of the IGBT 10 by the drain-source capacitance of the transistor 30. Thus, it is possible to avoid the inconvenience that the potential of the gate 10A rises first, whereby a current flows from the gate 10A to the transistor 30 and the potential of the gate 10A becomes unstable.

[Modification]
The best mode for carrying out the present invention has been described above with reference to the embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the scope of the present invention. And substitutions can be added.

  For example, the resistance value of the resistor Rb is set to a value smaller than a value obtained by dividing the sum of the resistance values of the resistors Rg and Rgp by the gate-emitter capacitance of the IGBT 10 by the drain-source capacitance of the transistor 30. However, simpler restrictions may be imposed. For example, assuming that the gate-emitter capacitance Cm of the IGBT 10 is applied to a device having a drain-source capacitance Cs greater than that of the transistor 30, the resistance value of the resistor Rb is simply changed to the resistances of the resistors Rg and Rgp. The value may be smaller than the sum of the values.

  Further, as shown in FIG. 6, the resistors Rgp and Rgn are not distinguished from each other, and the power path during the on-control of the gate 10A and the power path during the off-control may be shared. In this case, it is not necessary to distinguish between the terminals MP and MN.

  Further, as shown in FIG. 7, a buffer 70 may be provided in the middle of the power line from the gate 10A to the terminal SoutD. The configuration of this figure is preferably applied when the current flowing from the output terminal MG to the terminal SoutD is relatively large. The buffer 70 includes a transistor 72 and a resistor Reb. Similar to the transistor 30, the transistor 72 is sufficiently small so that the gate potential of the gate 10A does not exceed the threshold voltage due to the current expected to flow into the gate when the main current flowing between the collector and emitter of the IGBT 10 changes. A resistor is used. The transistor 72 operates so as to be turned on when a certain potential difference or more is generated between the emitter and the base. The resistor Reb is provided to set the potential difference between the base and the emitter of the transistor 72 to 0 [V] when the transistor 30 is turned off. According to such a configuration, it is possible to cope with a case where the current flowing from the output terminal MG to the terminal SoutD is relatively large.

  The present invention can be used in the automobile manufacturing industry, the automobile parts manufacturing industry, and the like.

It is a figure which shows an example of the whole structure of the switching circuit 1 which concerns on one Example of this invention. It is a figure which simplifies and shows the structure of the conventional semiconductor device. It is a figure which shows a mode that the time until the gate potential of a main transistor becomes more than a threshold potential becomes long compared with the case where a subtransistor is not provided depending on the capacity | capacitance of a subtransistor. It is a figure which shows the characteristic of the gate electric potential of IGBT10 and the drain electric potential of the transistor 30 implement | achieved by the structure of a present Example. It is a structural example of the inverter 50 to which the switching circuit 1 is applied suitably. In this configuration example, the resistors Rgp and Rgn are not distinguished from each other, and the power path during the on-control of the gate 10A and the power path during the off-control are shared. In this configuration example, a buffer 70 is provided in the middle of the power line from the gate 10A to the terminal SoutD.

Explanation of symbols

1 Switching circuit 10 IGBT
10A Gate 30, 72 Transistor 50 Inverter 51, 52, 53 Arm 60 Motor 70 Buffer Ds, Db Diode Qp, Qn Switching element Rg, Rgp, Rgn, Rb, Rj, Reb Resistance MP, MN, SoutD terminal MG Output terminal

Claims (4)

A voltage controlled main transistor;
A sub-transistor connected to the ground terminal and having a drain-source voltage lower than the gate threshold voltage of the main transistor when on;
A first power line provided with a first resistor and connecting a terminal connected to a power supply device and the gate of the main transistor;
A second power line that selectively allows current to flow from the gate of the main transistor to the sub-transistor;
A second resistor, a third power line connecting the terminal and the sub-transistor,
The resistance value of the second resistor is a value smaller than a value obtained by dividing the product of the capacitance of the main transistor and the resistance value of the first resistor by the capacitance of the sub-transistor.
Switching circuit. A voltage controlled main transistor;
A sub-transistor connected to the ground terminal and having a drain-source voltage lower than the gate threshold voltage of the main transistor when on;
A first power line provided with a first resistor and connecting a terminal connected to a power supply device and the gate of the main transistor;
A second power line that selectively allows current to flow from the gate of the main transistor to the sub-transistor;
A second resistor, a third power line connecting the terminal and the sub-transistor,
The resistance value of the second resistor is smaller than the resistance value of the first resistor.
Switching circuit. The third power line selectively allows current to flow from the terminal to the sub-transistor;
The switching circuit according to claim 1 or 2. A transistor driving circuit for voltage-controlling a main transistor,
A sub-transistor connected to the ground terminal;
A first power line provided with a first resistor and connecting a terminal connected to a power supply device and the gate of the main transistor;
A second power line that selectively allows current to flow from the gate of the main transistor to the sub-transistor;
A third power line provided with a second resistor connecting the terminal and the sub-transistor;
A driving circuit of a transistor having

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