JP3964912B2 - Inrush current reduction circuit - Google Patents

Description

  The present invention relates to an inrush current reduction circuit.

  As inverter technology is applied to commercially available electrical equipment, there is an increased possibility of electromagnetic interference to other electronic equipment due to the inrush current generated when power is applied to the equipment.

  For example, when a plurality of inverter lighting devices are turned on with a single switch, such as office ceiling lighting, the same inrush current flows to each device at the same time, but a very large inrush current flows instantaneously as a whole, May cause electromagnetic interference.

  In order to easily reduce the inrush current, an inductor may be inserted in series with the power supply line. However, if the L component of the inductor is increased in order to further reduce the inrush current, the volume and weight increase. In addition, the inductor has a considerable impedance even at a commercial power supply frequency, which causes energy loss. When a burst inrush current occurs, resonance may occur due to the L component of the inductor, the L component of the load, and the C (capacitance) component, and it is difficult to select the value of the inductor L.

  As another method for reducing the inrush current, a zero cross switch using a switching semiconductor element, a solid state relay, a thyristor, a triac, or the like is used.

  In other words, a resistor is inserted in the power supply line so that this resistor can be short-circuited by a switching semiconductor element.When the power is turned on, the resistor reduces the inrush current, and after a predetermined period after the power is turned on, a high inrush current flows, This is a method of preventing energy loss due to resistance thereafter by turning on the switching semiconductor element.

Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique for making a current (drain current) flowing in the power supply line constant by inserting a MOSFET in the power supply line and adjusting the gate voltage by voltage dividing means.
Japanese Patent Laid-Open No. 5-19879

  However, in the method of short-circuiting the resistor with the switching semiconductor element, the semiconductor element is used as a mere switch. Therefore, a resistance that can withstand the heat generated by the inrush current is required separately from the semiconductor element. Simplification is difficult. In addition, the thyristor cannot reduce the inrush current that occurs intermittently unless a circuit for turning it off is added. In addition, the zero cross switch has a disadvantage that it is difficult to use for a low-priced device because the configuration is complicated and expensive because phase control is required.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide an inrush current reduction circuit that solves inconveniences when a semiconductor is used as a simple switch.

In order to solve the above problems, the present invention of claim 1 includes a semiconductor element inserted in a current path from a power supply to a load, and a current detection circuit connected in parallel to the semiconductor element, and the current detection circuit the circuit node of the inner and connected to the bias control point of said semiconductor element, the rush current flowing through the current path is drawn to the current detection circuit, the inrush of bias voltage is a voltage of the bias control points so as to increase A current reduction circuit, wherein the current detection circuit is connected to the bias control point and charged by the drawn inrush current to increase the bias voltage; and a resistor connected in parallel to the capacitor An inrush current reduction circuit characterized by comprising:

The present invention of claim 2, the rush current reduction circuit provided with a device for preventing a reverse current at a location inrush current rush current reduction circuit according to claim 1 Symbol placement flows, the same rush current reduction and projecting input current reduction circuit An inrush current reduction circuit comprising a circuit and an inrush current reduction circuit connected in parallel in the opposite direction is used as a solution.

According to a third aspect of the present invention, there is provided an inrush current reduction circuit comprising the inrush current reduction circuit according to the second aspect in each line of a three-phase AC power supply.

The present invention of claim 4 is an element inserted at a location where an inrush current flows, and includes an element that lowers the bias voltage of the semiconductor element in accordance with a change in the voltage across the element when the inrush current flows. The inrush current reduction circuit according to any one of claims 1 to 3 is used as a solving means.

The present invention of claim 5 is an N-channel MOSFET, wherein the current detection circuit includes a resistor connected between a drain and a gate of the N-channel MOSFET, a resistor connected between a gate and a source of the N-channel MOSFET, it is configured to include a parallel capacitor to the resistor and solutions with a rush current reduction circuit according to any one of claims 1 to 4, characterized in.

According to the present invention of claim 6 , the semiconductor element is an NPN bipolar transistor, and the current detection circuit is connected between a collector and base of the NPN bipolar transistor and between a base and emitter of the NPN bipolar transistor. a resistor, and solutions have a rush current reduction circuit according to any one of claims 1 to 4, characterized in that it is configured to include a parallel capacitor to the resistor.

  According to the inrush current reduction circuit of the present invention, when the inrush current flows, the semiconductor element to be inserted at the location where the inrush current flows and when the inrush current does not flow (in a steady state), the bias of the semiconductor element is deepened and the inrush current flows. And a current detection circuit for reducing the bias of the semiconductor element. Since the semiconductor element is used as a switch and a resistor, a resistor is not necessary, and there is a component such as an additional circuit necessary for turning off the thyristor. Therefore, it is easy to miniaturize and simplify the circuit, and it is possible to incorporate it into the device.

  Further, since a phase control mechanism such as a zero-cross switch is unnecessary, the configuration can be simplified and the cost can be reduced, and it can be used for an inexpensive device.

  In addition, since the bias of the semiconductor element is shallowed only during a short period during which the inrush current flows, there is little power loss and heat generation, and consideration for heat dissipation can be reduced.

  Further, since the inductor is not provided in the current path, the inrush current can be reduced without causing a resonance phenomenon.

  It is also possible to reduce the inrush current from the three-phase AC power source.

  Embodiments of an inrush current reduction circuit according to the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a circuit diagram of an example including an inrush current reduction circuit according to the first embodiment.

  The positive electrode of the DC power source 1 is connected to the drain of the transistor Q1, which is an N-channel MOSFET (for example, enhanced mode MOSFET), via the switch SW, and the source of the transistor Q1 is connected to the positive electrode of the load (device) 2. The negative electrode of the DC power source 1 and the negative electrode of the load 2 are connected. One end of the resistor R1 is connected to the drain of the transistor Q1, and the other end of the resistor R1 is connected to the gate of the transistor Q1. One end of the resistor R2 is connected to the gate of the transistor Q1, and the other end of the resistor R2 is connected to the source of the transistor Q1. A capacitor C1 is connected in parallel with the resistor R2. Since the transistor Q1 is inserted in the current path from the DC power source 1 to the load 2, it is a so-called power transistor, and preferably has a high withstand voltage, low on-resistance, and high heat dissipation. This is the same in other embodiments.

  The transistor Q1, resistors R1, R2 and the capacitor C1 constitute an inrush current reduction circuit, and the resistors R1, R2 and the capacitor C1 constitute a current detection circuit.

  Since the frequency component of the inrush current is often composed of a sufficiently high frequency component compared to the commercial AC power supply frequency, it does not respond at the commercial AC frequency, but the bias circuit is configured by resistance voltage division so that it responds at a high frequency By inserting the capacitor C1 in parallel with the resistor, the bias reduction to the inrush current (direction in which the transistor is turned off) is realized. The same applies to other embodiments.

  In FIG. 1, when the switch SW is turned on from off, an inrush current flows through the load 2. At this time, first, charging of the capacitor C1 starts from the DC power source 1 via the resistor R1. At the beginning of charging, since the potential difference across the capacitor C1, that is, the gate voltage of the transistor Q1, is small, the bias of the transistor Q1 is shallow and the transistor Q1 is cut off.

  As the charging continues, the gate voltage of the transistor Q1 increases, that is, the bias of the transistor Q1 deepens, and current begins to flow through the transistor Q1, but at that time, the inrush current flowing through the transistor Q1 is sufficiently small and the load 2 The current is also small. Therefore, the maximum value of the current to the load 2 can be made lower than when the switch SW and the load 2 are directly connected.

  Note that the drain-source voltage of the transistor Q1 when the steady current is supplied to the load 2 is turned on with respect to the resistor R1 so that the steady-state current is turned on, that is, the gate-source voltage is sufficiently large. The resistance value of the resistor R2 is set.

[Second Embodiment]
FIG. 2 is a circuit diagram of an example including an inrush current reduction circuit according to the second embodiment.

  Here, the same reference numerals are given to components having the same functions as those in the first embodiment.

  The positive electrode of the DC power source 1 is connected to the collector of the transistor Q1, which is an NPN bipolar transistor, via the switch SW. The emitter of the transistor Q1 is connected to the positive electrode of the load (device) 2, and the negative electrode of the DC power source 1 and the load 2 negative electrodes are connected. One end of the resistor R1 is connected to the collector of the transistor Q1, and the other end of the resistor R1 is connected to the base of the transistor Q1. One end of the resistor R2 is connected to the base of the transistor Q1, and the other end of the resistor R2 is connected to the emitter of the transistor Q1. A capacitor C1 is connected in parallel with the resistor R2.

  The transistor Q1, resistors R1, R2 and the capacitor C1 constitute an inrush current reduction circuit, and the resistors R1, R2 and the capacitor C1 constitute a current detection circuit.

  Now, in FIG. 2, when the switch SW is turned on from off, an inrush current tends to flow through the load 2. At this time, first, charging of the capacitor C1 starts from the DC power source 1 via the resistor R1. At the beginning of charging, since the potential difference between both ends of the capacitor C1, that is, the base voltage of the transistor Q1 is small and the base current is also small, the bias of the transistor Q1 is shallow and the transistor Q1 is cut off.

  As the charging continues, the base current of the transistor Q1 becomes large, that is, the bias of the transistor Q1 becomes deep and the current starts to flow through the transistor Q1, but at that time, the inrush current flowing through the transistor Q1 is sufficiently small and the load 2 The current of is also small. Therefore, the maximum value of the current to the load 2 can be made lower than when the switch SW and the load 2 are directly connected.

  Note that the collector-emitter voltage of the transistor Q1 when the steady current is supplied to the load 2 is turned on with respect to the steady current, that is, the base-emitter voltage and the base current are sufficiently large. The resistance values of the resistors R1 and R2 are set.

[Third Embodiment]
FIG. 3 is a circuit diagram of an example including an inrush current reduction circuit according to the third embodiment.

  Here, the same reference numerals are given to those having the same functions as those in the first and second embodiments.

  One pole of the AC power supply 1 is connected to the anode of the diode D1 via the switch SW, the cathode of the diode D1 is connected to the drain of the transistor Q1, which is an N-channel MOSFET, and the source of the transistor Q1 is connected to the resistor R3. The other end of the resistor R3 is connected to one pole of the load (device) 2, and the other pole of the DC power source 1 and the other pole of the load 2 are connected. One end of the resistor R1 is connected to the drain of the transistor Q1, and the other end of the resistor R1 is connected to the gate of the transistor Q1. One end of the resistor R2 is connected to the gate of the transistor Q1, and the other end of the resistor R2 is connected to the other end of the resistor R3. A capacitor C1 is connected in parallel with the resistor R2.

  The other pole of the AC power supply 1 is connected to the anode of the diode D2 via the load 2, the cathode of the diode D2 is connected to the drain of the transistor Q2, which is an N-channel MOSFET, and the source of the transistor Q2 is connected to the resistor R13. The other end of the resistor R13 is connected to one pole of the AC power supply 1 via the switch SW. One end of the resistor R11 is connected to the drain of the transistor Q2, and the other end of the resistor R11 is connected to the gate of the transistor Q2. One end of the resistor R12 is connected to the gate of the transistor Q2, and the other end of the resistor R12 is connected to the other end of the resistor R13. A capacitor C11 is connected in parallel with the resistor R12.

  The transistor Q1, resistors R1, R2, and R3 and the capacitor C1 constitute an inrush current reduction circuit, and the resistors R1, R2, R3, and the capacitor C1 constitute a current detection circuit.

  The inrush current reduction circuit, transistor Q2, resistors R11, R12, R13, and capacitor C11 constitute an inrush current reduction circuit, and resistors R11, R12, R13, and capacitor C11 constitute a current detection circuit.

  Now, in FIG. 3, when the voltage of the pole on the switch SW side of the AC power supply 1 is higher than the voltage of the pole on the load 2 side, an inrush current flows through the load 2 when the switch SW is turned on. To do. At this time, first, charging of the capacitor C1 starts from the AC power source 1 via the diode D1 and the resistor R1.

  At the beginning of charging, since the potential difference across the capacitor C1 is small and the gate voltage of the transistor Q1 is also small, the bias of the transistor Q1 is shallow and the transistor Q1 is cut off.

  As the charging continues, the gate voltage of the transistor Q1 increases, that is, the bias of the transistor Q1 becomes deep, and the current starts to flow through the transistor Q1, but at that time, the current flowing through the transistor Q1 is sufficiently small, The current is also small. Therefore, the maximum value of the current to the load 2 can be made lower than when the switch SW and the load 2 are directly connected.

  In addition, in a period in which a steady current is supplied to the load 2 and the voltage of the pole on the switch SW side of the AC power source 1 is higher than the voltage of the pole on the load 2 side, the drain-source voltage of the transistor Q1 is The resistance values of the resistor R1, the resistor R2, and the resistor R3 are set so as to be in an on state with respect to the steady current, that is, the gate-source voltage is sufficiently large, so that the capacitor C1 is not discharged during the opposite phase period. The capacitance of the capacitor C1 and the resistance values of the resistors R1 and R2 are set.

  Further, when a large current flows through the resistor R3, the voltage across the resistor R3 increases, so that the bias of the transistor Q1 can be made shallower by the resistor R3. Further, the resistance value of the resistors R1 and R2 can be easily set by the resistor R3.

  In addition, the transistor Q2 can be protected by blocking the reverse current by the diode D2.

  Now, when the voltage at the pole on the load 2 side of the AC power supply 1 is higher than the voltage at the pole on the switch SW side, an inrush current will flow through the load 2 when the switch SW is turned on. At this time, first, charging of the capacitor C11 is started from the AC power source 1 through the diode D2 and the resistor R11. At the beginning of charging, since the potential difference between both ends of the capacitor C11 is small and the gate voltage of the transistor Q2 is also small, the bias of the transistor Q2 is shallow and the transistor Q2 is cut off.

  As the charging continues, the gate voltage of the transistor Q2 increases, that is, the bias of the transistor Q2 deepens, and a current begins to flow through the transistor Q2. At that time, the inrush current flowing through the transistor Q2 is sufficiently small, and the load 2 The current of is also small. Therefore, the maximum value of the current to the load 2 can be made lower than when the switch SW and the load 2 are directly connected.

  In addition, during the period in which steady current is supplied to the load 2 and the voltage of the pole on the load 2 side of the AC power supply 1 is higher than the voltage of the pole on the switch SW side, the drain-source voltage of the transistor Q2 is The resistance values of the resistor R11, the resistor R12, and the resistor R13 are set so as to be in an on state with respect to the steady current, that is, the gate-source voltage is sufficiently large, and the capacitor C11 is not discharged in the opposite phase period. The capacitance of the capacitor C11 and the resistance values of the resistors R11 and R12 are set.

  Further, when a large current flows through the resistor R13, the voltage across the resistor R13 increases, so that the bias of the transistor Q2 can be made shallower by the resistor R13. Further, the resistance value of the resistors R11 and R12 can be easily set by the resistor R13.

  In addition, the transistor Q2 can be protected by blocking the reverse current by the diode D2.

  Even when a forward diode is used instead of the resistor R3 and the resistor R13, the bias of the transistors Q1 and Q2 can be reduced, so that the same effect can be obtained. If the bias can be set only by the resistors R11 and R12, these resistors and forward diodes need not be used. These resistors and forward diodes may be used in the first and second embodiments.

  In the third embodiment, the transistor Q1 that is an N-channel MOSFET may be an NPN bipolar transistor.

[Fourth Embodiment]
FIG. 4 is a circuit diagram of an example including the inrush current reduction circuit according to the fourth embodiment.

  Here, components having the same functions as those in the first, second, and third embodiments are given the same reference numerals.

  In the fourth embodiment, an inrush current reduction circuit surrounded by a dotted line in FIG. 3 is inserted into each line between the three-link switch SW connected to the three-phase AC power source 1 and the three-phase load 2.

  When the three-link switch SW is turned on from off, as in the third embodiment, there is a possibility that an inrush current in one direction and an inrush current in the opposite direction occur in each line. These inrush currents can be reduced by the operation of the inrush current reducing circuit described in the third embodiment, and the same operational effects as those of the third embodiment can be obtained.

  As mentioned above, although embodiment of this invention was described, in these embodiment, even if the load 2 has inductivity and capacitive property, there is no difference in the effect.

  In these embodiments, when the switch SW is turned off, the capacitor is discharged. Therefore, when the switch SW is turned on again, the same effect as when the switch SW is turned on first is obtained. .

  In these embodiments, N-channel MOSFETs and NPN bipolar transistors are used, but P-channel MOSFETs and PNP bipolar transistors may be used. Further, the semiconductor bias may be controlled using the amount of light or the pulse width of light. Other semiconductors may be used as long as the depth of the bias can be controlled by voltage or current.

  In these embodiments, capacitors are used, but other elements having a capacitance component may be used. Moreover, although resistance was used, you may use the other element which has a resistance component.

It is a circuit diagram of the Example containing the inrush current reduction circuit which concerns on 1st Embodiment. It is a circuit diagram of the Example containing the inrush current reduction circuit which concerns on 2nd Embodiment. It is a circuit diagram of the Example containing the inrush current reduction circuit which concerns on 3rd Embodiment. It is a circuit diagram of the Example containing the inrush current reduction circuit which concerns on 4th Embodiment.

Explanation of symbols

1 Power supply 2 Load Q1, Q2 Transistors R1, R2, R3, R11, R12, R13 Resistors C1, C11 Capacitor SW switch

Claims (6)

A semiconductor element inserted in the current path from the power source to the load;
A current detection circuit connected in parallel to the semiconductor element,
A circuit node in the current detection circuit is connected to a bias control point of the semiconductor element;
The inrush current flowing through the current path is drawn to the current detection circuit, the bias voltage is a voltage of the bias control point a rush current reduction circuit so as to rise,
The current detection circuit includes:
A capacitor connected to the bias control point and charged by the drawn inrush current to increase the bias voltage;
A resistor connected in parallel to the capacitor
An inrush current reduction circuit characterized by that. An inrush current reduction circuit comprising an element for blocking reverse current at a location where inrush current flows in the inrush current reduction circuit according to claim 1, and the same inrush current reduction circuit as the inrush current reduction circuit, and connected in parallel in the reverse direction. An inrush current reduction circuit comprising: an inrush current reduction circuit. An inrush current reduction circuit comprising the inrush current reduction circuit according to claim 2 in each line of a three-phase AC power source. An element to be inserted at a location where an inrush current flows, the element comprising: an element that reduces the bias voltage of the semiconductor element in accordance with a change in voltage across the element when the inrush current flows. The inrush current reduction circuit according to any one of 1 to 3 . The semiconductor element is an N-channel MOSFET, and the current detection circuit includes a resistor connected between the drain and gate of the N-channel MOSFET, a resistor connected between the gate and source of the N-channel MOSFET, and the resistor in parallel. rush current reduction circuit according to any one of claims 1 to 4, characterized in that it is configured to include a capacitor. The semiconductor element is an NPN bipolar transistor, and the current detection circuit includes a resistor connected between the collector and the base of the NPN bipolar transistor, a resistor connected between the base and the emitter of the NPN bipolar transistor, and the resistor in parallel. rush current reduction circuit according to any one of claims 1 to 4, characterized in that it is configured to include a capacitor.

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