JP4355683B2 - Pseudo capacitance circuit - Google Patents

Description

  The present invention relates to a pseudo capacitance circuit.

  Capacitance elements used for improving the power factor of commercial power grids are electrode plate materials and the distance between electrodes separated by a dielectric substrate to prevent dielectric breakdown so that they can be applied to high voltage and large currents. The mass and volume are large because the electrode plate area for securing the capacitance is taken into consideration.

  Furthermore, even if high-frequency noise occurs in an environment such as a commercial power supply network, the power factor can be improved, and the mass and volume can be reduced. Application is expected. However, as a pseudo capacitance circuit, a circuit using a mirror effect is known in the field of weak electricity handling communication signals and the like, but a power source for that purpose is necessary, and it is not suitable for a high power circuit.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a pseudocapacitance circuit that can reduce the mass and volume and does not require a power source.

In order to solve the above problems, the present invention of claim 1 is directed to a semiconductor element, two resistive elements connected to the semiconductor element to determine a fixed bias condition of the semiconductor element, and the resistive element Two circuits each including a circuit including a capacitive element connected in parallel to one of the semiconductor elements and a reverse current preventing semiconductor element connected in series to the circuit for preventing a reverse current to the semiconductor element, with a pseudo capacitance circuit, characterized in that the direction of reverse current direction and the other of the circuit of reverse current one of the circuit and the circuit in parallel is connected to have opposite directions to each other and solutions.

According to a second aspect of the present invention, the semiconductor element is an N-channel MOSFET, and one resistive element and a capacitive element are connected in parallel between the drain and gate of the N-channel MOSFET, and the other resistive element is The pseudo-capacitance circuit according to claim 1, which is connected in parallel between the gate and source of an N-channel MOSFET.
According to the third aspect of the present invention, the collector and emitter of the output side phototransistor of the photocoupler are connected between the drain and gate of the MOSFET which is the semiconductor element, and the amplitude, frequency, and duty ratio of the pulse signal applied to the photocoupler are reduced. 3. The pseudo-capacitance circuit according to claim 1, wherein the resistance value of the output side phototransistor is changed by controlling at least one of the elements.
According to a fourth aspect of the present invention, the collector and emitter of the output side phototransistor of the photocoupler are connected between the drain and gate of the MOSFET which is the semiconductor element, and the amplitude, frequency and DC component of the sine wave signal applied to the photocoupler. 3. The pseudo-capacitance circuit according to claim 1, wherein the resistance value of the output side phototransistor is changed by controlling at least one of the elements.

  According to the present invention, it is possible to provide a pseudo capacitance circuit that can reduce the mass and volume and does not require a power source.

  Embodiments of a pseudo capacitance circuit according to the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a circuit diagram of a pseudo capacitance circuit 1 according to the first embodiment.

  The terminal A and the anode of the diode D1 are connected, and the cathode of the diode D1 and the drain of the transistor Q1, which is a power type N-channel MOSFET, are connected. The source of the transistor Q1 and the terminal B are connected. A resistor R1 and a capacitor C1 are connected in parallel between the drain and gate of the transistor Q1, and a resistor R2 is connected in parallel between the gate and source of the transistor Q1.

  The terminal B and the anode of the diode D2 are connected, and the cathode of the diode D2 and the drain of the transistor Q2 which is a power type N-channel MOSFET are connected. The source of the transistor Q2 and the terminal A are connected. A resistor R11 and a capacitor C2 are connected in parallel between the drain and gate of the transistor Q2, and a resistor R12 is connected in parallel between the gate and source of the transistor Q2.

  Next, the operation of the pseudo capacitance circuit 1 will be described.

  When the potential at the terminal A is higher than the potential at the terminal B, the diode D2 blocks the current that is about to flow to the transistor Q2, while the capacitor C1 starts to be charged via the diode D1 and the resistor R2. At the beginning of charging, since the potential difference between both ends of the capacitor C1 is small and the voltage between the gate and the source of the transistor Q1 is large, the bias of the transistor Q1 is deep, the transistor Q1 becomes conductive, and the current value thereof is between the resistors R1 and R2. It depends on the ratio (fixed bias condition). As the charging continues, the potential difference between both ends of the capacitor C1 increases, the voltage between the gate and source of the transistor Q1 decreases, that is, the bias of the transistor Q1 becomes shallow, the current of the transistor Q1 decreases, and eventually cuts off.

  In this manner, a current in the direction from the terminal A to the terminal B flows transiently, and eventually cuts off.

  On the contrary, when the potential at the terminal B is higher, the diode D1 blocks the current that is about to flow to the transistor Q1, while the capacitor C2 starts to be charged via the diode D2 and the resistor R12. At the beginning of charging, since the potential difference between both ends of the capacitor C2 is small and the voltage between the gate and the source of the transistor Q2 is large, the bias of the transistor Q2 is deep, the transistor Q2 becomes conductive, and the current value thereof is between the resistors R1 and R2. It depends on the ratio (fixed bias condition). As the charge continues, the potential difference between both ends of the capacitor C2 increases, the gate-source voltage of the transistor Q2 decreases, that is, the bias of the transistor Q2 becomes shallow, the current of the transistor Q2 decreases, and eventually cuts off.

  In this manner, a current in the direction from the terminal B to the terminal A flows transiently and eventually cuts off.

  That is, the pseudo capacitance circuit 1 can be used for a DC circuit and an AC circuit, and in either case, an operation is performed in which a current is passed transiently and cut off steadily.

[Second Embodiment]
FIG. 2 is a circuit diagram of a pseudo capacitance circuit 1A according to the second embodiment.

  The pseudo capacitance circuit 1 </ b> A is obtained by changing a part of the pseudo capacitance circuit 1. In the pseudo capacitance circuit 1A, the collector of the output side phototransistor of the photocoupler PC1 is connected to the drain of the transistor Q1, the emitter of the output side phototransistor is connected to the gate of the transistor Q1, and a pulse power source is connected between each input terminal of the photocoupler PC1. 11 is connected. In the pseudo capacitance circuit 1A, the collector of the output side phototransistor of the photocoupler PC2 is connected to the drain of the transistor Q2, the emitter of the output side phototransistor is connected to the gate of the transistor Q2, and between the input terminals of the photocoupler PC2. A pulse power supply 21 is connected. By providing such a configuration, the pseudo capacitance circuit 1A does not include the resistor R1 and the resistor R11. Other portions are the same as those of the pseudo capacitance circuit 1.

  The pseudo capacitance circuit 1A controls at least one of the amplitude, frequency, and duty ratio of the pulse signal supplied from the pulse power supply 11 or the pulse power supply 21 to the photocoupler PC1 or the photocoupler PC2, thereby enabling the photocoupler PC1 or the photocoupler PC2. Since the resistance value (output resistance) of the output side phototransistor can be changed, the fixed bias conditions of the transistor Q1 and the transistor Q2 can be changed. Therefore, the characteristics of the pseudo capacitance circuit 1A can be changed. In the second embodiment, the same effect can be obtained even in a circuit in which one of the resistor R1 and the resistor R11 used in the first embodiment is left and a photocoupler and a pulse power supply are not provided in place of the resistor R1. can get. Further, a similar effect can be obtained whether or not the photocoupler and the pulse power source are provided in place of at least one of the resistor R2 and the resistor R12, and the resistor R1 and the resistor R11 are replaced with the photocoupler and the pulse power source. The waveform of the pulse signal applied to the photocoupler may be a waveform having an arbitrary shape such as a rectangular wave, a triangular wave, a trapezoidal wave, or a sawtooth wave. Further, a waveform obtained by combining these waveforms may be used.

[Third Embodiment]
FIG. 3 is a circuit diagram of a pseudo capacitance circuit 1B according to the third embodiment.

  The pseudo capacitance circuit 1B is obtained by replacing the pulse power source 11 and the pulse power source 21 of the pseudo capacitance circuit 1A with a sine wave signal power source 11a and a sine wave signal power source 21a that respectively generate a sine wave signal.

  In the pseudo capacitance circuit 1B, the photocoupler PC1 or the sine wave signal power source 11a or the sine wave signal power source 21a is controlled by controlling at least one of the amplitude, frequency, and DC component of the sine wave signal applied to the photocoupler PC1 and the photocoupler PC2. Since the resistance value (output resistance) of the output circuit of the photocoupler PC2 can be changed, the fixed bias conditions of the transistor Q1 and the transistor Q2 can be changed. Therefore, the characteristics of the pseudo capacitance circuit 1A can be changed. In the third embodiment, the same operation can be achieved as a circuit in which one of the resistor R1 and the resistor R11 used in the first embodiment is left and a photocoupler and a sine wave signal power source are not provided instead. An effect is obtained. In addition, a photocoupler and a sine wave signal power supply that replace at least one of the resistor R2 and the resistor R12 are provided, and whether or not the resistor R1 and the resistor R11 are replaced with the photocoupler and the sine wave signal power supply can have the same effect. It is done.

  FIG. 4 is a characteristic diagram of the N-channel MOSFET prepared to show that the drain current can be controlled by the gate-source voltage obtained by dividing the source-drain voltage as described above. The characteristics of the drain-source voltage VDS with respect to the voltage VGS are shown.

  According to FIG. 4, when the voltage VGS is increased from 0V, the drain current ID starts flowing at a certain point. If the voltage VDS at this time is made higher than the voltage VGS, that is, if the hatched area in FIG. 2 is used, then a high transfer admittance (a value obtained by dividing the rate of change of the drain current ID by the rate of change of the voltage VGS). can get. Further, when the voltage VGS is lowered, the drain current ID does not flow at a certain point. Therefore, by changing the voltage VGS obtained by dividing the voltage VDS, the conduction / non-conduction and the magnitude of the current ID can be controlled.

  FIG. 5 is a diagram illustrating an example of an implementation of the pseudo capacitance circuit of each embodiment.

  The output side of the transformer 3 in the substation 2 is connected to a load 4 (inverter device, household electrical appliance, industrial machine, etc.) via a power transmission line or indoor wiring. In this substation 2, a terminal A such as a pseudo capacitance circuit 1 is connected to the output side of the transformer 3, and a terminal B of the pseudo capacitance circuit 1 is grounded.

  The pseudo-capacitance circuit 1 or the like prevents a malfunction of the load 4 due to this current by flowing a transient high-frequency noise current generated on the output side of the transformer 3 to the ground, while at the same time preventing a current at a constant commercial frequency. On the other hand, this current is supplied to the load 4 by cutting off.

  Furthermore, since the pseudo capacitance circuit 1 or the like does not use an inductance, the stored magnetic energy is not released or resonated.

  Although the pseudo capacitance circuit has been described above, an NPN bipolar transistor, a P channel MOSFET, a PNP bipolar transistor, an IGBT (Insurated Gate Bipolar Transistor), a GTBT (Grounded trench mos structure assisted bipolar mode JFET.), Etc. are used instead of the N channel MOSFET. It may be used.

1 is a circuit diagram of a pseudo capacitance circuit according to a first embodiment. FIG. It is a circuit diagram of the pseudo capacitance circuit which concerns on 2nd Embodiment. It is a circuit diagram of the pseudo capacitance circuit which concerns on 3rd Embodiment. It is a characteristic view of N channel MOSFET used in order to show that drain current control is possible with the gate-source voltage which divided the source-drain voltage. It is a figure which shows an example of the embodiment about a pseudo capacitance circuit.

Explanation of symbols

1, 1A, 1B Pseudocapacitance circuit 11, 21 Pulse power supply 11a, 21a Sine wave power supply Q1, Q2 Transistors R1, R2, R11, R12 Resistor C1, C2 Capacitor D1, D2 Diode (reverse current prevention semiconductor element)
PC1, PC2 Photocoupler

Claims (4)

Semiconductor elements,
Two resistive elements connected to the semiconductor element to determine a fixed bias condition of the semiconductor element;
And a circuit comprising a capacitive element connected in parallel to one of the resistive elements;
2 circuits comprising a reverse current prevention semiconductor element connected in series to the circuit for preventing reverse current to the semiconductor element,
Pseudo capacitance circuit, characterized in that the reverse current of Orientation and other of the circuit of reverse current one of the circuit and the second circuit in parallel is connected to have opposite directions to each other.   The semiconductor element is an N-channel MOSFET, one resistive element is connected in parallel between the drain and gate of the N-channel MOSFET, and the other resistive element and capacitive element are the gate-source of the N-channel MOSFET. The pseudo capacitance circuit according to claim 1, wherein the pseudo capacitance circuit is connected in parallel. The collector and emitter of the output side phototransistor of the photocoupler are connected between the drain and gate of the MOSFET which is the semiconductor element, and at least one of the amplitude, frequency and duty ratio of the pulse signal applied to the photocoupler is controlled. 3. The pseudo capacitance circuit according to claim 1, wherein the resistance value of the output side phototransistor is changed. The collector and emitter of the output side phototransistor of the photocoupler are connected between the drain and gate of the MOSFET which is the semiconductor element, and at least one element among the amplitude, frequency, and DC component of the sine wave signal to be given to the photocoupler. 3. The pseudo capacitance circuit according to claim 1, wherein the resistance value of the output side phototransistor is changed by control.

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